A 30 GS/s 4-Bit Binary Weighted DAC in SiGe BiCMOS Technology

Halder, Samiran and Gustat, Hans

IEEE Bipolar/BiCMOS Circuits and Technology Meeting, 2007

Sept. 30 Oct. 2 pp.46 - 49.

Speaker: Juan-Zhi Lee

OUTLINE

1.INTRODUCTION

2.DAC ARCHITECTURE

3.CIRCUIT IMPLEMENTION

4.RESULTS AND DISCUSSIONS

5.CONCLUSION

INTRODUCTION In this paper an attempt has been made to serve the

applications by developing a low-power low-resolution binary weighted DAC with 30GS/s sampling rate.

This DAC can also be used as a sub-DAC for implementing the part of a segmented 8-bit current steering DAC with 20GS/s or more sampling rate.

DAC ARCHITECTURE In the present application a binary weighted architecture is

chosen as the resolution is only 4 bit. The block diagram of the presented DAC is shown in Fig.1. Unlike the common binary weighted DAC, all of the

current sources in this work have same current. This is a strong advantage in terms of sampling rate,

because it allows to operate the LSB cells with full current and speed.

Compensation resistors are used to create an equal resistive load at the output of the each current switch.

CIRCUIT IMPLEMENTION The DAC is implemented in a 0.25µm SiGe BiCMOS tech

nology. The minimum emitter size of the HBT is 0.21x0.84µm2 and

the fT ,fMAX are both 190GHz. This technology also provides poly resistors and MIM capa

citors in a five-layer metallization system. In the time critical signal paths, minimum size HBTs have

been used for high speed and minimum parasitic capacitance load.

Schematic diagrams of the novel current switch concept used in this work are presented in Fig.2a.

A simple differential pair is used as the current switch. The current source is implemented by a cascode stage.

An isolated nMOS transistor is used as the main current source and the cascode device is an HBT transistor.

To reduce this effect a capacitor (Cs) is used across the drain and source of the M1, which has a low-pass effect and substantially reduces the spike energy.

Fig.2b shows the schematic of one branch of the output load for the DAC.

Additional resistors are used to equalize the resistive load at the input of each current switch. Unlike the conventional binary weighted DAC, this new

approach allows to operate all of the current sources with the same current and load impedance.

The proper timing alignment of the current switches has

great impact to the dynamic performance of the DAC. Unequal delay among the current switches would result in

higher current glitches at the output and the SFDR of the

DAC would be reduced. Special attention has been paid to make the signal paths fro

m the retiming DFFs to the current switches as short as possible and equal in length, reducing the timing skew for the current switches.

The retiming DFF is implemented with a commonly used ECL DFF. A differential amplifier at the output of the DFF is used to ensure the steep rising and falling edges.

In Fig. 3 the layout of the retiming DFF and the current switch is presented. Thus the layout has been designed

with focus on low wiring capacitance and high symmetry

RESULTS AND DISCUSSIONS In Fig. 4. the measured INL and DNL of the 4-bit DAC

is plotted. It achieved INL and DNL of 0.49LSB and

0.57LSB respectively.

Fig 5a shows the one of the differential output of the DAC for an input pattern corresponding to a sinusoidal function.

The constructed sinusoidal has a frequency of 560 MHz. The DAC clock is 30GHz.

A full-swing step response of the DAC is presented in Fig. 5b with the input data rate of 500MHz and clock rate of 15GHz.

For the rise time measurement a reconstructed saw-tooth signal is used. In Fig. 6a such a reconstructed saw-tooth signal for the clock rate of 22GHz and 500MHz of input data rate is shown.

The zoomed portion of the full-scale transition is presented in Fig. 6b. From the rise time measurement (Fig. 6b) the output bandwidth of the DAC is calculated to be 3.85 GHz.

CONCLUSION In this paper a binary weighted current steering DAC is pre

sented which can be used as a standalone DAC as well as a sub-DAC for a higher resolution segmented DAC. Unlike conventional binary weighted DACs, the weighting

function is implemented in the load resistor instead of the current sources.

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