A Greatest Common Divisor(GCD) Processor
Euclid’s GCD algorithm
1: int x, y;2: x = x_input;3: y = y_input;4: while (x != y) 5: {6: if (x<y)7: y = y-x;8: else9: x = x-y;10: }11: output = x;
GCD(9,15)x = 9y = 15y = 15 – 9 = 6x = 9 – 6 = 3y = 6 – 3 = 3
GCD(9,15) = 3
ALU
Alusel(2:0) Function Output 0 0 0 Pass A A 0 0 1 Addition A + B 0 1 0 Subtraction-1 A – B 0 1 1 Subtraction-2 B – A 1 0 0 Invert NOT A 1 0 1 And A AND B 1 1 0 Or A OR B 1 1 1 Xor A XOR B
1: int x, y;2: x = x_input;3: y = y_input;4: while (x != y) 5: {6: if (x<y)7: y = y-x;8: else9: x = x-y;10: }11: output = x;
msel(1:0)
1001 clrclkr0ld
R1 clrclkr1ld
W clrclkwld
ALU alusel(2:0)B A
Y
PAPB
M10123
PDPC
PE
000
0
00
1
0
1111
1001
ALU: Pass AR0 1001
clrclk
stld N Z V C
40
1: int x, y;2: x = x_input;3: y = y_input;4: while (x != y) 5: {6: if (x<y)7: y = y-x;8: else9: x = x-y;10: }11: output = x;
msel(1:0)
1001 clrclkr0ld
1111 clrclkr1ld
W clrclkwld
ALU alusel(2:0)B A
Y
PAPB
M10123
PDPC
PE
000
0
01
0
1
1111
1001
ALU: Pass AR1 1111
clrclk
stld N Z V C
40
1: int x, y;2: x = x_input;3: y = y_input;4: while (x != y) 5: {6: if (x<y)7: y = y-x;8: else9: x = x-y;10: }11: output = x;
msel(1:0)
1001 clrclkr0ld
1111 clrclkr1ld
1001 clrclkwld
ALU alusel(2:0)B A
Y
PAPB
M10123
PDPC
PE
000
1
11
0
0
xxxx
xxxx
ALU: Pass AW R0
clrclk
stld N Z V C
40
1: int x, y;2: x = x_input;3: y = y_input;4: while (x != y) 5: {6: if (x<y)7: y = y-x;8: else9: x = x-y;10: }11: output = x;
msel(1:0)
1001 clrclkr0ld
1111 clrclkr1ld
0110 clrclkwld
ALU alusel(2:0)B A
Y
PAPB
M10123
PDPC
PE
010
1
10
0
0
xxxx
xxxx
ALU: A - BW R1 - W
clrclk
stld N Z V C
41
1: int x, y;2: x = x_input;3: y = y_input;4: while (x != y) 5: {6: if (x<y)7: y = y-x;8: else9: x = x-y;10: }11: output = x;
msel(1:0)
1001 clrclkr0ld
1111 clrclkr1ld
0110 clrclkwld
ALU alusel(2:0)B A
Y
PAPB
M10123
PDPC
PE
010
1
10
0
0
xxxx
xxxx
ALU: A - BW R1 - W
clrclk
stld N Z V C
41
1: int x, y;2: x = x_input;3: y = y_input;4: while (x != y) 5: {6: if (x<y)7: y = y-x;8: else9: x = x-y;10: }11: output = x;
msel(1:0)
1001 clrclkr0ld
1111 clrclkr1ld
1001 clrclkwld
ALU alusel(2:0)B A
Y
PAPB
M10123
PDPC
PE
000
1
11
0
0
xxxx
xxxx
ALU: Pass AW R0
clrclk
stld N Z V C
40
1: int x, y;2: x = x_input;3: y = y_input;4: while (x != y) 5: {6: if (x<y)7: y = y-x;8: else9: x = x-y;10: }11: output = x;
msel(1:0)
1001 clrclkr0ld
0110 clrclkr1ld
1001 clrclkwld
ALU alusel(2:0)B A
Y
PAPB
M10123
PDPC
PE
010
0
10
0
1
xxxx
xxxx
ALU: A - BR1 R1 - W
clrclk
stld N Z V C
41
1: int x, y;2: x = x_input;3: y = y_input;4: while (x != y) 5: {6: if (x<y)7: y = y-x;8: else9: x = x-y;10: }11: output = x;
msel(1:0)
1001 clrclkr0ld
0110 clrclkr1ld
1001 clrclkwld
ALU alusel(2:0)B A
Y
PAPB
M10123
PDPC
PE
000
1
11
0
0
xxxx
xxxx
ALU: Pass AW R0
clrclk
stld N Z V C
40
1: int x, y;2: x = x_input;3: y = y_input;4: while (x != y) 5: {6: if (x<y)7: y = y-x;8: else9: x = x-y;10: }11: output = x;
msel(1:0)
0011clr
clkr0ld
0110clr
clkr1ld
1001clr
clkwld
ALU alusel(2:0)B A
Y
PAPB
M10123
PDPC
PE
011
0
10
1
0
xxxx
xxxx
ALU: B - AR0 W - R1
clr
clkstld N Z V C
41
1: int x, y;2: x = x_input;3: y = y_input;4: while (x != y) 5: {6: if (x<y)7: y = y-x;8: else9: x = x-y;10: }11: output = x;
msel(1:0)
0011 clrclkr0ld
0110 clrclkr1ld
0011 clrclkwld
ALU alusel(2:0)B A
Y
PAPB
M10123
PDPC
PE
000
1
11
0
0
xxxx
xxxx
ALU: Pass AW R0
clrclk
stld N Z V C
40
1: int x, y;2: x = x_input;3: y = y_input;4: while (x != y) 5: {6: if (x<y)7: y = y-x;8: else9: x = x-y;10: }11: output = x;
msel(1:0)
0011 clrclkr0ld
0011 clrclkr1ld
0011 clrclkwld
ALU alusel(2:0)B A
Y
PAPB
M10123
PDPC
PE
010
1
10
0
1
xxxx
xxxx
ALU: A - BR1 R1 - W
clrclk
stld N Z V C
41
1: int x, y;2: x = x_input;3: y = y_input;4: while (x != y) 5: {6: if (x<y)7: y = y-x;8: else9: x = x-y;10: }11: output = x;
msel(1:0)
0011 clrclkr0ld
0011 clrclkr1ld
0011 clrclkwld
ALU alusel(2:0)B A
Y
PAPB
M10123
PDPC
PE
000
1
11
0
0
xxxx
xxxx
ALU: Pass AW R0
clrclk
stld N Z V C
40
GCD
GCDDatapath
GCDControl Unit
ZC
clr clk clr clk
r0ldr1ldwldstldmsel(1:0)alusel(2:0)
PE
PA
PB
gcdpath.vhd-- Title: GCD Datapathlibrary IEEE;use IEEE.STD_LOGIC_1164.all;use IEEE.std_logic_unsigned.all;use work.gcd_components.all;
entity GCDpath is generic(width:positive); port(
PA: in STD_LOGIC_VECTOR (width-1 downto 0); PB: in STD_LOGIC_VECTOR (width-1 downto 0); alusel: in STD_LOGIC_VECTOR (2 downto 0);
msel: in STD_LOGIC_VECTOR (1 downto 0);r0ld, r1ld, stld, wld: in STD_LOGIC;clr, clk: in STD_LOGIC;C, Z: out STD_LOGIC;
PE: out STD_LOGIC_VECTOR (width-1 downto 0)
);end GCDpath;
architecture GCDpath_arch of GCDpath is
signal y, a, PEs, PCs, PDs: std_logic_vector(width-1 downto 0);signal s, status: std_logic_vector(3 downto 0);constant bus_width: integer := 4;constant status_width: integer := 4;
begin
gcdpath.vhd (cont.)
msel(1:0)
R0 clrclkr0ld
R1 clrclkr1ld
W clrclkwld
ALU alusel(2:0)B A
Y
PAPB
M10123
PDPC
PE
Input
Input
clrclk
stld N Z V C
4
y
as
alu1: alu generic map(width => bus_width) port map (a => a, b => PEs, alusel => alusel, status => s, y => y); R0: reg generic map(width => bus_width) port map (d => y, load =>r0ld, clr => clr, clk =>clk, q => PDs); R1: reg generic map(width => bus_width) port map (d => y, load => r1ld, clr => clr, clk =>clk, q => PCs);
stat: reg generic map(width => status_width) port map (d => s, load =>stld, clr => clr, clk =>clk, q => status);
gcdpath.vhd (cont.)
msel(1:0)
R0 clrclkr0ld
R1 clrclkr1ld
W clrclkwld
ALU alusel(2:0)B A
Y
PAPB
M10123
PDPC
PE
Input
Input
clrclk
stld N Z V C
4
a
y
s
W: reg generic map(width => bus_width) port map (d => y, load => wld, clr => clr, clk =>clk, q => PEs);
M1: mux4g generic map(width => bus_width) port map (a => PA, b => PB, c => PCs, d => PDs, sel => msel, y => a); C <= status(0); Z <= status(2); PE <= PEs; end GCDpath_arch;
gcdpath.vhd (cont.)
msel(1:0)
R0 clrclkr0ld
R1 clrclkr1ld
W clrclkwld
ALU alusel(2:0)B A
Y
PAPB
M10123
PDPC
PE
Input
Input
clrclk
stld N Z V C
4
a
y
s
GCD
GCDDatapath
GCDControl Unit
ZC
clr clk clr clk
r0ldr1ldwldstldmsel(1:0)alusel(2:0)
PE
PA
PB
s0
s1
s2
s3
s4
s5 s6
s7
R0 x
R1 y
W R0
W R1 - W
C = 1W R0
R1 R1 - W
Z = 1
C = 0W R0
W R0
R0 W - R1
W R0
Done
1: int x, y;2: x = x_input;3: y = y_input;4: while (x != y) 5: {6: if (x<y)7: y = y-x;8: else9: x = x-y;10: }11: output = x;
VHDLMealy Machine
Stat
e R
egis
ter
C1
x(t)
s(t+1)
s(t)z(t)
clk
init
present statepresent
input
nextstate
C2
process(clk, init)
process(present_state, x)
process(present_state, x)
gcd_control.vhd
-- Title: GCD Control Unitlibrary IEEE;use IEEE.std_logic_1164.all;use IEEE.std_logic_unsigned.all;
entity gcd_control is port ( clr: in STD_LOGIC; clk: in STD_LOGIC; Z: in STD_LOGIC; C: in STD_LOGIC; alusel: out STD_LOGIC_VECTOR (2 downto 0); msel: out STD_LOGIC_VECTOR (1 downto 0); r0ld, r1ld, stld, wld: out STD_LOGIC );end gcd_control;
architecture gcd_control_arch of gcd_control is
type state_type is (s0, s1, s2, s3, s4, s5, s6, s7);
signal current_state, next_state: state_type;
begin statereg: process(clk, clr) -- the state register begin if clr = '1' then current_state <= s0; elsif (clk'event and clk = '1') then current_state <= next_state;
end if; end process statereg;
gcd_control.vhd (cont.)
gcd_control.vhd (cont.)
s0
s1
s2
s3
s4
s5 s6
s7
R0 x
R1 y
W R0
W R1 - W
C = 1W R0
R1 R1 - W
Z = 1
C = 0W R0
W R0
R0 W - R1
W R0
Done
C1: process(current_state, Z, C) begin case current_state is when s0 =>
next_state <= s1; when s1 =>
next_state <= s2; when s2 =>
next_state <= s3; when s3 =>
next_state <= s4; when s4 =>
if Z = '1' then next_state <= s7; elsif C = '1' then
next_state <= s5;else next_state <= s6;
end if;
gcd_control.vhd (cont.)s0
s1
s2
s3
s4
s5 s6
s7
R0 x
R1 y
W R0
W R1 - W
C = 1W R0
R1 R1 - W
Z = 1
C = 0W R0
W R0
R0 W - R1
W R0
Done
when s5 => next_state <= s2;
when s6 => next_state <= s2;
when s7 => next_state <= s7;
end case;end process C1;
gcd_control.vhd (cont.)C2: process(current_state) begin -- Initialize all outputs alusel <= "000"; msel <= "00"; r0ld <= '0'; r1ld <= '0'; stld <= '0'; wld <= '0';
case current_state is when s0 => -- R0 <- x r0ld <= '1' ; r1ld <= '0';
stld <= '1'; wld <= '0'; msel <= "00";
alusel <= "000";
msel(1:0)
R0 clrclkr0ld
R1 clrclkr1ld
W clrclkwld
ALU alusel(2:0)B A
Y
PAPB
M10123
PDPC
PE
Input
Input
clrclk
stld N Z V C
4
a
y
s
gcd_control.vhd (cont.)
when s1 => -- R1 <- Y r0ld <= '0' ; r1ld <= '1';
stld <= '1'; wld <= '0'; msel <= "01";
alusel <= "000";
when s2 => -- W <- R0 r0ld <= '0' ; r1ld <= '0';
stld <= '1'; wld <= '1'; msel <= "11";
alusel <= "000";
when s3 => -- W <- R1 - W r0ld <= '0' ; r1ld <= '0';
stld <= '1'; wld <= '1'; msel <= "10";
alusel <= "010";
msel(1:0)
R0 clrclkr0ld
R1 clrclkr1ld
W clrclkwld
ALU alusel(2:0)B A
Y
PAPB
M10123
PDPC
PE
Input
Input
clrclk
stld N Z V C
4
a
y
s
gcd_control.vhd (cont.)
msel(1:0)
R0 clrclkr0ld
R1 clrclkr1ld
W clrclkwld
ALU alusel(2:0)B A
Y
PAPB
M10123
PDPC
PE
Input
Input
clrclk
stld N Z V C
4
a
y
s
when s4 => -- W <- R0 r0ld <= '0' ; r1ld <= '0';
stld <= '1'; wld <= '1'; msel <= "11";
alusel <= "000";
when s5 => -- R0 <- W - R1 r0ld <= '1' ; r1ld <= '0';
stld <= '1'; wld <= '0'; msel <= "10";
alusel <= "011";
when s6 => -- R1 <- R1 - W r0ld <= '0' ; r1ld <= '1';
stld <= '1'; wld <= '0'; msel <= "10";
alusel <= "010";
gcd_control.vhd (cont.)
msel(1:0)
R0 clrclkr0ld
R1 clrclkr1ld
W clrclkwld
ALU alusel(2:0)B A
Y
PAPB
M10123
PDPC
PE
Input
Input
clrclk
stld N Z V C
4
a
y
s
when s7 => -- W <- R0 r0ld <= '0' ; r1ld <= '0';
stld <= '1'; wld <= '1'; msel <= "11";
alusel <= "000";
when others => null;
end case; end process C2; end gcd_control_arch;
GCD
GCDDatapath
GCDControl Unit
ZC
clr clk clr clk
r0ldr1ldwldstldmsel(1:0)alusel(2:0)
PE
PA
PB
GCDDatapath
GCDControl Unit
ZC
clr clk clr clk
r0ldr1ldwldstld
msel(1:0)alusel(2:0)
PE
PA
PB
-- Title: Greatest Common Divisorlibrary IEEE;use IEEE.STD_LOGIC_1164.all;use IEEE.std_logic_unsigned.all;use work.GCD_components.all;
entity GCD isgeneric(width:positive);port( PA: in STD_LOGIC_VECTOR ((width-1) downto 0); PB: in STD_LOGIC_VECTOR ((width-1) downto 0); clr, clk: in STD_LOGIC;
PE: out STD_LOGIC_VECTOR ((width-1) downto 0)
);end GCD;
GCD.vhd
GCD.vhd (cont.)architecture GCD_arch of GCD is
signal alusel: std_logic_vector(2 downto 0);signal msel: std_logic_vector(1 downto 0);signal C, Z: std_logic;signal r0ld, r1ld, stld, wld: std_logic;
GCDDatapath
GCDControl Unit
ZC
clr clk clr clk
r0ldr1ldwldstld
msel(1:0)alusel(2:0)
PE
PA
PB
GCD.vhd (cont.)
GCDDatapath
GCDControl Unit
ZC
clr clk clr clk
r0ldr1ldwldstld
msel(1:0)alusel(2:0)
PE
PA
PB
begin
U1: gcdpath generic map(width => width) port map (PA => PA, PB => PB, alusel => alusel, msel => msel, r0ld => r0ld, r1ld => r1ld, stld => stld, wld => wld,
clr => clr, clk =>clk, PE => PE, C => C, Z => Z); U2: gcd_control port map (alusel => alusel, msel => msel, C => C, Z => Z, r0ld => r0ld, r1ld => r1ld, stld => stld, wld => wld,
clr => clr, clk => clk);
end GCD_arch;
-- Title: GCD Testlibrary IEEE;use IEEE.STD_LOGIC_1164.all;use IEEE.std_logic_unsigned.all;use work.GCD_components.all;
entity GCDtest is port(
mclk : in STD_LOGIC; SW : in STD_LOGIC_VECTOR(7 downto 0);
BTN: in STD_LOGIC_VECTOR(3 downto 0); LD : out STD_LOGIC_VECTOR(7 downto 0); AtoG : out STD_LOGIC_VECTOR(6 downto 0); AN : out STD_LOGIC_VECTOR(3 downto 0)
);end GCDtest;
GCDtest.vhd
GCDtest.vhd (cont.)
architecture GCDtest_arch of GCDtest is
signal r, p: std_logic_vector(15 downto 0);signal clr, clk, cclk, bnbuf: std_logic;signal clkdiv: std_logic_vector(26 downto 0);
constant bus_width: positive := 4;
begin clr <= BTN(3);
GCDtest.vhd (cont.)
-- Divide the master clock (50Mhz) process (mclk)
begin if mclk = '1' and mclk'Event then
clkdiv <= clkdiv + 1; end if;
end process;
clk <= clkdiv(0); -- 25 MHz
cclk <= clkdiv(17); -- 190 Hz
r(15 downto 4) <= "000000000000";
GCDtest.vhd (cont.)
U1: GCD generic map(width => bus_width) port map (PA => SW(7 downto 4), PB =>SW(3 downto 0),
clr => clr, clk =>clk, PE => r(3 downto 0)); U2: binbcd port map (B => r, P => p); U3: x7segb port map (x => p, cclk => cclk, clr => clr, AtoG => AtoG,
AN => AN);
LD <= SW;
end GCDtest_arch;
s0
s1
s2
s3
s4
s5 s6
s7
R0 x
R1 y
W R0
W R1 - W
C = 1W R0
R1 R1 - W
Z = 1
C = 0W R0
W R0
R0 W - R1
W R0
Done
msel(1:0)
R0 clrclkr0ld
R1 clrclkr1ld
W clrclkwld
ALU alusel(2:0)B A
Y
PAPB
M10123
PDPC
PE
Input
Input
clrclk
stld N Z V C
4
a
y
s