IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 42, NO. 3, MARCH 1995 513

A High Performance Super Self-Aligned 3 V/5 V BiCMOS Technology with Extremely Low

Parasitics for Low-Power Mixed-Signal Applications J. M. Sung, T.-Y. Chiu, Member, IEEE, K. Lau, T. M. Liu, Senior Member, IEEE, V. D. Archer, Member, IEEE,

B. Razavi, Member, IEEE, R. G. Swartz, Fellow, IEEE, F. M. Erceg, J. T. Glick, G. R. Hower, S. A. Krafty, A. J. LaDuca, M. P. Ling, K. G. Moerschel, W. A. Possanza, M. A. Prozonic, and T. P. Long

Absfruct- A high performance BiCMOS technology, BEST- 2 (Bipolar Enhanced super Self-aligned Technology) designed For supporting low-power multiGHz mixed-signal applications is presented. Process modules to produce low parasitic device structures wil l be described. The developed BiCMOS process implemented with 1 pm design rules (0.5 pm as one nesting tolerance) has achieved ft and fmax for npn bipolar (A, = l x 2 pm2) OF 23 GHz and 24 GHz at V,, = 3 V, respectively, with BV,,, 2 5.5 volts, and PVA product of 2400. mica1 measured ECL gate delay is 48 pd37 ps per stage (A, = 1 x 2pm2; 500 mV swing) at 0.6 mA12.1 mA switching currents, and CMOS gate delay (gate oxide = 125 A, L,E = 0.6 pm; &h,nch = 0.45 V; &h,p& = - 0.45 v ) 70 pdstage. BiCMOS phase-locked-loop (emitter width = 1 pm; gate Lee = 0.7 pm) has achieved 6 GHz operation at 2 V power supply with total power consumption of 60 mW [l].

1. INTRODUCTION HE growing market of high frequency mixed-signal T (mixed analog/digital functions) IC's ranging from

telecommunication circuits, wireless products, high speed networked computing systems, and high speed data acquisition systems, to global positioning system receivers, etc., has attracted many IC vendors to develop high performance mixed-signal BiCMOS technology [2].

Among the targeted mixed-signal products, many are for portable use. It is a common goal in semiconductor industries to aqhieve high speed at very low power consumption for those battery supported systems.

Low power design of mixed-signal integration on a chip generally uses bipolar ECL for high speed critical signal paths, and CMOS for data storage and low-power low-speed logic functions. To achieve low-power high-speed ECL, para- sitics such as cc, (collector-to-substrate capacitance) and c b c

(collector-to-base capacitance) must be reduced and high ft, fmax, value as well. Fig. 1 shows the simulated ECL delay

Manuscript received April 15, 1994. The review of this paper was arranged by Guest Editor K. Sbenai.

J. M. Sung, T.-Y. Chiu, K. Lau, T. M. Liu, V. D. Archer, B. Razavi, and R. D. Swartz are with AT&T Bell Laboratories, Holmdel, NJ 07733 USA.

F. M. Erceg, J. T. Glick, G. R. Hower, S. A. Krafty, A. I. LaDuca, M. P. Ling, K. G. Moerschel, W. A. Possanza, M. A. Prozonic, and T. P. Long are with ATCT Microelectronics, Allentown, PA 18103 USA.

IEEE Log Number 9408329.

- AV=OSV C, = 4fF fT = 40GHz I R B i = l O W O C,=15fF

109

.~ '0

10-121 ' " ' 1 1 1 1 1 I ' " ' I I I I 1 1 1 1 1 1 1

10-5 la4 10-3 10-2

Ic (A)

Fig. 1. Unloaded ECL gate delay component break up as a function of gate current. Tt equals to the inverse of 2 rift. C d diffusion capacitance equals tol, times ~d divided by 0.15 [2]. The values of other parameters used in simulation including f t , c,,, cbc, and Rb, are the listed numbers.

component as a function of gate current [3]. At low current, it is obvious that RzC,, and RI Cbc are the two major ECL delay components (Rl is the load resistance, typically fabricated with low parasitic polysilicon resistor). It is therefore for low-power high-speed ECL, both C,, and c b c must be reduced.

Reduction of C,, generally incorporates deep trench iso- lations to reduce Ccs,perimeter coefficient and/or silicon-on- insulator substrate materials to reduce Cc,,,re, coefficient [4], [5]. Reduction of c b c generally involves self-aligned double- poly bipolar structure to reduce extrinsic base area (therefore, lowering the extrinsic c b c value) [6]-[lo]. However, as the Cbc,extrinsic value decreases to be comparable in comparison with the cbc,intrjnsic value, the intrinsic collector profile must be also carefully optimized. An optimal intrinsic collector design should minimize the sum of both carrier transit time in favor of high collector concentration and (Rl + Rb)Cbc terms in favor of low collector concentration.

Here, we present our approach of low parasitic capac- itance fabrication. Key modules include selective-epitaxy- growth (SEG) [ l l ] , deep recessed LOCOS isolation, and Non-Overlapping self-Aligned (NOVA) double poly process W I , [ W .

0018-9383/95$04,00 0 1995 IEEE

514 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 42, NO. 3, MARCH 1995

TABLE 1 BEST-2 3 V/5 V BiCMOS FABRICATION SEQUENCE

10 11 12 13 14 15

CMOS

Isolation p-welVChannel-stop

n-well

150A or 125A Gate OX

Gate/Emitter Define PLDD/Base Linkup

NLDD p+s/d Poly-2 n+s/d

NOVA Planarization 3LM Backend

Bipolar Others

Collector Sinker

- Total = 21 Masks tnru M3, including scnottky Uiode, Linear Resistor Fabrication

11. KEY PROCESS MODULES Table I lists the BEST-2 BiCMOS fabrication sequence.

As buried 1ayerISEG-cappinglthin epitaxy module were exe- cuted first, followed by deep fully recessed LOCOS isolation. Subsequently, two masks were used to set up both ntub and ptub profiles as well as to adjust both n-ch and p-ch MOSFET’s 3 VI5 V threshold voltage at the same time. The collector plug was heavily doped by Phos. implant at the expense of one mask. Along with the threshold voltage implant adjustment for the 3 VI5 V CMOS technology choice, a different gate oxide thicknesses (125 h l 5 0 A ) were grown according to 3 VI5 V design. After gate oxidation, follows the bipolar process which is similar to the previous report [12]. The total mask counts through metal-3 including Schottky diode and linear components’ fabrication, is 21. Fig. 2 shows the schematic cross sections of some supported components including npn, n-ch, p-ch, poly2-resistor (three different sheet values: 150 Q/U, 300 R/U, 1 500 Q/U), and linear capacitor (top plate: silicided n+ poly-1; bottom plate: n+ silicon). Here, it is worthwhile to point out that all the active devices have identical structure above silicon level which is unique characteristics of nonoverlapping super self-aligned double- poly technology [ 121.

SEG/Epi Module: A buried layer module capable of satis- fying both low Ccs,perimeter requirement and low subcollector resistance is the goal. Arsenic dopant due to its higher solid solubility, therefore, can achieve low buried layer sheet resis- tance even at -1 pm thick only (in contrast to -3 pm thick antimony buried layer needed for the same buried layer sheet resistance).

However, arsenic due to its high lateral autodoping level experienced in traditional barrel epitaxy reactors would require very high boron dose implant cm-’) to counterdope the outside areas of the buried layers after epitaxy growth. The high dose boron counterdoping adversely increases the C,, perimeter coefficient. As a result, the advantage of using As as buried layer dopant is defeated.

We suppressed the As lateral autodoping problem by adopt- ing original SEG-capping technique with some modification as described below [ l l l . SEG-capping technique described in the previous report can effectively reduce the As lateral

Lin. Capacitor Poly Resistor NPN NMOS PMOS

I p’ Substrate I

Fig. 2. Schematic cross sections of npn bipolar, n-ch MOSFET, p-ch MOS- FET, polysilicon resistor, and linear capacitor. The device dimensions were not drawn to scales. Field implant (B++, 200 keV) and tub formation were after field oxide growth. Poly-I doped by As implant was used for both gate and emitter. Poly-2 can be either intrinsic, or n-type, or p-type for resistors, source/drain,and basekollector. When poly- 1 and poly-2 were used in local interconnection, they were fully silicided.

autodoping level to below 1 x l O I 5 cmP3 level. However, the unavoidable stacking faults produced at the edges of SEG layer needed to be taken care of. In the previous generation, SEG- capping was directly grown on buried layer areas. To ensure the SEG incurred defects be sufficiently displaced away from the active silicon areas, a larger buried layer dimension than needed from resistance point of view had to be used.

Here, we developed a new scheme which not only displaces the SEG defects sufficiently away from active silicon but also allows minimum buried layer dimension layout according to resistance requirement.

The developed process started with a thick oxide, 1 pm, grown on p- bulk, 10-20 Q-cm, substrate, followed by 1 d LPCVD nitride deposition. The buried layer areas were lithographically defined and nitride RIE etched as shown in Fig. 3(a). After stripping the photoresist, wafers were sub- jected to BHF to remove 1 pm thick oxide at the exposed buried layer windows. At the same time, approximately 1 pm oxide undercut along the defined windows’ edges was pur- posely produced (Fig. 3(b)). As a result, the dimension of the exposed silicon at the bottom of the buried layer windows was -2 pm larger than the top nitride opening. Subsequently, As, 35 KeV, 6 x 1015 ~ m - ~ , implantation was conducted. However, due to the 1 pm overhanging nitride film at the top of buried layer windows, its undemeath exposed silicon received no As implant. Afterwards, thermal oxide of 0.25 pm thickness was grown to drive As dopants into the substrate. Hot Phos. etch was used to remove the top nitride film, followed by 3 d oxide etch. As a result of 1 pm oxide undercut scheme introduced in the beginning, the physical dimension of the exposed silicon at this moment was 2 pm larger than original drawn buried layer. This prepared the condition prior to the SEG growth. After 0.3 pm SEG epitaxy, the oxide cap outside of the SEG-capped areas was completely etched off. A blanket p- silicon deposition of 0.5 pm thickness was followed. Fig. 3(c) shows the results.

Using the described SEG-defect offset scheme, the stacking faults produced at SEG edges can be displaced away from active silicon areas to the specified distance without incorpo- rating the buried layer layout to go with. In general, at least 3 pm in each x and y dimension of drawn buried layer can be saved between the new SEG-capping scheme and the reported scheme [ l l ] .

Deep Fully-Recessed LOCOS Isolation: Purposes of de- veloping this module is to further reduce C,, perimeter

SUNG et al.: A HIGH PERFORMANCE SUPER SELF-ALIGNED BiCMOS TECHNOLOGY FOR LOW-POWER MIXED-SIGNAL APPLICATIONS 515

As Implant

p- Substrate

(c)

Fig. 3. Schematic cross sections illustrate As-buried-layer and selec- tive-epitaxial-capping process: (a) after buried layer feature opening, (b) wpm oxide undercut at buried layer feature for the purpose of offsetting SEG defects away from active region, and (c) final buried layer cross section after SEG and blanket p-epi deposition.

component. It was achieved by physically separating the intrinsic collector from contacting the boron channel-stop implanted regions under the field oxide.

A LOCOS mask consists of 300 8, pad oxide, 1500 8, polysilicon, 1700 8, nitride, and 500 8, TEOS, were pho- tolithographically patterned and plasma etched. After striping the photoresist, a silicon trench of 2000 8, depth was etched. Sidewall mask materials of silicon trench consisted of 350 8, thermal grown oxide and 300 8, LPCVD nitride. L-footshape sidewall mask was then fabricated using disposable polysilicon spacer technique. The bottom dimension of L-foot spacer around 0.3 pm was produced. The TEOS film on top of the LOCOS mask provided an excellent etch stop during polysil- icon spacer overetch and protected the underlying LOCOS mask stack.

Field oxide of 8000 8, was grown at 95OoC, 10 atm, in steam for 20 minutes. Afterwards, the LOCOS mask was removed by wet etch, and subsequently, a two-step (450 k l 5 0 A) sacrificial oxidation were carried out for improving gate oxide reliability.

One of the issue associated with deep recessed LOCOS isolation is its apparent notch (groove) characteristic near the bird's beak region which potentially degrades the chip yield due to possible polysilicon residue left inside the notch after gate/emitter polysilicon etching. By combining a LPCVD nitride deposition and wet etchback process, the notch near the bird's beak was planarized. Fig. 4(b) shows the SEM cross section of the final field oxide.

300A Nitride

(a)

300A dxide

35OA Oxide

(b)

Fig. 4. Schematic cross sections illustrate deep fully recessed LOCOS isolation process: (a) prior to field oxidation. Top mask consists of 300 Aoxide, 1 500 8, polysilicon, and 1700 8, nitride. Sidewall mask (L-shape) consists of 350 8, oxide and 300 Anitride, covering sidewall of LOCOS mask and 0.2 pm deepsilicon trench. the bottom dimension of L-shape sidewall mask is 0.2 pm. (b) SEM cross section of field oxide prior to gate oxidation.

Non-Overlapping Super Self-Aligned Device Fabrication: Super self-aligned device structure can reduce base, source, and drain contact areas, therefore reducing parasitic capac- itance. Nonoverlapping double-poly bipolar structure enables both poly-1 and poly-2 to be fully silicided, which allows both polysilicon films to be silicided. The extrinsic base resistance thus can be further reduced. In contrast to the overlapping self-aligned double-poly bipolar structures, the overlapped base-poly near the emitter-poly cannot be silicided.

In the previous report, single resist planarization technique was developed to fabricate nonoverlapping super self-aligned device structure 1121. However, the resist thickness on top of to-be-planarized poly-stack varies according to the local device density across the chip, resulting in nonuniform protection during NOVA planarization. This limits the application of NOVA concept on various BiCMOS circuits. Here, we present a two-step resist planarization technique which solves the aforementioned issue.

Fig. 5(a) depicts the device cross section after poly-2 de- position, in which poly- l (gate/emitter stack) was entirely encapsulated by poly-2 film. Two-step photoresist-assisted- planarization was used to remove the overlap poly-2 materials. A first layer of resist (de-photosensitized) with low viscosity was applied on the wafers to achieve local planarization. A uniform thickness of thin resist coating on top of poly- 1 stacks independent of local transistor packing density and a poor resist coverage on open field were obtained. A second photoresist patterned by lithography was designed to cover the poorly covered area from the first resist. The sensitivity of de- vice pattern density encountered in original NOVA application was then completely eliminated. Afterwards, the wafers were subjected to plasma etching, resulting in Fig. 5(b) condition.

516 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 42, NO. 3, MARCH 1995

I 6kgr Dummy Poly

Ph

(b)

Fig. 5. Schematic device cross section illustrate super-self aligned device fabrication process: (a) After poly-2 capping. (b) After two-step photore- sist-assisted planarization which removes the poly-2 material at overlapped regions between poly-I stacks and poly-2 capping shown in (a).

750

600

450

0 - 300

150

0 I I I I I I 1 1 1 1

0 1.4 2.8 4.2 6.6 7

Fig. 6. IC-\:? characteristics of 13 860 equivalent EIX npn transistor in parallel array tester. E IX npn emitter area 1 x 2 pm2, drawn buried layer 7 x 3 pm2, base area 2.5 x 2 pmZ. The drawn buried layer was 0.5 p m outside of activesilicon boundary. Isolation distance between base and collector was 2.5 pm.

h

5 g!

c C

L

3

10-13 0 0.5 1

vbe(v)

Fig. 7. collector-base junction was reverse biased to 1 V.

Gummel plot of 13 860 paralleled E1X npn transistor array. The

24

20

16

12

8

A f,,;V,=IV A ft ;V,,=IV

4

0 0 1 10 100

IC (mA)

Fig. 8. Measured ft/f,,,dependence on collector current at tie = 1 V, 3 V, and 5 V,on E16X npn device (emitter contains 16 fingers, each finger area is I x 2 pm').

111. BIPOLAR PERFORMANCE

Fig. 6 shows the linear I,-Vce at different I b biases, starting at 0 pA with AI, = 1 pA, obtained from 13 860 paralleled E1X npn bipolar transistors (ElX: emitter dimension: 1 x 2 pm2, design rules: one nesting tolerance: 0.5 pm). The early voltage at V,, = 3 V is 24 V, and current gain 100, and BV,,, > 6 V, which exhibits the same characteristics as single E1X npn transistor.

Fig. 7 shows the corresponding Gummel plots of I , and Ib at vbc = - 1 V measured on the same tester (13 860 paralleled E1X npn array). Very ideal device characteristic (59-61 mV/dec) was obtained down to pA range.

SUNG et al.: A HIGH PERFORMANCE SUPER SELF-ALIGNED BiCMOS TECHNOLOGY FOR LOW-POWER MIXED-SIGNAL APPLICATIONS 517

loo-

Eminer Area: 1 x2 & 500 mV Logic Swing

0 1 I I I I I I 0.4 0.8 1.2 1.6 2.0

Switching Cumnt (Wstage)

Fig. 9. Measured unloaded ECL gate delay as a function of gate cur- rent(signal swing = 500 mV and V,, = - 5 V).

I ! I ! I ! I

I - - - - - - - - - - - I !-i I

110 r

20 L c b - v I V

I . 0 I I I I I I I I

-5 -4 -3 2 1 C

Collector-Substrate Bias (V)

Fig. 10. Measured C,, of different npn devices as a function of collec- tor-to-substrate reverse bias.

Dependence of ft (unity of current gain) and fmax (unity of power gain) on collector current (I,) as a function of V,, are demonstrated in Fig. 8. At Vce = 3 V, the peak ft and fmax are 23 GHz and 24 GHz, respectively. The collector current density at which ft peaks is in the range of 20-30 kA/cm2. The ft BV,,, product about 138 is achieved (typical reported ftBV,,, product ranges from 70 to 140 using implanted base silicon technology).

The measured unloaded ECL gate delays (500 mV swing and V,, = - 5 V) versus gate currents is plotted in Fig. 9. At gate currents of 2.1 "0.6 mA, 37 ps/48 ps were obtained. In the following, we will present the measured C,, and c b c of bipolar devices, and how they compared with reported values.

Fig. 10 presents the measured C,, of different npn devices (ElX, E4X, E16X, E32X) versus collector-to-substrate reverse bias. Fig. 1 1 depicts the layout/dimension of the measured devices. The minimum E1X npn device, the drawn buried layer of 6.5 x 3 pm2, has a zero biased C,, of 7.8 fF. Fig. 12 plots the measured C,,huried layer area (fF/pm2) as a function of buried layer perimeterhuried layer area (l/pm). By least square fitting, we obtain the Ccs,perimeter from the slope to be 0.35 fF/pm and C,,,,re, from the y-intercept to be 0.07 fF/pm2. For typical LOCOS isolated bipolar technologies, Ccs,perimeter are in the range between 1 to 3 fF/pm.

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I I 1 I

E 8 X

I I

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1 ; I 1

S I

I 1 1

I I I

E 3 2 X

m r - - - - - I _ - - _ - I

C H R N N E L E M I T T E R S T O P

Fig. 11. Top view of npn device layout for C,. measurement. Shown levels include buried layer, active silicon, emitter (polyl), poly2.

0.5 EIX

iu 0.4

Y-Intercept (C,J = 0.07 fF/prn2

Slope (c,,p) - 0.35 fF/prn 0 0.1

0.0' I I ' ' ' ' ' 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0

Perimeter/Area (pm-1)

Fig. 12. Measured C,, over buried layer area of different npn devices as a function of buried layer perimeter over buried layer area.

To see how the measured C,, fabricated without deep trench isolation with ideal cases using deep trench technologies. Fig. 13 plots the measured C,, data for various devices in comparison with the calculated data using poly-filled deep trench ( d / h = 1 pm/5 pm) on p- substrate. The open squares represent the BEST2 data. The solid squares represent the cal- culated C,, based on the same C,,,,,,, coefficient as extracted from BEST2 devices and 0.1 fF/pm as Ccs,perimeter to simulate the 1 pm wide poly-filled deep trench in conjunction with 1 pm thick (As) buried layer. The solid triangles represent the calculated C,, using the conditions as described in solid squares' except that the Ccs,perimeter is replaced by 0.3 fF/pm to simulate 3 pm Sb buried layer. The results show that the developed low C,, technology can mimic the C,, performance delivered by deep trench in conjunction with Sb buried layer based on the same design rules.

Fig. 14 compares reported C,, up to date versus design rules and technologies [14]. Indeed in case of LOCOS isolation,

518 EEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 42, NO. 3, MARCH 1995

12

11

10

2 9 0

$ 7

p

8 4

4 3

--

3 5 0

2

1

0

BL1 BL2 8o - Acalculatedc basedon

70 -

60 -

50

40

30

C,, p - 0.3 fim and C,. a = 0.07 ffl& to simulate poly-filled deep trench and 3p-n thick buried layer (Sb)) on p- substrate

-

-

- 1 2 3 4

Dram EL-to-EL Distanca, L (p)

Fig. 15. Measured leakage current as a function of the drawn separation distance between two adjacent buried layer. The field implant (B++, 200 KeV, 5 x lo1' cm-') was through thick field oxide at 1.25 um distance away from each buried layer.

" E1X E2X E4X E8X E16X E32X npn Devices

Fig. 13. Comparison of measured C,, for various npn devices with ideal cases where deep trench isolation is employed.

. E SinglePoly

#

LOCOS A SO1 +Trench

E

o 0

4 BEST 2

0 0 0

#

6 20 8 0 301 0

8 o 0.2 0.4 0.6 0.8 I 1.2

Design Rules (pn)

Fig. 16. Reported minimum size bipolar C b C data in the literature versus design rules. The open squares were associated with double-poly bipolar structure. The solid squares with single-poly bipolar structure.

BEST 2

4 i lot 0 0 0.2 0.4 0.6 0.8 1 1.2

Design Rules (am) between 2.75 pm and 3.25 pm drawn separation. The achieved packing density is very comparable to 1 pm wide deep trench isolation since typically a 0.5 pm to 1 pm offset distance from trench to active silicon is needed for preventing the junction leakage caused by the silicon defects 'generated athear the trench.

The reason of our low C,, performance without losing bipolar packing density are due to the following factors carefully engineered: 1) lateral autodoping suppression allows incorporation of shallow As buried layer with reduced de- vice depth and perimetedarea, 2) self-aligned SEG setback region minimizes buried layer dimension, 3) thick field oxide reduced perimeter capacitance, 4) low dose post oxidation field channel-stop implant and its displacement from buried layer further reduced perimeter capacitance.

Fig. 16 compares the Cbc data among the published reports against design rules and technologies [14]. BEST2 E1X npn, the drawn active base area 2.5 x 2 pm2, has achieved 5 fF,

Fig. 14. Reported minimal size bipolar C,, data in the literature versus design rules. The open squares were associated with deep trench technologies. The solid squares with LOCOS isolation. The solid triangle is by deep trench and SO1 substrate.

most C,, data other than three data points are higher than deep trench isolation's. The competitive low C,, data based on LOCOS technology other than BEST2, however, either involves advance low-temperature-epitaxial base or reduces Ccs,perimeter coefficient at the price of losing bipolar packing density.

Next, we will examine the bipolar device packing density. The achieved bipolar packing density can be seen in Fig. 15. It plots the leakage between the adjacent buried layers (50 pm wicith) at 7 V bias. The insert figure illustrates the tester used and testing condition. Basically, no detectable leakage is seen between drawn buried layer at 3.25 pm apart till somewhere

SUNG er al.: A HIGH PERFORMANCE SUPER SELF-ALIGNED BiCMOS TECHNOLOGY FOR LOW-POWER MIXED-SIGNAL APPLICATIONS

7

- 6 5 f 5

.- $ 4

UJ ii

z $ 3

2

o I c = 2 m A o I c = 4 m A A k = 8 m A

0 1 2 3 4 5 6 Frequency (GHz)

Fig. 17. Measured minimal noise figure and associated gain on E16X npn device as a function of frequency at different collector currents (2 mA, 4 mA, and 8 mA). ft peaks around 8 mA in E16X npn device.

5

0 0.75 1.5

v g s w

Fig. 18. (drawn gate dimension = 0.8 X 1 pm2 and V and 5.5 V, respectively.

Subthreshold characteristics of 1 680 paralleled n-ch MOSFET E1X = 0.68 pm) at vd, = 0.1

which is among the average reported value. Due to the reverse sequence in forming the emitter (polyl) and the base (poly2) in our bipolar process in comparison to the sequence, where the base (polyl) was formed prior to the emitter (poly2). We cannot take advantage of the pedestal collector technique which can selectively optimize the intrinsic collector doping without disturbing the extrinsic collector doping concentration at no additional mask. Here, at the expense of one additional mask (to protect CMOS and bipolar collector areas), the extrinsic collector doping concentration can be diluted using

519

I 0 -0.75

v g s w

-1.5

Fig. 19. (drawn gate dimension = 0.9 x 1 pm2 and V and - 5.5 V, respectively.

Subthreshold characteristics of 1 680 paralleled p-ch MOSFET ElX = 0.8 pm) at vd, = -0.1

I------: I.. . - -, U m BL T O X GFITE

Fig. 20. levels include buried layer, active silicon, gate (polyl) and poly2.

Topview of E1X n-ch and p-ch MOSFET's layout. Shown layout

boron implant. It is projected that the CbC of E1X npn can be reduced down to 2.5 fF with one additional mask.

Fig. 17 shows the minimal noise figure measured on E16X npn device (emitter area: 16 times 1 x 2 pm2) as a function of frequency for three different collector currents. At 2 GHz, min- imum noise figure of 3.25 dB with associated gain 12 dB was obtained. The achieved noise performance can be improved by reducing the base resistance using multiple finger emitter structure in trading with associated gain, or by lowering the intrinsic base sheet in trading with digital circuits performance.

IV. CMOS PERFORMANCE

BEST2 supports both 3 V and 5 V product designs. The main constraints of 5 V version are n-ch MOSFET hot carrier life time (20% linear transconductance degradation in 10 years and pA/pm io^ for minimal gate length with allowed variation of gate length o f f 0.15 pm and A&, of f 0.1 V.

Fig. 18 and Fig. 19 presents the subthreshold curves of 1680 paralleled E1X n-ch (surface channel) MOSFET'S and 1680 paralleled E1X p-ch (buried channel) MOSFET's, at V& = f 0.1 V and f 5.5 V, respectively. Fig. 20 depicts the E1X n- ch and E1X p-ch transistor layout for reference (noting p-ch MOSFET has buried layer underneath). The exhibited inverse subthreshold slopes were around 80-90 mV/decade.

520 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 42, NO. 3, MARCH 1995

200-

180 -

180 -

f 140 Q 1 2 0 -

-

2 5 loo 0

-

a 8 0 - 0

v , p* = 0.45 v

8 0 -

40- , -. -. J

20

0 I 1 I I I I I I 1 1.5 2 2.5 3 3.5 4 4.5 5 5.5

Power Supply Voltage (V)

Fig. 21. Measured unloaded CMOS gate delay (worse-slow to worst-fast) as a function of supply voltage for both 3 V and 5 V process. The variation in speed were caused by the variation in gate oxide thickness, threshold voltage, and channel length.

2 8 II

> 8

CMOS

I /- I I I I I I

0 0.1 0.2 0.3 0.4 0.5 0.6 Load Capacitance (pF)

Fig. 22. Measured CMOS, BiCMOS, and BiNMOS delays versus load capacitance at 3 V power supply for 3 V process.

Both n-ch and p-ch MOSFET’s source/drain junctions were formed by out-diffusion dopants from the implanted-poly 2 into the silicon substrate. Thus, a shallow junction for both n+ and p+ source/drain can be easily accomplished. The second merit of self-aligned double-poly MOS structure allows the source/drain silicon area to be reduced down to one-third of conventional single-poly devices’. Here, 1 pm design rule was used in device layout, the drawn dimension of source/drain silicon area is 0.75 x transistor width pm2.

For 5 V (150 A gate oxide) CMOS technology, nominal threshold voltage are 0.65 V for n-ch, and - 0.9 V for p-ch MOSFET’s. Threshold voltage shift (Avth) at substrate bias, Vbs, 5 V are measured to be 0.9 V for n-ch and -0.45 V for p-ch devices. The low body effect of p-ch devices is resulted from the low-high ntub doping profile, where the low n-type doping concentration is nearly constant at I x 10l6 cm-3 from silicon surface to 0.5 pm deep and the high n-type profile is the As buried layer used in npn bipolar.

The extrapolated early voltages at V,, = 5 V/V,, = 3 V were 200 V for E1X n-ch and 20 V for ElX p-ch MOSFET’s, respectively. Both poly1 and poly2 are silicided with sheet

TABLE U TYPICAL VALUE OF DEVICE PARAMETERS OF 5V BiCMOS VERSION

resistance of 3 a/O. The window contact to gate/source/drain lands on silicided polysilicon which are located on field oxide.

By adjusting the surface profiles at the tub implant step to- gether with 125 w gate oxide and with rest of process identical to 5 V process, n-ch threshold voltage is scaled down to 0.45 V and p-ch to -0.45 V for constituting 3 V BiCMOS technology. The objective of 3 V CMOS process is to retain 5 V CMOS speed performance down to 2 V power supply. To achieve this, the Io* requirement has been relaxed to nNpm range.

Fig. 21 depicts the measured worst-slow to the worst-fast gate delays of unloaded CMOS ring oscillators (131 stages) versus power supply voltage for both 3 V (highlighted by shaded region) and 5 V CMOS technologies. In 3 V case, a 50% speed degradation occurs at 1.75 V supply. Nominal CMOS delays at 3 V, le^ = 0.6 pm, is measured 70 ps/stage. From the C-V measurements, the source/drain junc- tion capacitance perimeter coefficient near the isolation edge is 0.09 fF/pm, and areal coefficient 1.2 fF/pm2. From simulation, our self-aligned double-poly MOSFET structure can improve unloaded ring oscillator speed by at least 30% over conven- tional CMOS technologies based on similar design rules. The speed improvement over conventional CMOS technologies’ are due to the following factors: 1) reduced source/drain silicon area, 2) reduced junction capacitance perimeter coefficient by the recessed LOCOS isolation, 3) shallow source/drain junc- tion achieved by polysilicon out-diffusion scheme, 4) careful engineering in minimizing the gate-to-source/drain overlap capacitance. The last factor is often overlooked in 80-90s’ CMOS technologies when the short channel margin with respect to &,ff/&h rolloff exceeded the lithography capability, a common practice to overdrive the source/drain to reduce the Le* is used to gain higher DC drivability and higher ft. How- ever, the actual CMOS circuit speed might be degraded due to the miller effect of the large gate-to-drain overlap capacitance.

Lastly, Fig. 22 presents CMOS, BiCMOS, and BiNMOS delays versus load capacitance measured at 3 V power supply. Table I1 lists the typical values of device parameters for 5 V version.

V. SUMMARY

We obtain low parasitics npn bipolar/MOSFET’s devices based on SEG/epi process, deep fully recessed LOCOS isola-

SUNG et al.: A HIGH PERFORMANCE SUPER SELF-ALIGNED BiCMOS TECHNOLOGY FOR LOW-POWER MIXED-SIGNAL APPLICATIONS 521

tion, and NOVA double-poly processes. With 1 pm design rule, the achieved parasitic capacitance value has shown a very competitive performance in comparison to the published data using 0.5 pm design rules. The developed low parasitics modules have been successfully integrated into BEST2, a 1 pm BICMOS technology, in manufacturing. Excellent yield, pack- ing density, and circuit performance have been demonstrated.

ACKNOWLEDGMENT

The authors are obliged to the operation staffs of AT&T- Microelectronics at Allentown, PA, for their assistance of BEST2 BICMOS devicekircuit fabrication, and Samuel Mar- tin for noise measurement.

REFERENCES

B. Razavi et al., “A 6 GHz 60 mW BiCMOS phase-locked loop with 2 V supply,” in ISSCC Digest, p. 114, 1994. R. Hadaway et al., “BiCMOS technology for telecommunications,” in Proc. Bipolar Circuit and Tech. Meeting, 1993, p. 159. P. K. Tien, “Propagation delay in high speed silicon bipolar and GaAs HBT digital circuits,” Int. J. High Speed Electron., vol. 1, no. 1, p. 101, 1990. M. Sugiyama et al., “A 40 GHz ft Si bipolar transistor LSI technology,” in IEDM Tech. Digest, p. 221, 1989. C. Davis et al., “UHF-I: A high speed complementary bipolar analog process on SOI,” in Proc. Bipolar Circuit and Tech. Meeting, 1992, p. 260. T. Yoshimura et al., “0.6 pm high speed BiCMOS technology with emitter-base self-aligned structure,” IEDM Tech. Digest, p. 241, 1989. W. Burger et al., “An advanced self-aligned BiCMOS technology for high performance 1-megabit ECL VO SRAM’s,” in IEDM Tech. Digest, p. 421, 1989. Y. Kobayashi et al., “SST-BiCMOS technology with 130 ps CMOS and SO ps ECL,” in Proc. Symp. VLSI Technology, 1990. p. 85. T. Shiba et al., “SPOTEC-a sub I O pm2 bipolar transistor structure using self-aligned sidewall polycide base technology,” in IEDM Tech. Digest, p. 455, 1991. J. Kirchgessner et al., “An advanced 0.4 pm BiCMOS technology for high performance ASIC applications,” in IEDM Tech. Digest, p. 97, 1991. T. Y. Chiu et al., “Lateral autodoping suppression by selective epitaxy capping and its application in high speed BiCMOS,” in Proc. 20th Con$ Solid State Devices and Materials, 1988, p. 45. T. Y. Chiu et al., “A high speed super self-aligned bipolar-CMOS technology,” in IEDM, p. 24, 1987. K. G. Moerschel et al., “BEST1: A BiCMOS-compatible super self- aligned ECL technology,” in Proc. Custom Integrated Circuit Con$, 18.3.1, 1990. 1988-1993 IEDM Tech. Dig., VLSI Tech. Sym., BCTM Sym.

T.-Y. Chiu (S’78-M’82) was bom in Taiwan, R.O.C. He received the B.S. degree from Rensselaer Polytechnic Institute in Troy, NY, in 1977, and the Ph.D. degree in electrical engineering from the University of California, Berkeley, in 1983.

From 1979 to 1980, he was with the Institut fuer Festkoerpertechnologie, Munich, Germany. He joined AT&T Bell Laboratories in 1984 and was responsible for the design and integration of first generation NOVA BiCMOS. He is now the head of the High Performance VLSI Department and the Silicon Research Operations Department. His present interest is in low-power high- speed BiCMOS, silicon MMIC, and device physics and characterization. He has been awarded 5 patents in the field of integrated circuit technology.

Dr. Chiu was named Distinguished Member of the Technical Staff at AT&T. He was an Associate Editor for IEEE ELECTRON DEVICE LETTERS and is a member of Tau Beta Pi.

K. Lau, photograph and biography not available at the time of publication.

T. M. Liu, (S’80-M’83-SM’93), photograph and biography not available at the time of publication.

V. D. Archer (M’80), photograph and biography not available at the time of publication.

B. Razavi (S’90-M’91), photograph and biography not available at the time of publication.

R. G. Swartz (M’80-SM’89-F’94), photograph and biography not available at the time of publication.

F. M. Erceg, photograph and biography not available at the time of publication.

J. T. Glick, photograph and biography not available at the time of publication.

J. M. Sung received the B.A degree in 1979 and the M.S. degree in 1981, both from Taiwan National Chiao-Tung University, and the Ph.D, degree from Princeton University in 1988.

He then joined AT&T Bell Laboratones, Allen- town, PA, as a member of the technical staff of the VLSWLSI CMOS technology department, where he was involved in half-mcrometer twin-tub VI CMOS technology development. In 1989, he was transferred to the high-speed memory laboratory to develop high-speed high-density SRAM technology.

In 1991, he moved to the silicon research laboratory in Holmdel, NJ, involving high performance bipolar/BiCMOS technology research and leading technology establishment in the AT&T Microelectronics High Performance IC Business Unit. In 1994, he was transferred to the high-performance technology department at Murray Hill, NJ. He is now project leader responisble for high-performance low-cost BiCMOS and low-power high-speed electronics research and manufacture transfer. He has authoredco-authored over 35 papers in refereed journals on the subjects of device physics, device structure, and technology and holds 7 U.S. patents

G. R. Hower, photograph and biography not available at the time of publication

S. A. Krafty, photograph and biography not available at the time of publi- cation.

A. J. LaDuca, photograph and biography not available at the time of publication

M. P. Ling, photograph and biography not available at the time of publication

522 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 42, NO. 3, MARCH 1995

K. G. Moersehel, photograph and biography not available at the time of publication. publication.

M. A. Prozonic, photograph and biography not available at the time of

W. A. Possanza, photograph and biography not available at the time of publication. T. P. Long, photograph and biography not available at the time of publication.