Abstract—One of the most significant recent advances in power electronics is the multilevel inverter. Using this concept the power conversion is performed with enhanced power quality. In this scenario the Cascade H-Bridge Multi Level Inverter (CHBMLI) is an exceptional one and it has many inherent benefits like: its modular structure, it can be easily implemented through the series connection of identical H-bridges, generates stepped sinusoidal voltages at fundamental frequency with small harmonics and finally no electromagnetic interference . This flexibility has resulted CHBMLI topology in various applications like medium-voltage industrial drives, electric vehicles and the grid connection of photovoltaic-cell generation systems. But one of the major limitations of the cascade multilevel converters is requirement of isolated dc voltage sources for each H-bridge and more number of switches, this increases the converter cost and reduces the reliability of the system. This drawback is the key motivation for the present work. This paper investigates multilevel inverter topology with reduced DC sources and Switches. A conventional switching strategy is implemented to get the multilevel output without using any PWM techniques. Finally the proposed model reduces the THD and size of multilevel converter when compared with the cascade H-bridge multilevel inverter (CHBMLI). The performance of proposed architecture, simulation results are presented in this paper.

Keywords—CHBMLI, Multilevel Inverter, THD.

I. INTRODUCTION ULTILEVEL converter gives massive advantages compared with conventional and very well known

two level converters like; high power quality waveforms, low switching losses, high voltage capability, low electromagnetic compatibility etc. [1]–[3]. One of the most significant multilevel topology is Cascade H-Bridge Multi Level-Inverter (CHBMLI) [4], [5]. CHBMLI has numerous advantages over Diode-Clamped (DCMC), Flying-Capacitor (FCMC) and P2 Multilevel Converters (P2MC) [6], [7]. All these

Dr. V Siva Krishna Rao Gadi is with the, Electrical Engineering Department, College of Engineering, Andhra University, Visakapatnam, INDIA. (e-mail: gvskrishna_rao@yahoo.com).

N. CH.V. Chakravarthi Bobbili is with the Electrical Engineering Department, Vishnu Institute of Technology, Vishnupur, Bhimavaram, WG (Dt), INDIA, (e-mail: chakravarthi204@gmail.com).

Seshagiri Boppana is with the Electrical Engineering Department, , Vishnu Institute of Technology, Vishnupur, Bhimavaram, WG (Dt), INDIA.(e-mail:seshu.boppana@gmail.com).

Dr. Suresh Kumar Tummala with the Electrical Engineering Department, , Vishnu Institute of Technology, Vishnupur, Bhimavaram, WG (Dt), INDIA.(e-mail: sureshkumar255@ieee.org).

converters are compared in terms of feasibility of their utilizations and applications [8].

Multilevel inverters are an attractive alternative to improve the output by synthesizing a staircase waveform imitating a sinusoidal waveform. Such a waveform not only has a low distortion, but it also reduces the dv/dt stress [9]. Multilevel inverter topologies have the advantages of overcoming voltage limit capability of semiconductor switches, high voltage capability and better harmonic profile [10]–[12].

Moreover, multilevel inverters can operate at both fundamental switching frequency and high switching frequency. Thus, for high power/high voltage applications a multilevel inverter can achieve better output waveform using medium voltage power switches and hence preferred over classical two-level inverters.

As aforesaid discussion indicates, multilevel inverters have been attracting lot of attention in high power and high voltage applications because they allow to keep the voltage stresses of power switches within rated limits and thus adds to the reliability of the converter.

However, another reliability issue is ‘simplicity’, as in electronics design, a system with more number of parts is more likely to fail, all the difficulties stated above can minimized by reducing the number of switches ,in this paper the proposed topology having 8 number switches for single phase connection.

II. BASIC MULTI LEVEL H-BRIDGE INVERTER TOPOLOGY The concept adapted for the proposed MLI topology is

that the inverter should be capable of synthesizing all possible additive and subtractive combinations of the DC levels of the input sources.

Fig. 1 Cascaded H-Bridge Inverter Configuration.

A Hybrid Multi Level Three Phase Inverter

Dr. V Siva Krishna Rao Gadi, N.CH.V. Chakravarthi Bobbili, Seshagiri Boppana, and Dr. Suresh Kumar Tummala

M

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Topologically, multilevel inverters are largely divided into three configurations:[13] diode-clamped multilevel (DCML) inverters, flying-capacitor multilevel (FCML) inverters, and cascaded H-bridge (CHML) multilevel inverters. Among them, a cascaded H-bridge inverter with separate dc sources is useful for practical applications.(Fig.,1), because of reduced number switches and DC link sources. Multiple numbers of H-Bridges are connected in cascade [15] to get number of levels at the output voltage. (Fig. 1)

The "level" in a cascaded-inverters defined by M=2N+1, where M is the output phase voltage level, and N is the number of H-Bridges [16].

For example to obtain 11 level output voltage we need to connect 5 H-Bridges in cascade., so to attain the higher levels the circuit becomes complex .

Fig. 2 Three-phase Cascaded H-Bridge Inverter for 11-Level

III. PROPOSED THREE PHASE TOPOLOGY

In this paper, the proposed topology has been investigated for various objectives such as minimum number of switches and DC voltage sources.

Fig. 3 Three-Phase 11-Level Inverter.

By changing the magnitude of the DC input sources in the proposed topology can attain different levels at the output.

To obtain number of levels at the output side the values of DC sources has to consider as per Table 1.The proposed topology can easy to develop as compared to the cascaded H-bridge multilevel inverters and THD also reduced as compared to the cascade inverters.

TABLE I LIST OF DC INPUT VOLTAGES WITH LEVEL NUMBER S.NO Level Number DC Input Voltages

1 7 E,E,E 2 9 E,2E,E

3 11 E,2E,2E

4 13 E,3E,2E

This Paper presents a conventional Three-phase 11 and 13-level inverter with less number of power elements and hence less gate drive circuits in addition to less circuit layout complexity. As the number of output levels increases the harmonic content can be reduced. In this inverter without using any PWM techniques the THD level will reduce.

TABLE II SWITCHING PATTERN FOR PROPOSED 11-LEVEL INVERTER

Level Voltages

Switching Pattern S1 S2 S3 S4 S5 S6 S7 S8

+5E 1 0 0 1 1 0 0 1 +4E 0 1 0 1 1 0 0 1 +3E 1 0 0 1 1 0 1 0 +2E 0 1 0 1 1 0 1 0 +E 1 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 -E 0 1 1 0 1 0 1 0 -2E 1 0 1 0 0 1 0 1 -3E 0 1 1 0 0 1 0 1 -4E 1 0 1 0 0 1 1 0 -5E 0 1 1 0 0 1 1 0

The switching pattern for 11-level inverter is tabulated

in the Table II indicates switch is in ON position, 0 indicates switch is in OFF position. From the above table the gate pulses are evaluated for each switch.

TABLE III SWITCHING PATTERN FOR PROPOSED 13-LEVEL INVERTER

Level Voltages

Switching Pattern S1 S2 S3 S4 S5 S6 S7 S8

+6E 1 0 0 1 1 0 0 1 +5E 0 1 0 1 1 0 0 1 +4E 1 0 0 1 1 0 1 0 +3E 0 1 0 1 1 0 1 0 +2E 1 0 1 0 1 0 0 1 +E 1 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 -E 0 1 1 0 1 0 1 0

-2E 0 1 0 1 0 1 1 0 -3E 1 0 1 0 0 1 0 1 -4E 0 1 1 0 0 1 0 1 -5E 1 0 1 0 0 1 1 0 -6E 0 1 1 0 0 1 1 0

The switching pattern for 13-level inverter is tabulated in the table3.

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IV SIMULATION RESULTS For both 11 and 13 level inverters, the circuit configuration remains same, but they are differed by DC bus voltages and gating signals. Proposed 11 and 13-level inverters are shown in Fig. 3, which are realized through the SIMULINK / MATLAB. The input DC bus voltages for 11-level and 13-level inverters are tabulated in Table III. Fig. 5 shows the gating pulses for left leg of inverter and the complementary gating pulses are applied to right leg of proposed 11-level inverter.

Fig. 5 Gating Pulses for Switches in one Leg of the proposed Inverter.

Fig. 6 Three- Phase Line to Line Voltages of 11-Level Conventional H-Bridge Inverter

Fig. 7 FFT analysis of 11-level conventional H-Bridge Fig. 7 indicates the Harmonic spectra of Conventional H-

Bridge Inverter. The Total harmonic Distortion (THD) value is about 9.35%.

Fig. 8 Three-Phase LL Voltages of proposed 11 Level Inverter Fig. 8 shows the three phase line to line output voltages

of proposed 11-level inverter and output voltage waveforms with small first order filter.

Fig. 9 FFT analysis of 11-Level Proposed inverter

Fig. 9 Shows the FFT analysis of three proposed 11-level

inverter output voltage. The fundamental component of inverter is 761.2V for an input DC bus voltage of 500V. The total Harmonic Distortion (THD) value is reduced to 7.43% without using any pulse width modulation (PWM) techniques.

Fig. 10 Three-Phase LL voltages of proposed 13 Level Inverter

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Fig. 10 shows the three phase line to line output voltages of proposed 13-level inverter and output voltage waveforms with small first order filter

Fig. 11 FFT analysis of 13-level proposed inverter

Fig. 11 shows the FFT analysis of three proposed 13-level

inverter output voltage. The fundamental component of inverter is 903.8V for an input DC bus voltage of 600V. The Total Harmonic Distortion (THD) value is reduced to 6.83% without using any Pulse Width Modulation (PWM) techniques.

V. CONCLUSIONS Technical aspects and Performance of proposed Multilevel Inverters with reduced DC sources are presented. Proposed three phase 11 & 13-level inverters are able to produce line voltages at higher fundamental and lower THD as compared to the CHBMLI. The effectiveness and validity of the proposed approach are also demonstrated with results. Since less number of components are utilized, the proposed structure is reliable, efficient, cost-effective and compact. The attractive features of the proposed converters are: low switching frequency and reduce electromagnetic interference problems, increase utilization rate because of less number of DC sources, Consequently, this characteristic allows one to achieve high quality output voltages and input currents. Also, it has outstanding availability due to their intrinsic component redundancy. Due to these features, proposed architecture is superior over the conventional structures. Results presented in this paper are line voltage, because the line voltage is able to synthesize more levels compared to the phase voltage, thus resembling a more desirable sinusoidal waveform. Besides that, the line voltage yields better spectral performance, hence reducing the need of an output filter.

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Prof. G. V. Siva Krishna Rao received his Bachelor Degree in Electrical and Electronics Engineering from Sri Venkateswara university Thirupathi Andhra Pradesh, India. He completed his Master of Technology in Power Systems from Sri Venkateswara university Thirupathi Andhra Pradesh, India. He was awarded with Doctorate (Ph.D.) degree in Electrical Engineering from the Andhra University in 2007.Presently Working as Professor Depatment Of Electrical Engineering

college of Engineering Andhra University Vishakapatnam. Two research scholars are guided and four are under process..He has published several papers in his areas of interest. He is also a member of different professional societies like IEEE, IGNOU, UGC Nominee and AICTE.

International Conference on Advances in Engineering and Technology (ICAET'2014) March 29-30, 2014 Singapore

http://dx.doi.org/10.15242/IIE.E0314115 539

B.N.CH.V. Chakravarthi received his Bachelor degree in Electrical and Electronics Engineering from Akula Gopayya Engineering College, Tadepalligudem, Andhra Pradesh, India in the year 2006. He completed his Master of Technology in Power Electronics at Nova Engineering College, Jangareddigudem, Andhra Pradesh, India in the year 2011. His area of interests includes Power Industrial drives and FACTS Controllers. He published two papers on

Multilevel Inverters. He is a member of ISTE, IAENG. He is currently working as Assistant Professor in Electrical and Electronics Engineering Department at Vishnu institute of Technology Bhimavaram, Andhra Pradesh, India.

B. Seshagiri received his Bachelor Degree in Electrical and Electronics Engineering from Gudlavalleru Engineering College, Andhra Pradesh, India in the year 2008. He completed his Master of Technology in Power Electronics stream from Swarnandhra College of Engineering and Technology, Narasapuram, Andhra Pradesh, India in the year 2012. His area of interests includes Power Industrial drives and FACTS Controllers. He published two papers on reduction of harmonics in Voltage source

Inverters. He is currently working as Assistant Professor in Electrical and Electronics Engineering Department at Vishnu institute of Technology Bhimavaram, Andhra Pradesh, India.

Dr. Suresh Kumar Tummala (M’08) was born in Visakhapatnam. He received his Bachelor’s and Maters degree in Electrical & Electronics Engineering from Jawaharlal Nehru Technological University, Hyd. in 2005 and 2007 respectively. He was awarded with Doctorate (Ph.D.) degree in Electrical Engineering from the JNTUA, Ananthapur in 2013. Presently working as Associate Professor & Head of EEE Department with Vishnu Institute of Technology, Bhimavaram, Andhra Pradesh, India. His areas of

interests include Power System Reliability, Renewable Energy, Power Electronics, Drives and Electrical Machines. He has published several papers in his areas of interest. He is also a member of different professional societies like IEEE, IAENG, ISTE, ISEEE, ISES, and EDAS.

International Conference on Advances in Engineering and Technology (ICAET'2014) March 29-30, 2014 Singapore

http://dx.doi.org/10.15242/IIE.E0314115 540