IEEE Transactions on Nuclear Science, Vol. NS-27, No. 6, December 1980
A PROCESS FOR THE SIMULTANEOUSPRODUCTION OF RADIATION HARDENED
COMPLEMENTARY LINEAR BIPOLARAND LINEAR METAL GATE CMOS DEVICES
K. A. Ports
Harris SemiconductorMelbourne, Florida 32901
AbstractA process has been developed for the manufacture
of radiation hardened linear metal gate CMOS devicesand complementary linear bipolar devices on the samesilicon chip. The devices are fabricated into di-electrically isolated single crystal silicon tubs in apolysilicon substrate. A pyrogenic oxidation processwas used to form the CMOS gate oxides, and total dosehardness to 1 Mrad(Si) has been demonstrated for bothCMOS and bipolar devices. The pyrogenic oxidationprocess has been applied to a radiation hardeneddigital CMOS fabrication process, and a significantdecrease in radiation effects has been observed indevices fabricated with the pyrogenic process.
Introduction
Though military systems used in space andnuclear environments can consist of both digital andanalog functions, most of the process development forradiation hardened CMOS circuits has centered on thelower voltage, digital parts.1'2 The optimalprocesses for the fabrication of these parts pre-supposed guardringed n- channel device design andutilized thin, carefully grown and annealed gateoxides and several other process constraints.The ambient used for the gate oxidation was dryoxygen, and hardness to well over 1 Megarad (Si) isnow routinely achieved for digital, metal gate CMOScircuits specifically designed and processed forradiation hardness.
In previously reported work,4 it was shown thatlinear, metal gate NMOS and PMOS devices could befabricated which had radiation hardness comparableto that of digital CMOS devices. These lineardevices were built on junction isolated, (1-0-0) n-
type silicon substrates and utilized pyrogenicallygrown gate oxides. To attain the required breakdownvoltages, MOS device doping profiles were used whichwere different from those in digital devices, and thegate oxide thickness was increased to more than 1000.
The present paper reports the development of a
device fabrication process with which radiationhardened, linear metal gate CMOS devices can be pro-
duced simultaneously with linear complementary bipolardevices, each in dielectrically isolated silicon tubson a polysilicon substrate. The availability of thiscombination of devices on a single silicon chip makesa wide variety of analog bipolar-CMOS circuits avail-able for implementation in systems subjected toradiation environments. Also reported in this paper
is the significant enhancement of the hardness ofdigital CMOS devices obtained when the gate oxide isgrown pyrogenically instead of in dry oxygen.
Fabrication ProcessThe substrate material used for the linear
devices was dielectrically isolated and in a (1-0-0)orientation. The original starting material was n-type and had 3-5 ohm-cm resistivity. Standarddielectric isolation processing resulted in n-typesingle-crystal tubs with heavily doped n-type buriedlayers and in p-type single crystal tubs with dopingconcentrations which increased towards the bottom ofthe tubs. To increase hardness against transientgamma irradiation, the tub volumes (and hence thephotocurrent generation volumes) were reduced inthickness by about 35% to a nominal 15 vm. Thisnominal thickness will limit the photoqurrentgeneration to less than 7X10- via/mill (rad(Si)/sec).No transient response data, however, was taken forthis paper. Standard lapping and polishing techniqueswere used throughout the preparation of the material.
The processing steps, starting with the completedsubstrates, are outlined in Table I. Following avariety of wafer cleans, the wafers were given aninitial oxidation in steam to generate the field oxideand to provide for oxide masking of subsequent dopantimplants and depositions. The first photoresist stepdefined the p-wells, which were to be the bodies forthe n-channel MOS devices. These were located inp-type single crystal crystal tubs. A low dose(X900 Q/l) boron ion implant followed, along with ashort, high temperature diffusion cycle. The purposeof the implant and diffusion processes was to providea well controlled surface doping profile for the gateregions of the n-channel devices. If desired, highresistivity resistors could be formed in n-type tubsduring this process sequence.
RAD HARD GATE OXIDE MOS GATE REGIONS, CAPACITORS, ' 1200RFABRICATION CONTACT AREAS
CONTACT APERTUREDEFINITION
METAL LIZATION
PASSI VAT ION.
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The next photoresist step defined regions whichwere to be relatively lightly doped with phosphorus.These regions included the sources and drains of then-channel devices and the bases of vertical PNPtransistors. The n-channel sources and drains wereplaced within the previously defined p wells, and thePNP bases were placed in p-type single crystal tubs.Standard deposition and diffusion cycles resulted ina diffused phosphorus layer about two pm deep with asheet resistivity of about 150 Q/o .
The regions to be medium doped p-type were thendefined. These included the sources and drains of thep-channel devices, diffused resistors, and the basesof vertical NPN transistors. The p-channel devices,resistors, and the NPN transistors were fabricatedinto n-type single crystal tubs. The boron depositionand diffusion processes were standard and yielded a1.8 uim layer with a sheet resistivity of about 130 Q/a.
The next photoresist step opened up regions whichwere to receive a heavy boron deposition. Theseincluded contact areas on p-channel device sources anddrains, contact areas to p-type resistors, emitters forPNP transistors, collector contact areas on PNPtransistors, guardrings and P_ well contact areas onn-channel devices, and contact areas to the basesof NPN transistors. Capacitor bottom plates andcrossunders would be other applications for the heavyboron deposition. The design and purpose of theguardrings on the n-channel devices was the same asthat of the guardrings employed on radiation hardeneddigital devices. The boron deposition itself is apiloted operation, and the final deposition cycle ischosen to yield appropriate breakdown voltages andPNP transistor hFE's.
Regions to be heavily phosphorus doped wereopened next. These included contact areas on n-channeldevice sources and drains, emitters for NPN transistors,collector contact areas for NPN transistors, body tiecontact areas for p channel devices, contact areasfor the bases of PNP transistors, and crossunderregions. The heavy phosphorus deposition was alsopiloted, and the final deposition cycle was chosen toyield appropriate NPN transistor breakdown voltagesand hFE' s.
The regions which were to receive a gate oxidewere then defined. These were the CMOS device gates,all capacitors, and oversize contact aperture areas.The n-channel device gates were specifically designedfor radiation hardness and extended out to the p+guardrings located around the p- wells. The gateoxidation process was carried out below 9000C andconsisted of an oxidation in a pyrogenic ambientfollowed by an anneal in nitrogen at the same tempera-ture The target thickness for the gate oxide was1200R. The development of this gate oxidation cyclefor NMOS and PMOS devices has been discussed indetail in a previous paper.
The balance of the fabrication process wasstraightforward and consisted of the opening of contactapertures, flash evaporated aluminum metallization,interconnect patterning, the deposition of chemical-vapor-deposited SiO2 passivation, a 5000C sinter innitrogen, the patterning of bond pad windows, a 3500Cstabilization bake, and final probing and processing.The flash evaporation process for metallization wasrequisite for total dose hardness of metal gate MOSdevices. SEM analysis of completed wafers has shownthere are no step coverage problems associated withthe process. A cross section of completed devices isshown in Figure 1.
NPN PNP
Figue1 Cros S-ectonalaVe oLinea Bollector
N hnni-hne
and Linear Metal Gate CMOS Devices
The mask set used in conjunction with thisfabrication process contained a variety of MOS andbipolar devices. Data were taken on linear CMOSdevices having drawn channel lengths of 10, 10, and25 urn and respective channel widths of 13, 127, and127 pim. The bipolar devices investigated hademitter2areas of 260, 770, and 970 iimz (0.4, 1.2, and
The device characteristics produced by the processdescribed above are summarized in Table 2.
Table 2. Linear Device Electrical Characteristics
DEVICETYPE hFE BVCEO BVCBO BVEBO
NPN 200-260
PNP 100-130
DEVICETYPE
n-channel
p-channel
45V 70V 6.4V
35V 48V 8.2V
VT
1.8 -2.2V
1.8 - 2.5V
BVDSS
32V
35V
Irradiation Procedures
Each device was characterized initially and againafter irradiation. Post-irradiation characterizationbegan within minutes of the conclusion of theirradiation and was normally completed in 15 to 30minutes. Each device was irradiation only one time.This approach was taken to avoid the introduction ofany randomizing factors associated with multipleirradiations of devices or the exercising and debiasingof partially irradiated units. Using different devicesfor each irradiation introduced no systematic errorsinto the results; some change in the randomness of datacan be noted from dose level to dose level in thefigures, but not enough to alter any of the conclusionsdrawn. The irradiations were done with Harris Semi-conductor's Cobalt 60 source at a rate of about 157rad (Si)/sec. Several wafers were represented duringeach irradiation. The irradiation lots ranged in countfrom 4 to 12 assembled dice. Each assembled diecontained at least 4 and usually 6 test devices,depending on pinout. The dice were assembled into 16pin DIP's for characterization and testing.
All devices were biased for the duration of theirirradiation. The biasing for linear n-channel deviceswas +20 volts on the gate, 0 volts on source, drain,andbody. For linear p-channel devices, the biasing was+20volts on the source, body and gate, and 0 volts on thedrain.
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This biasing scheme approximates conditions en-countered in a linear CMOS circuit. The biasing oflinear bipolar devices was PNP emitter at +30 volts,PNP collector at 0 volts, PNP base open, and NPN co-llector at + 30 volts, NPN emitter at zero volts,and NPN base open. This open base configuration wasfound to produce slightly more hFE degradation than a
similar configuration in which the bases were shortedto their respective emitters.
Results and DiscussionA primary purpose of this investigation was to
learn whether dielectrically isolated substrates couldbe used for the production of radiation hardened CMOSdevices. The results for n-channel and p-channeldevices are shown respectively in Figures 2 and 3.
+3tox 1200]R
+2
+1
AVTN 0(VOLTS)
-2
-3
-4 - - -
104 105 106 107GAMMA DOSE (RADS (Si))
Figure 2. Threshold Shift of Linear n-channel Devices VersusGamma Dose
+3
A VTp(VOLTS)
105 1o6GAMMA DOSE (RADS (Si))
107
Figure 3. Threshold Shift of Linear p-channel Devices VersusGamma Dose
In these figures, the shift in one microampere thresh-old voltage is shown for each type of device as a
function of total gamma dose. The gamma dose isplotted logarithmically for clarity of display. Theshifts in threshold voltage were found to be indepen-dent of channel length and width for both p-channeland n-channel devices. The vertical bars in the plotsrepresent plus and minus one standard deviation inthe resulting data. As can be seen, the n-channeldevices at first underwent a negative shift inthreshold voltage. The effect saturated at about5X105 rads(Si) with a negative shift of just over
1.0 volt. As the gamma dose was further increased,the shift in threshold acquired a positive slope and,at the 1X107 rad(Si) level, the average thresholdshift was about+ 2.3 volts. For p-channel devices, no
saturation effect was observed. The threshold voltagesbecame continously more negative, and had shifted anaverage -1.25 volts at a gama dose of 1X106 rads (Si)and about -3.0 volts at lX107 rads (Si). The functionalforms of the threshold shifts were similar to thosecommonly reported in the literature for digital CMOSdevices. 5,6 The magnitude of the threshold shiftswas nearly the same as that reported earlier for thesame gate oxidation process applied to jurction iso-lated single crystal silicon substrates. It was,therefore, concluded that the use of dielectricallyisolated material as a substrate does not have adegrading effect on the radiation hardness of metalgate CMOS devices.
In the linear region of operation, the draincurrent of a CMOS device in a common-source con-figuration is related to the voltages applied to thedevice by 7/
ID 2 Leff(Vg VT) VDVD)' (1)
where ID is drain current, Z is channel width, 11 iscarrier mobility within the channel, CO is gate oxidecapacitance per unit area, Leff is the effectivechannel length, Vg is the applied gate voltage withrespect to the source, V is the device thresholdvoltage, and VD is the a4plied drain voltage withrespect to the source. A parameter
= ,u 0 (2)K - 2
can be defined, such that
I D =Le (2 ( Vg - VT) VD - VD)
Using K' and the threshold voltage for a device, itsdrain current can be calculated directly from geo-metrical device design data and information on thebiasing of the device. It should be noted that Eq.(3) applies only to the linear operating region of adevice (where VD < (Vg - VT)). The value of K' andits response to radiation are of interest to bothcircuit and device designers.
Figures 4 and 5 show the effect of total dose onK' for n- and p-channel devices, respectively. Tonormalize the results over a range of thresholdvoltages, K' is plotted as a function of V - VT.The drawn lines represent averages, and the verticalbars indicate the range of values measured beforeirradiation. Before irradiation, the n-channel K'value first increased with increasing gate bias due toeffects of the P_ well doping profile. As the gatebias was further increased, K' decreased due to highfield effects in the gate region. The n-channel K'values were not signifipantly affected by gamma dosesof less than about 2X10 rads(Si). By 106 rad(Si),KI was reduced by as much as 50% at low gate voltages,and by 107 rads(Si) it was reduced by nearly an orderof magnitude at the low biases. In p-channel devices,K' decreased monotonically with increasing gatevoltage. The uniform doping of the p-channel bodiesprecluded the low bias voltage effects seen in the n-channels. The p-channel K' was lower in pre-irradiation value than the n-channel K', due to thelower mobility of holes in silicon. As in the n-channel devices, little degradation in K' value wasnoted for gamma doses of less than about 2X105 rads(Si). Degradation of K' in p-channel devices was lessthan that in n-channel devices, with a maximum decrease
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(3)
tox 1200RI I~~~~~~~~~~~~~~
+2-
+1
01 i
1
-2
-3
-4 1 --.
of about 30% noted for low biases after a dose of 107rads(Si). At high gate biases for both n-channel andp-channel devices, the degradation of mobility, andhence K', was much less. This is consistent githearlier findings reported in the literature.
10
9
8
7
6k'
(A-' ) 5
4
3
2
0
The effects of gamma dose on the gains of linear NPNand PNP bipolar transistors are presented respectivelyin Figures 6 and 7. About 12 NPN and 12 PNP deviceswere subjected to each gamma dose level. Pre-irradiation hFE values varied over about a factor of 2
in magnitude and all device hFE's degraded proportion-ately to one another with irradiation. The datapoints in the figures represent typical values of hFEand are plotted over several orders of magnitudeof emitter current density. Both NPN's and PNP'sexhibited the expected pre-irradiation characteristics.Significant hFE degradation at low current densities
occurred at gamma fluences of as little as 104 rads(Si).The hFE degradation decreased with increasing emitter
current density. An operating emitter current densityof about 80 A/cm2 (about 500 vA/mil2) appears optimalfor minimizing the radiation effegts on NPN and PNPhFE. After a gamma fluence of 10 rads(Si), the NPN
hFE at this current level was about half its pre-
irradiation value; the PNP h was about one third ofits pre-irradiation value. The degradation of hFE wasindependent of the geometrical designs and emitterareas of the three types of devices characterized andtested.
300 1
2502 3 4 5 6 7
Vg-VT (VOLTS) 200hFE
150Figure 4. Total Dose Degradation of k' Values forLinear n-channel Devices
4
3
k'
( V22
0
100
50
n
175
150
125
100hFE
75
50
25
2 3 4 5 6 7
Vg-VT (VOLTS)
Figure 5. Total Dose Degradation of k' Values forLinear p-channel Devices
-"V
*oo
0.1 1.0 10.0 100.0 1000.0
JE (AMPS /CM2)
Figure 6. Total Dose Degradation of NPN hFE's
0.1 1.0 10.0 100.0
JE (AMPS/CM2)
Figure 7. Total Dose Degradation of PNP hFE's
1000.0
1724
OB= 104 RADS
OB 105 RADS
101,07,1OA, =1
006WB 00000,
I-e
I
Application to Digital CMOS ProcessingThe total dose degradation o served in linear
metal gate CMOS devices with 1200A thick pyro-genically grown gate oxides were comparable to thosenormally observed in digital CMOS devices having muchthinner gate oxides grown in dry oxygen. As radiationeffects in MOS devices vary as t n, where 2<n<3,it was thought that some improvement in the hardnessof digital CMOS devices could be realized if the gateoxide was grown pyrogenically instead of in dry oxygen.The pyrogenic process used for the linear devices wasmodified to yield 60O0 of oxide and was inserted intothe standard fabrication process for radiationhardened digital metal gate CMOS devices.
The results of the modified process are shown inFigures 8-10. The irradiation procedure was identicalto that used for the linear CMOS devices, except thatthe bias voltage was +10 volts. Figures 8 and 9illustrate the shifts in n-channel and p-channel thres-hold voltages, respectively, and Figure 10 illustratesthe total dose degradation of K'. The dry 02 oxida-tion curves in Figures 8 and 9 were obtained byaveraging the total dose degrada ion characteristicsof several wafer lots having 675: gate oxides gpownin dry 02. The results were then scaled to 600A bythe cube of the oxide thickness and plotted. As canbe seen, the n-channel threshold shift gas improved bya factor of about 3 over the 0.3-1. X10 rad(Si) gammafluence range. The p-channel threshold shift wasvirtually unaffected by the pyrogenic process. Aftera total dose of 3.6X10/ rads(Si), the n-channelthreshold shift was +1.1 volts and the p-channel shiftwas -1.5 volts. Further testing of both pryogenicgate oxide and dry oxygen gate oxide devices to totaldose levels of 1O rads(Si) or more is in progress.
The K' values in Figure 10 were higher for thedigital devices than for the linear devices due tothe narrower gate oxide involved and correspondinglyhigher MOS gate capacitances. The radiation effectson digital device and linear device K'S were similar,though the digital device K' values were lesssensitive to radiation.
SummaryThe results of this project confirm that radia-
tion hardened metal gate CMOS devices can be fabri-cated simultaneously with complementary linear bipolardevices, all in dielectrically isolated silicon sub-strate materials. Radiation hardness has been demon-strated to 107 rads(Si) for the CMOS devices and to106 rads(Si) for the bipolar devices. The availa-bility of this combination of radiation hardenedlinear devices will provide circuit and systemsdesigners with a means for incorporating analogfunctions into government and military systems whichmust withstand certain radiation environments.
The pyrogenic gate oxidation process used for thelinear devices, when applied to a radiation hardeneddigital CMOS process, produced devices hard to morethan 3.5X10 rads(Si). The n-channel deyices weresignificantly harder over the 0.3-1.0X106 rad(Si)range than those processed with the dry oxygen gateoxidation process normally used for achieving hardness.These findings warrant further study to assess thecomplete potential of pyrogenic gate oxidations aspart of the optimal fabrication process for radiationhardened digital CMOS devices.
+1.5
a VTN(VOLTS)
-2.0 '105 i06 107 108
TOTAL DOSE (RAD (Sill
Figure 8. Threshold Shift of Digital n-channel DevicesVersus Gamma Dose
AVTp(VOLTS)
+1.5
+1.0
-to. 600R+0.5.
X PYROGENIC OXIDATION
0.0
-0.5 _
DRY O2OXIDATIO N-1.0 I
-1.5
-20 .- l106
TOTAL DOSE (RADSI Si)108
Figure 9. Threshold Shift of Digital p-channel DevicesVersus Gamma Dose
20
18
16
14
12k'
(JA- 10( V2 )
8
6
4
2
0 1 2 3 4 5 6 7 8
V9-VT (VOLTS)
Figure 10. Total Dose Degradation of k' Valuesfor Digital CMOS Devices
1725
107
Acknowl edgements
The author wishes to thank Joe Boarman, TomSanders and Jim Schroeder for many helpful technicaldiscussions, Roger Milner and Anne Wakefield forcharacterizing the devices and performing theirradiations, and Rhea Cohen for typing the manuscript.
References
1. Pikor, A. and Reiss, E. M., "TechnologicalAdvances in Manufacture of Radiation-HardenedCMOS Integrated Circuits", IEEE Trans. Nucl.Sci., NS-24, 2047 (1977).
2. Sanders, T. J., "CMOS Hardness Assurance ThroughProcess Controls and Optimized Design Procedures",IEEE Trans. Nucl. Sci., NS-24, 2051 (1977).
3. Derbenwick, G. and Gregory, B., "ProcessOptimnization of Radiation-Hardened CMOSIntegrated Circuits", IEEE Trans. Nucl. Sci.,NS-22, 2151 (1975).
4. Sanders, T. J. and Ports, K. A., "Radiation-Hardened Devices for Linear Circuit Applications",IEEE Trans. Nucl. Sci., NS-25, 1465 (1978).
5. London, A. and Wang, R. C., "Dose Rate andExtended Total Dose Characterization ofRadiation Hardened Metal Gate CMOS IntegratedCircuits", IEEE Trans. Nucl. Sci., NS-251173 (1978).
6. Freeman, R., and Holmes-Siedle, A., "A SimpleModel for Predicting Radiation Effects in MOSDevices", IEEE Trans. Nucl. Sci., NS-25, 1216(1978).
7. Sze, S. M., Physics of Semiconductor Devices,Chapter 10, John Wiley & Sons, Inc., (1969).
8. Whitefield, J. E., Southward, H. D., andMaier, R. J., "Total Dose Effects on SurfaceState Density, Carrier Concentration andMobility in MOS Layers", IEEE Trans. Nucl.Sci., NS-23, 1549 (1976).
9. Viswanathan, C. R., and Maserjian, J., "Modelfor Thickness Dependence of Radiation Chargingin MOS Structures", IEEE Trans. Nucl. Sci.,NS-23, 1540 (1978).
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