IEEE Transactions on Nuclear Science, Vol. NS-27, No. 1, February 1980
A QUADRATIC ANALOG-TO-DIGITAL CONVERTER
Harrison, D.C.; Staples, M.H.American Science and Engineering
Abstract
In background noise limited instrumentation systems,an analog-to-digital converter with a square roottransfer function will allow a maximum dynamic rangewith a fixed number of data bits. The converterdescribed herein was developed to digitize theoutput from a CCD in a space environment wheretelemetry is limited. The goals of low powerdissipation, moderately fast conversion time, andreliability have been achieved using standardcomponents and avoiding non-linear elements.
Introduction
Many detector systems are used to measure phenomenawhose characteristics are either variable or notwell known. As a result, the detectors must operateover a wide dynamic range, extending from darkcurrent to saturation. A digital signal processingsystem which supports the detector is then requiredto accept a large number of binary bits describingeach digitized data point. A detector systemintended for spaceflight has the additionalconstraint of limited telemetry rate. To cope withthe large data volume, previous systems have usednon-linear analog elements prior to digitization orhave encoded the converted digital data usingvarious compression algorithms.
This quadratic analog-to-digital convertereliminates the need for non-linear analog elements,which are generally slow and unstable, and providesa two-fold reduction in the digital data handlingrequirements. The transfer function is not a trueinformation preserving compression method butmaintains a constant signal to noise ratio for thosedetectors whose output is shot noise limited. The
V SUCCESSIVPDAT-ANA D APPROXT
converter to be described was developed for use witha pair of charge coupled device imaging detectors inthe White Light Coronagraph/X-ray XUV Telescope(CXX) experiment to be flown as part of the InternalSolar Polar Mission, a five year interplanetaryflight.(l) The Principal Investigator for the CXXis Robert M. MacQueen of the High AltitudeObservatory, National Center for AtmosphericResearch. Co-Principal Investigators are Allan S.Krieger of American Science and Engineering, MartinJ. Koomen of the Naval Research Laboratory, andArthur B. C. Walker of Stanford University. Thespecific circuitry shown is selected to meet missionrequirements for an eight bit digitization with a 40microsecond maximum conversion time and a powerdissipation less than 400 milliwatts. The generaltechnique can readily be modified for fasterconverters or ones with higher resolutions.
General Description
A block diagram of the topology for a quadraticanalog-to-digital converter is shown in Figure 1.The general form of the converter is that of astandard linear successive approximation converterin which a digital-to-analog converter issuccessively driven by trial codes until acomparator determines the largest output code whichhas an analog value less than the input analogsignal. The quadratic converter generates a linearrepresentation of the trial code (V1) with astandard linear digital-to-analog converter. Thelinear representation is then used as the referencevoltage of a second digital-to-analog converterwhose output (V2), controlled by the trial code,is proportional to the square of V1. V2 iscompared to the input voltage of the converter togenerate successive trial codes as is done in a
Figure 1 Square Root ADC Block Diagram
The work presented here was performed undersubcontract NCAR S9003 under UCAR's Prime ContractATM-77-23757 with the National Science Foundationthrough a transfer of funds from the NationalAeronautics and Space Administration.
linear converter. The final trial results in avoltage (V2) that is a close approximation to theinput voltage. Since V1 is proportional to thesquare of V1 and the digital code is a linearrepresentation of V1, the input approximates thesquare of the digital code, or, in other words, thedigital code approximates the square root of theinput vol tage.
When the output of the converter is a digital wordof N bits, the dynamic range covered by V2 is(2N)2 or 22N. The dynamic range of theconverter equals the dynamic range of a linearconverter having twice as many bits.
For those applications which can accomodate a squareroot transfer function, a quadraticanalog-to-digital converter can halve the data rate,or allow sampling to occur twice as fast with afixed data rate.
Circuit Description
Figure 2 shows a schematic representation of asquare root analog-to-digital converter designed fora specific application. The circuit is controlledby successive approximation register Ul. Ul drivesdigital-to-analog converters U2 and U3 whichgenerate a voltage compared with the analog input bycomparator ARl. U4 and U5 are latched bus bufferswith three state outputs. The conversion rate ofthe circuit is governed by PADC-CLK, a 250 KHzclock. This clock fixes the successiveapproximation rate at 4 microseconds per bit. Ulrequires nine clock pulses per eight bit conversionresulting in a 36 microsecond conversion time. Thebinary trial codes from Ul are fed to the inputs ofU2, a CMOS digital-to-analog converter. U2 is aswitched resistor ladder network which must beloaded at its output with a very low impedance, suchas a summing node. The network includes a matchedresistor used as a feedback element. AR2 isconnected to U2 to form a digital-to-analogconverter whose output magnitude is proportional tothe digital code and the reference voltage input,but whose polarity is opposite to that of thereference voltage. The output voltage from U2 withAR2 is used as the reference voltage for a digital.
to-analog converter consisting of U3 with AR3, withthe result that the output of AR3 has the samepolarity as the reference voltage for U2. Thereference voltage for U2 is nominally +7V.
A conversion is initiated by setting PADC-SC lowprior to a positive transition of PADC-CLK. Thissets the most significant bit of Ul (Q7) to a logiclow and all the other bits to logic high. This datais presented to U2 and 03. AR2 then has an outputof -7 x 127, 256 or -3.4V which is used as thereference for U3. AR3 has an output voltage equalto 3.47 x 127 + 256 or +1.27V, which is compared tothe analog input (PDAT-ANA) by ARl.
I f PDAT-ANA is greater than 1.27V, a logic one ispresented to the D input of U1 by AR1; at the nextpositive clock transition, Q7 is set to logic oneand Q6 is set to logic zero. If PDAT-ANA is lessthan 1.27V, AR3 drives the D input with a logiczero, which leaves Q7 at logic zero and sets Q6 tologic zero at the next positive clock transition.This sequence continues until all eight outputs ofU1 have been tested and set to the proper value.After Q9 has been sampled, Ul signals that theconversion is complete by setting CC to logic zero.The transition is used by the delaying inverterconsisting of Ql and associated components to loaddata into U4 and U5 for buffer storage. CC,relabelled PBUSY, is monitored by the data system asa data ready flag. PDAT-STR is a signal from thedata system which places the contents of U4 and U5onto a system data bus.
Some Design Considerations
Component selections and circuit layout are normallyvery important in any analog-to-digital converterdesign and are even more important when analogdynamic ranges are expanded. The eight bit squareroot analog-to-digital converter (shown in Figure 2)has an input dynamic range equivalent to sixteenbits. All layout and most component selection mustthen be done as if the converter had a sixteen bitlinear dynamic range.
Full scale errors cannot be specified in the normalway, since at full scale the LSB is equal to about54mV whereas near zero the LSB equals 100 microvolts.
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P/0 Pi
RIPADCPADC
- 0 (MsB)
- 2_ 3
_ 567 (L 4B
Absolute gain error can be twice that allowed for alinear eight bit analog-to-digital converter, butoffset errors must be held to levels consistent withthe desired input dynamic range. Prime voltageoffset drivers are the errors in AR1 and AR3.Errors in AR2 are important, but are calculated onthe basis of an eight bit converter, as U3attenuates the AR2 signal at all codes less than themaximum code. ARI and AR3 errors, however, directlyaffect the accuracy of the code conversion and inputsignal comparison. Because of the topology of U3,input voltage offset errors on AR3 have a gainranging from +1 at very low digital codes to +2 atmaximum code. The offset error allowed at theoutput of AR3 is identical with the input offseterror at low codes. As the LSB grows rapidly, theallowed error increases faster than the offset gainchange.
Figure 2 shows offset adjustments for AR3 and AR1.Parts requiring trimming are used because ofstringent power limitations in the application forwhich the circuit was developed. Applications withless restrictive power budgets have the option ofusing more precise parts to achieve higher untrimmedaccuracies.
Acknowldgements
We wish to thank Robert M. MacQueen of the HighAltitude Observatory, the Principal Investigator,for his forebearance and useful comments during thedevelopment of this circuit. We also wish to thanksome of our associates at AS&E; Allen S. Krieger, ACo-Prinicipal Investigator for his encouragement,Klaus Kubierschky for his incisive advice and RudiVasquez for building the breadboards. Last, but notleast, we thank our typist, Ellie Valminuto, whomanaged to transform our editted drafts into finalcopy under impossible time constraints.
Re ferences
1. Harrison, D.; Kubierschky, K.; Staples, M.;and Carpenter, C.; CCD Camera System andSupport Electronics for a White LightCoronagraph and X-ray XUV Solar Telescope,submitted to IEEE 1979 Nuclear ScienceSymposium.
The circuit can be trimmed to a true sixteen bitinput dynamic range and remain stable over a periodof several weeks.
Conclusion
A quadratic analog-to-digital converter can readilybe made using standard components without resortingto non-linear analog techniques. The resultingconverter can be made highly precise and verystable. For systems which are noise limited, theconverter may allow either a double sample rate or
halved storage requirement compared to a linearanalog-to-digital converter which has to cover thesame dynamic range. In the space flight applicationfor the International Solar Polar Mission the datareduction allows an increase in the number of CCDimages that can be telemetered to ground.
