Sai Vineel Reddy Chittamuru, Srinivas Desai, Sudeep Pasricha Department of Electrical and Computer Engineering Colorado State University, Fort Collins, CO, U.S.A.
ABSTRACT On-chip communication is widely considered to be one of the major performance bottlenecks in contemporary chip multiprocessors (CMPs). With recent advances in silicon nanophotonics, photonic-based networks-on-chip (NoCs) are being considered as a viable option for communication in emerging CMPs as they can enable higher bandwidth and lower power dissipation compared to traditional electrical NoCs. In this paper, we present UltraNoC, a novel reconfigurable silicon-photonic NoC architecture that features improved channel sharing and supports dynamic re-prioritization and exchange of bandwidth between clusters of cores running multiple applications, to increase channel utilization and performance. Experimental results show that UltraNoC improves throughput by up to 9.8× while reducing latency by up to 55% and energy-delay product by up to 90% over state-of-the-art solutions.
Categories and Subject Descriptors C.2.1 [Computer-Communication Networks]: Network Architecture and Design—Network topology; C.4 [Performance of Systems]: design studies Keywords Network-on-chip (NoC), photonic channel sharing, arbitration
1. INTRODUCTION Advances in technology scaling over the past decade have
enabled the integration of billions of transistors on a single die. Such a massive number of transistors has allowed multiple processing cores and more memory to be integrated on a chip, to meet rapidly growing performance demands of modern applications. With hundreds of on-chip cores expected to become a reality in the near future, traditional electrical network-on-chip (NoC) communication fabrics [1], [2] are projected to suffer from cripplingly high power dissipation and severely reduced performance [7]. Crosstalk and electromagnetic interference in metallic interconnects will further worsen the performance and reliability of NoCs with technology scaling.
Recent developments in the area of silicon photonics have enabled their integration with CMOS circuits. On-chip photonic links provide several prolific advantages over their metallic counterparts, including light speed transfers, high bandwidth [3] density by using dense wavelength division multiplexing (DWDM) [3], low power dissipation [4], and low crosstalk [7]. Thus silicon photonics is being considered as an exciting new option for future NoCs. Several photonic devices such as microring resonators, waveguides and photodetectors have already been fabricated and demonstrated at the chip level [5], [6].
These devices have been used as a foundation for several photonic network architectures [8]-[11].
A few prior works emphasize the importance of network resource contention in photonic channels and proposed arbitration techniques to resolve contention [8], [10]. However, a limitation of these approaches is that they do not fully exploit available network bandwidth. Another limitation is that these approaches typically only target single parallel application workloads. In emerging multicore systems where multiple applications execute simultaneously on unique subsets of cores, there is significantly greater variation in temporal and spatial characteristics of network injected traffic. For example, cores running memory intensive tasks can require more network bandwidth than cores running compute intensive tasks [24].
To overcome these shortcomings, we propose a novel photonic NoC architecture called UltraNoC that utilizes multiple-write-multiple-read (MWMR) photonic waveguides in a crossbar topology, and supports dynamic performance adaptation to aggressively utilize network bandwidth and meet diverse application demands. We compare UltraNoC against architectures with the best-known arbitration mechanisms, for multi-threaded PARSEC [16] workloads on CMP platform sizes ranging from 64-cores to 256-cores. The novel contributions of this paper are:
A flexible on-chip photonic network architecture (UltraNoC) that facilitates selective and reconfigurable prioritization of applications based on their time-varying performance goals;
A concurrent token stream arbitration that provides multiple simultaneous tokens and increases channel utilization;
A dynamic bandwidth transfer technique with low overhead, to transfer unused bandwidth among clusters of cores;
A mechanism to monitor traffic being injected into the network by different co-running applications, to facilitate dynamic arbitration wavelength injection rate modulation.
2. RELATED WORK A considerable amount of work has focused on the area of
photonic NoC design. Several efforts have explored high-radix low-diameter photonic crossbar architectures that provide non-blocking connectivity, e.g., [8], [10], [15] and [21]; whereas silicon photonic implementations of low-radix high-diameter NoCs have also been investigated in [14], [17], [18], and [20]. Prior work has shown that photonic crossbars are extremely promising architectures to meet future on-chip bandwidths demands, but they can suffer from (i) large power dissipation and (ii) high contention for resources, especially when using inefficient token-based arbitration schemes. A few techniques to reduce power overhead of photonic NoCs have been proposed in literature. For example, an effective policy for runtime management of the laser source is proposed in [11]. We build on their work to manage power in photonic crossbar NoCs. To reduce contention issues in crossbars, a few improved arbitration techniques have been proposed in [10], [22] that use time division multiplexing (TDM), so that a single data waveguide can be simultaneously used by more than one node in different time slots.
A Reconfigurable Silicon-Photonic Network with Improved Channel Sharing for Multicore Architectures
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65
conversion from its current cluster arbitration wavelength to the next cluster arbitration wavelength, a counter (shown in figure 3) is incremented. This conversion event represents the case where an unused arbitration slot (bandwidth) is transferred from one cluster to another. Over a time interval T, the recorded wavelength conversion counts WCC0 – WCC3 from each cluster are then used to determine unused bandwidth of each cluster.
Step 2: Calculation of excess arbitration slots: The wavelength conversion count values of different clusters show the aggregated number of excess arbitration slots, which includes excess arbitration slots of the present cluster along with the excess arbitration slots of predecessor clusters. Therefore the excess arbitration slots for the ith cluster (ESi) are calculated using equation (1) shown below, by subtracting the cluster wavelength conversion count of the predecessor cluster (WCCi-1) from the wavelength conversion count of the cluster under consideration (WCCi). ESi values can also be negative, when a cluster consumes a greater number of arbitration slots (made available by predecessor clusters) than its allocated arbitration slots. Such a cluster has a deficit of arbitration slots. ES = WCC ,i = 0WCC −WCC , i > 0 (1)
Step 3: Setting new weight (priority) for each cluster: Based on the estimation of excesses and deficits in arbitration slots assigned across clusters, this final step attempts to adjust weight values of each cluster to eliminate the excesses and deficits. To determine the new weight of the ith cluster wi(next) for the upcoming time interval, we must subtract the excess weight EWi of the cluster from its current weight wi(current). We can calculate EWi by dividing the excess arbitration slots of the ith cluster (ESi), calculated in equation (1), by the total number of arbitration slots released in the time interval T, which we denote as K. The equations below show these calculations: EWi=ESi/K(2)wi(next)=wi(current)–EWi(3)
Based on the values of the new weights, the LSWC changes the distribution of arbitration wavelengths injected for the next time interval T, such that a cluster with a higher weight will receive more arbitration wavelengths, and has more opportunities to use the waveguides for data transfer. The weight values are also communicated to all clusters, so that arbiters can adjust their local counters to match the new arbitration slot profile in waveguides.
4. EXPERIMENTS 4.1 Experimental Setup
To evaluate our proposed UltraNoC architecture, we compared it to an electrical mesh (EMesh) based NoC as well as to two state-of-the-art photonic crossbar NoCs that use smart arbitration techniques: Flexishare with token stream arbitration [10] and Corona with an enhanced token-slot arbitration [22]. We modeled and simulated the architectures at a cycle-accurate granularity with a SystemC-based NoC simulator, for two CMP platform complexities: 64-core and 256-core. We used the PARSEC benchmark suite [16] to create multi-application workloads, with clusters running parallelized versions of different benchmarks.
Table 1 shows the PARSEC benchmarks we considered, classified into three categories according to their memory intensities. Compute intensive benchmarks spend most of the time computing and less time communicating with memory; whereas memory intensive applications spend a larger portion of their execution time communicating with memory and less time computing within cores. Hybrid intensity benchmarks demonstrate both compute and memory intensive phases. We created 12 multi-application workloads from these benchmarks. Each workload
combines 4 benchmarks, and the memory intensity of the workloads varies across the spectrum, from compute intensive to memory intensive. As an example, the SC-BT-BS-VI workload combines parallelized implementations of Streamclusters (SC), Bodytrack (BT), Blackscholes (BS) and Vips (VI), and executes them in clusters C0, C1, C2, and C3, respectively. Each parallelized benchmark is executed on a group of 16 cores and 64 cores, in the 64-core and 256-core CMP platforms, respectively. Full-system simulation of parallelized PARSEC benchmarks using gem5 [25] was used to generate traces that were fed into our cycle-accurate network simulator. We set a “warm-up” period of 100M instructions and captured traces for 1B instructions.
Table 1: Memory intensity classification of PARSEC benchmarks
Application Representation Workload Type Blackscholes BS Compute intensive Bodytrack BT Compute intensive Vips VI Compute intensive Dedup DU Compute intensive Freqmine FQ Hybrid Ferret FR Hybrid Fluidanimate FA Hybrid X264 X264 Hybrid Streamclusters SC Memory intensive Canneal CA Memory intensive Facesim FS Memory intensive Swaptions SW Memory intensive
We targeted 32nm and 22nm process technologies for the 64-core and 256-core CMPs, respectively. Based on the geometric calculation of the waveguides for a 20mm×20mm chip dimension, we estimated the time needed for light to travel from the first to the last node in a single pass of the MWMR waveguide group in UltraNoC as 8 cycles at 5 GHz clock frequency. The same clock and 8 cycle round trip time is also applicable to the waveguides in the Flexishare and Corona photonic crossbar NoCs. Throughout our analysis we use a flit size of 64 bits for EMesh and a total packet size of 512 bits for all photonic NoC architectures. We consider data modulation at both clock edges to enable simultaneous transfer of 512 bits in a single cycle, in the UltraNoC, Flexishare, and Corona architectures.
The static and dynamic energy consumption of electrical routers is based on results obtained from the open-source DSENT tool. Energy consumption of various photonic components for all the photonic NoC architectures are adopted from photonic device characterizations in line with state-of-the-art proposals [19], [23] and shown in Table 2. Here Edynamic is the energy/bit for modulators and photodetectors and Elogic−dyn is the energy/bit for the driver circuits of modulators and photodetectors. PMWMR and PMWSR are the static power consumption of an MWMR and an MWSR waveguide group, respectively which includes the power overhead of ring resonator thermal tuning. We consider a ring heating power of 15 µW per ring and detector responsivity of 0.8 A/W [19]. To compute laser power consumption, we calculated photonic loss in components, which sets the photonic laser power budget and correspondingly the electrical laser power.
Finally, based on our gate-level analysis, area overhead due to electrical circuitry (e.g., adders, multipliers) in LSWC is estimated to be 0.011mm2 at 32nm. We set the reconfiguration delay overhead in UltraNoC to be 20 cycles to account for the time to transfer wavelength conversion counter values from each cluster to LSWC, time to determine new priority weights of each cluster, and to update these values in arbiters in each cluster. We set reconfiguration time interval window size in UltraNoC to 300 cycles, to balance reconfiguration overhead and performance.
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res architectureP platform by inur to enable hilability study. Wcy, and EDP for
andUltaNoC-16
as shown in access to the %, 32% and wer average pectively for
of UltraNoC-4-core CMP.
comparison on average
compared to UltraNoC-16 and EMesh. consumed in nic hardware or modulator pace) shows d 50% less
NoC-16 uses UltraNoC-16 NoC-16 uses tatic energy) t delay for
e scalability. ncreasing the igher traffic
We evaluated all photonic 6, we also
67
cwethhgTacUacrUEherUha
F8c
ohwin
considered Ultrawaveguide grouexperiments. Frohat on average
has 5.7×, 5.3× angreater throughpThe improvemenand Corona are ecore CMP case. FUltraNoC-8 has and 53% and Ultcompared to Cespectively. Fi
UltraNoC-8 has EMesh, Corona ahas 77% and 73energy delay espectively. Th
UltraNoC-16 anhardware used inalso reduces its th
Figure 5: (a) throu8, UltraNoC-16 acore CMP. Result
From the aboveof UltraNoC thhardware comparwith low as wendicator of the s
aNoC-32, a varups. Figures 5(aom the throughpUltraNoC-8 hasnd 5.7×, and Ul
put compared tonts in throughpeven better for thFrom figure 5(b)23%, 25% and 4traNoC-32 has 3Corona, Flexishinally, Figure
88%, 87% anand Flexishare r3% and UltraNproduct comp
he lower EDPnd UltraNoC-32n Flexishare, whhroughput and in
(
(
ughput (b) latencnd UltraNoC-32
ts are normalized
e results, we canhat can achievred to existing p
ell as high corescalability of our
riant of our arca)-(c) show theput results it cans 3×, 2.8× and 2ltraNoC-32 has o EMesh, Coronut for UltraNoChe 256-core CM), it can be seen 48%, UltraNoC-34%, 36% and 5hare and EM5(c) shows t
d 20% lower Erespectively. Fur
NoC-32 has 55%pared to EMeP of Flexisha2 is due to theich lowers its poncreases its laten
(a)
(b)
(c)
cy (c) EDP compawith other archiwrt EMesh.
n summarize thate better perfor
photonic NoCs, fe counts. The rer proposed Ultra
chitecture with e results of then also be inferr
2.6×, UltraNoC-9.8×, 9× and 9.7
na and FlexisharC over Flexisha
MP, than in the 6that on an avera-16 has 29%, 3055% lower laten
Mesh architecturthat on averaEDP compared rther UltraNoC-
% and 51% lowesh and Coroare compared e lower photonower footprint, bncy.
arison of UltraNoitectures for a 25
t there are varianrmance with lefor CMP platformesults are a go
NCLUSIONthis work we cture that featurng an aggressivey. UltraNoC ar bandwidth bee co-running aion and adapt UltraNoC impro
and EDP by up art photonic Nion mechanismsunts on a chip.
KNOWLEDresearch is sup
00, CCF-130269
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