Adam Rose

Questa VIP Product Marketing Manager

Verification IP : Trends and Products for ASIC and FPGA

www.mentor.com

© 2014 Mentor Graphics Corp. Company Confidential

Mentor Enterprise Verification Platform (EVP) Tools and automation for entire verification flow

ARM Techcon: PCIe subsys verif, JSP - Oct, 2014 2

VIRTUAL

PROTOTYPE FORMAL SIMULATION EMULATION

Verification Infrastructure and VIP

Debug Measurement

& Analysis Stimulus

Common User Views — Portable stimulus — Unified measurement & analysis — Common HW & SW debugging

Common Infrastructure — IP compliance & conformance — Subsystem performance — Full system integration

High Performance Engines — Architectural exploration — Formal automation — Multi-core simulation — System level emulation

www.mentor.com

© 2014 Mentor Graphics Corp. Company Confidential

Mentor Enterprise Verification Platform (EVP) Includes integrated verification IP

ARM Techcon: PCIe subsys verif, JSP - Oct, 2014 3

VIRTUAL

PROTOTYPE FORMAL SIMULATION EMULATION

Verification Infrastructure and VIP

Debug Measurement

& Analysis Stimulus

Common User Views — Portable stimulus — Unified measurement & analysis — Common HW & SW debugging

Common Infrastructure — IP compliance & conformance — Subsystem performance — Full system integration

High Performance Engines — Architectural exploration — Formal automation — Multi-core simulation — System level emulation

www.mentor.com

© 2014 Mentor Graphics Corp. Company Confidential

Verification IP solves IP integration and verification challenges

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Mentor Verification IP is a complete solution

Rapid integration and adoption — Standards based SV UVM support — Complete agent/driver/monitor

functionality — New features to ease integration

& configuration

Complete protocol assurance — Comprehensive test suite, checking

& coverage — Supports all device types

– E.g PCIe: RC, EP, PHY, Switch

High performance verification — Optimized simulation models — Synthesizable transactors for testbench

acceleration

Transactions

Configuration

Agent

Test Plan Coverage Test Suite Protocol Debug

interface

DUT

UVM Agent

(Transactor/BFM)

www.mentor.com

© 2014 Mentor Graphics Corp. Company Confidential

Built using SystemVerilog for UVM

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Connect and reuse standard UVM components — Agents, TLM ports, sequences, sequence items, config

PCIe IP DUT

AXI IF AXI Agent

PIPE PCIe PIPE

Agent

Virtual Sequencer

Scoreboard

ENV

TEST

Test Config

Test Sequence

Sequence item

www.mentor.com

© 2014 Mentor Graphics Corp. Company Confidential

Re-usable Protocol Test Plans

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Test Plan built from protocol specification — Section, title and description

XML format — Excel and Word

100s of items — AHB Full has ~200 items

Links to supplied coverage

Test sequences provided — Achieve 100% protocol coverage

www.mentor.com

© 2014 Mentor Graphics Corp. Company Confidential

Verify protocol behavior with complete test suite and coverage

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AXI Agent

Test Sequence SCORE

BOARD

AXI SLAVE

DUT

Coverage

VIP Component

User component

User design

Test plan, test suite Test plan, test suite and coverage Test plan

www.mentor.com

© 2014 Mentor Graphics Corp. Company Confidential

Quickly understand and analyze bus activity

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Highlighting links transaction and signal activity

Highlighting shows which

signals and WHEN

Relationship works BOTH

ways

www.mentor.com

© 2014 Mentor Graphics Corp. Company Confidential

Complete checking for protocol compliance

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Assertions check for any protocol violations

www.mentor.com

© 2014 Mentor Graphics Corp. Company Confidential

IP integration and Verification Challenges

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Protocols are complex — Long learning curve to verify effectively

Schedule pressure — Need to develop Testbench quickly — Can’t always wait for design — Find bugs quickly

Design complexity requires many tests — Need to abstract, re-use and automate — Use acceleration or emulation to complete tests in time

www.mentor.com

© 2014 Mentor Graphics Corp. Company Confidential

Mentor VIP

11

Completely independent from design IP

Tests, stimulus, coverage, testplans, slave models, scoreboards, compliance tests – all unencrypted UVM compliant SV

Mature Pre-Sales Discovery Process

All Support Requests get meaningful answers within 24 hours

Expert help and advice always available

Pre-defined and custom VIP consulting packages available if needed

Pre-defined verification kits available for commonly used design IP

www.mentor.com

© 2014 Mentor Graphics Corp. Company Confidential

ROI for Mentor Verification IP

12

A production environment

is in place

That is learned

while in use

A lot must be learned

Before a production

environment is operational

Without Questa VIP

A lot must be learned

before the environment

is operational

With Questa VIP

The environment is

in place and can be

learned while in use

Learning Curve Productivity Curve

Learning Curve Productivity Curve