QUADRA T URE P H ASE SHIFT KEYING MODULAT I O N TECHNIQUES

OBJECTIVE:ƒ Study of Carrier Modulation Techniques by Quadrature Phase Shift

Keying method.

EQUIPMENT:ƒ Experimentor Kit ADCL-02-03.ƒ Connecting Chords.ƒ Power supply.ƒ e-Lab

THEORY:In this modulation, called Quadrature PSK (QPSK) or 4 PSK the sine

carrier takes 4 phase values, separated of 90 deg. and determined by the combinations of bit pair (Dibit) of the binary data signal. The data are coded into Dibit by a circuit generating:

A) A data signal I (in phase) consisting in voltage levels corresponding to the value of the first bit of the considered pair, for duration equal to 2 bit intervals.B) A data signal Q (in quadrature) consisting in voltage levels corresponding to the value of the second bit of the pair, for duration equal to 2 bit intervals.The block diagram of the modulator used on the module is shown in the block diagram. Four 500KHz sine carriers, shifted between them of 90 deg, are applied to modulator. The data (signal I and Q) reach the modulator from the Dibit generator. The instantaneous value of I and Q data bit generates a symbol. Since I and Q can take either 0 or 1 value, maximum 4 possible symbols can be generated (00, 01, 10, and 11). According to the symbol generated one of the four-sine carrier will be selected. The relation between the symbol generated and sine carrier is shown in table.A receiver for the QPSK signal is shown in fig. Synchronous detection is required and hence it is necessary to locally regenerate the carriers. The scheme for carrier regeneration is similar to that employed in BPSK. In that earlier case we squared the incoming the signal, extracted the waveform at twice the carrier frequency by filtering, and recovered the carrier by frequency dividing by two. In the present case, it is required that the incoming signal be raised to the fourth power after which filtering recovers a waveforms at four times the carrier.A receiver for the QPSK signal is shown in fig. Synchronous detection is required and hence it is necessary to locally regenerate the carriers. The scheme for carrier regeneration is similar to that employed in BPSK. In that earlier case we squared the incoming the signal, extracted the waveform at twice the carrier frequency by filtering, and recovered the carrier by frequency dividing by two. In the present case, it is required that the incoming signal be raised to the fourth power after which filtering recovers a waveforms at four times the carrier.

1 2 3 4

1

0

CLOCK

& DATA

GENERATOR

5 6 7 8

SCLOCK

SW1

NRZ-L

CODER

[ADCL-02]

CLK IN

DIBIT

CONVERSION

I BIT C1

Q BIT C2

OFF

ON

MOD

SF1

1 2 3 4

SDATA DATA IN NRZ-L

DATADATA IN

CARRIER

SIN1

SIN2

IN1

IN2

CARRIER

MODULATOR

OUT

GENERATOR SIN3

SIN4

IN3

IN4

DATA

OUTDATA

DECODER

I BIT IN

Q BIT IN

I BIT

Q BIT

ENVELOPE

DETECTOR1

ENVELOPE

DEM1

ADDER

SAMPLER

180

SAMPLING

CLOCK

GENERATO

R

F/4

PLL

VCO

SQUARER

2

SQUARER

1

MOD

IN

CLK IN CLKDETECTOR 2 DEM0

RK CLK2 2

CLOCK RECOVERY

QPSK/DQPSK DEMODULATION

OFF

ON

SF1

1 2 3 4

PHASE SYNC RST [ADCL-03]

BLOCK DIAGRAM FOR QUADRATURE PHASE SHIFT KEYING MODULATION TECHNIQUE.

PROCEDURE:ƒ Refer to Block Diagram & Carry out the following connections and switch

settings.ƒ Connect power supply in proper polarity to the kit ADCL-02/03 & switch it

on.ƒ Select Data pattern of simulated data using switch SW1.ƒ Connect SDATA generated to DATA IN of NRZ-L CODER.ƒ Connect the coded data NRZ-L DATA to the DATA IN of the DIBIT

CONVERSION.

ƒ Connect the SCLOCK to CLK IN of DIBIT CONVERSION.

ƒ Connect the dibit data I bit to control input C1 of CARRIER MODULATOR

ƒ Connect the dibit data Q bit to control input C2 of CARRIER MODULATOR.

ƒ Connect carrier component to input of CARRIER MODULATOR as follows:

ƒ SIN 1 to IN 1

ƒ SIN 2 to IN 2

ƒ SIN 3 to IN 3

ƒ SIN 4 to IN 4

ƒ Connect QPSK modulated signal MOD OUT on ADCL-02 to the MOD INof the QPSK DEMODULATOR on ADCL-03.

ƒ Observe the output of first squarer at SQUARER 1.

ƒ Observe the output of second squarer at SQUARER 2.

ƒ Observe four sampling clocks at the output of SAMPLING CLOCKGENERATOR.

ƒ Observe the output of ADDER 1.

ƒ Observe the output of ADDER 2.

ƒ Observe the recovered data bit I at the output of ENVELOPEDETECTOR 1.

ƒ Observe the recovered data bit Q at the output of ENVELOPE DETECTOR 2.

ƒ Connect I BIT, Q BIT & CLK OUT outputs of QPSK Demodulator to I BIT IN, Q BIT IN & CLK IN posts of Data Decoder respectively.

ƒ Observe the recovered NRZ-L data from I & Q bits at the output of DATADECODER.

ƒ Use RESET switch if delay occurs at data out post and use PHASE SYNCswitch if there is mismatch in the pattern of data at output with respect to the transmitter data.

OBSERVATIONS:ON KIT ADCL-02

ƒ Input NRZ-L Data at DATA INPUT.

ƒ Carrier frequency SIN 1 to SIN 4

ƒ Dibit pair generated data I bit & Q bit at DIBIT CONVERSION.

ON KIT ADCL-03ƒ QPSK modulated signal at MOD OUT.

ƒ Output of first squarer at SQUARER 1.

ƒ Output of second squarer at SQUARER 2.

ƒ Four sampling clocks at the output of SAMPLING CLOCK GENERATOR.

ƒ Two adder outputs at the output of ADDER.

ƒ Recovered data bits (I & Q bits) at the output of ENVELOPEDETECTORS.

ƒ Recovered NRZ-L data from I & Q bits at the output of DATA DECODER.

CONCLUSION :In BPSK we deal individually with each bit of duration Tb. In QPSK we

lump two bits together to form a SYMBOL. The symbol can have any one of fourpossible values corresponding to two-bit sequence 00, 01, 10, and 11. We therefore arrange to make available for transmission four distinct signals. At the receiver each signal represents one symbol and, correspondingly, two bits. When bits are transmitted, as in BPSK, the signal changes occur at the bit rate. When symbols are transmitted the changes occur at the symbol rate which is one-half the bit rate. Thus the symbol time is Ts = 2Tb.