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TYPESThere are 7 types of addressing modes:
Immediate
Absolute Accumulator
Direct
Indirect
Memory mapped
stack
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IMMEDIATE ADDRESSING MODE Operand is mentioned in the instruction word itself
Indicated by ‘#’ symbol
Eg: LD #55h , A Two types:
1. short immediate addressing
2.long immediate addressing
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3 and 4 bit 8 bit 9 bit 16 bit
LD FRAME LD ADDM
LD ADD
AND
ANDM
CMPM
LD
MAC
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ABSOLUTE ADDRESSING Complete address of the operand mentioned in the
instruction itself
2 word length DP, SP, ACC and ARs – not used
3types:
1.dmad
2.pmad
3.PA
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DMAD:
ex: MVKD Data1, *AR3
PMAD:
ex: MVPD COEFF, *AR3
PA:
Ex: PORTR FIFO, *AR5
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ACCUMULATOR ADDRESSING Accumulator content is used as the address
Ex: READA Smem
WRITA Smem Both program and data memory space are involved
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DIRECT ADDRESSING Instruction contains 7 lower order bits of data memory
address
Effective address= base address + offset
15-8 7 0-6
CPL- compiler mode bit
Ex: ADD value1, B
opcode Mode
specifier
dma
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Two types:
1.stack pointer referenced2.data pointer referenced
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MMR ADDRESSING Modifies the MM registers without affecting the data
pointer and stack pointer.
Works for both direct and indirect addressing modesDIRECT MMR ADDRESSING:
It forces the 9 MSB’s of the dma to zero regardless of SP/DP.
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INDIRECT MMR ADDRESSING In the current AR ,7 LSB’s are used for the lower order
address.
AR-> FF25h (MMR addr value) 0025- register is aaccessed
AR changed to 0025h after the access
Ex: LDM MMR, dst
POPM MMR
PUSHM MMR
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STACK ADDRESSING Function of stack pointer
It is a MMR- 16 bit
Filled from highest to lowest address Points to last element in the stack
Ex: PSHD (PUSHD X2)
PSHM
POPM
PUSHM
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INDIRECT ADDRESSIND MODE AR contains the 16 bit address of the operand.
There are 8 16- bit auxillary registers.
AR address can be optionally modified by increment,decrement, offset/index
(read,read) (write,read) (read,write) (write,write)operations can be performed.
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SINGLE OPERAND ADDRESS
MODIFICATIONS *ARx+
*ARx-
*+ARx *-ARx
*ARx-0
*+ARx+0
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SINGLE OPERAND ADDRESSING
OPCODE l=0 MOD ARF
15-8 7 6-3 2-0
Mod defines the type of indirectaddressing.
ARF defines the AR used for
addressing.Depends on CMPT in ST1.
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CMPT=0 Standard mode. ARF always
specifies the AR irrespective of ARP. ARP must always be set to 0 in thismode.
. CMPT=1 compatability mode. If
ARF=0. ARP selects AR, else ARFselect AR and ARF is loaded into ARP
when access is completed
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ARAU & ADDRESS GENERATION
LOGIC
•
Two ARAUs (ARAU0 and ARAU1) operate on thecontents of the ARs. The ARAUs performed signed 16-bit AR arithmetic operations.
Ex: MAR- Modify Auxillary Registers
STM- loaded with an immediate value using the STMinstruction.
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DATA TYPES 16 BIT
32 BIT
32 BIT INSTRUCTIONS: DADD
DSUB
DLD
DST
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OPERAND ACCESS There are 3 buses involved in read and write
operations.
16 bit operand access: C and D buses
32 bit operand access:
C, D and E buses.
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