The Enab le r o f Low-Power Sys tems-on -Ch ip !
Addressing the Energy Efficiency Challenges of
IoT end points FREDERIC RENOUX – SOI CONSORTIUM SHANGHAI – SEPT. 2018
CORPORATE ID #1
Incorporated in 1985
150 highly qualified engineers to enable the design of Energy Efficient SoCs
> 600 Silicon IPs available at 180 nm to 22 nm in multiple foundries
• Power Management • Standard Cell libraries • Memory Compilers • Audio CODECs/ADCs/DACs and Triggers • Oscillators
Serving more than 500 companies worldwide, incl. more than 70 companies in China
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ENERGY-EFFICIENCY, THE NEW METRIC
• Performance is not anymore the only constraint • Power consumption has to be in the equation
Source:IBM,SemiconWest2018
Cloud Already developped
(More’s Moore driven)
Edge Emerging
Multiple techno/standards
Very Edge Future
Source:IMEC,ITF2018
Mops/µW
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Empty space for
now
A WORLD OF OPPORTUNITY, BUT
« There will be trillions of these IoT devices out there »
Jensen Huang, CEO of NVidia
« The speech and voice recognition market is expected to be valued at USD 6.19 Billion in 2017 and is likely to reach USD 18.30 Billion by 2023, at a CAGR of 19.80% between 2017 and 2023.»
Markets and Trends
« One of today’s technology most significant challenges is how to create a SOC that meets the conflicting consumer demand for devices with both high performance and extended battery life »
Samsung Semiconductor business
« …Power management is another feature, which in some cases may be the determining factor for whether a product (MCU) does well or fails because it affects battery life. Some of these MCUs have more than 16 low-power states, but to transition from one power state to the next is complex. »
Andrew Caples, Mentor a Siemens business
« The IoT technology market is expected to grow from USD 176.00 Billion in 2016 to USD 639.74 Billion by
2022, at a CAGR of 25.1% during the forecast period. »
Markets and Trends
Design Technology Disconnect
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THE CHALLENGE
Forbidden zone
?
How to make your IoT SoC the most competitive? Performance Power x area
Time x costs
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Manageable complexity High complexity
Best value
BEST TECHNICS FOR ENERGY EFFICIENCY
3x frequency at same Vdd ~250mV Vdd gain at same speed
Leakage Optimized Power Modes
32 bits DSP
Source: Ivan Miro-Panades, S3S tutorial
2017
Performan
ceBoo
st
+20%
+50%
+200%
PowerR
eductio
n
UltraLowVoltageHighPerf Energyefficiency LowPower
=
2X
10X
BenchmarkvsnoBB
1.5X
>1.5GHz ~1GHz 200MHz <50MHz
Process Variations Mitigation
Leakage limit
IDD
Q
SS FF
Trimmed
Untrimmed
IDD
Q B
BG
EN @
EW
S/R
oom
Source: P. Flatresse, ST, ICICDT17
Le
akag
e
Frequency
RemovedworstcasecornersforP,V,TandAgingduringdesign
EnhancedchipPPA
Noimpactonreliability
Noneedforexternalvoltageregulator
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BODY BIASING CONTRIBUTION
DOLPHIN’S UNIQUE CONTRIBUTION
Lower power IP impact
FinFET
Planar Bulk FD-SOI
DolphinIntegration
Performance Power x area
Time x costs
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Manageable complexity High complexity
Forbidden zone
More advanced process impact
More advanced power
architecture impact
Body Biasing impact
World-first Power Management
IP Platform
To enable cost-effective design
of most
Energy Efficient SoCs
COMPLETE POWER MANAGEMENT IP PLATFORM
• Best energy-efficiency in each SoC power mode by leveraging Power gating, DVFS, AVFS…
• Small silicon area and reduced BoM costs
Key features
• State-of-the-art IP offering
• Standardized IPs for streamlined SoC integra.
• Scalable to any SoC complexity
• Workable with third-party silicon IPs
• Built-in safety features to prevent SoC failures
• Based on silicon proven IP architectures…
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Power Island#1
Power Island#2
IOs Power
Island#3
Voltage Regulators (LDO/DC-DC)
Power
Gating
Power
Gating
Power
Gating
Power
Gating
PMU/ACU
monitor monitor
monitor monitor
Up to 5.5 V input voltage
Down to 0.6 V
SoC
Enablement of advanced SoC power architecture
to bridge the complexity gap
FD-SOI PHASE #1 – since 2016
TO MAKE THE HARD BODY BIASING EASY
Enhanced Power Management IP Platform
+ Body Bias Generators
➙ Ultra low power…
+ Monitors
➙ High accuracy In-Situ Monitors
➙ V/T sensors
+ Fully integrated in Power Management IP platform
➙ Automatic reach of Optimum Energy Point
➙ Regulation loop for process, temperature & aging compensation
➙ Workable with any standard-cell library & memory…
+ Design methodology & support
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Enablement of Adaptive Body Biasing as turnkey solution for
best Energy Efficiency without risks
FD-SOI PHASE #2 – going-on
Power Island#1
Power Island#2
IOs Power
Island#3
Voltage Regulators (LDO/DC-DC)
Power
Gating
Power
Gating
Power
Gating
Power
Gating
PMU/ACU
monitor monitor
monitor monitor
BB gen
BB gen
BB gen
BB gen SoC
Up to 5.5 V input voltage
Down to 0.4 V
BACKBONE TO DESIGN COST-EFFECTIVE EE SOCS
• World best-in-class ENERGY EFFICIENCY Sleep mode below 1 uA at 28/22 nm Up to 95% efficiency in active modes Twice faster mode transition time
• No need for advanced LP or BB expertise for best TTM
Complete power management IP platform to make the hard BB easy
Design guidance with know-how transfer
• Reduced silicon and system COSTS
• Lowered design & fab. RISKS Built-in Adaptive BB control In-rush current under control (even after tape-out) Start-up and mode transition safety Preventing risk of ESD issue during IO wake-up…
$ $
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IOT APPLICATION PROCESSOR SUCCESS STORY DOLPHIN’S CATALOG OF SILICON IPS FOR BEST ENERGY-EFFICIENCY
SUPPORT FROM SOC ARCHITECTURAL EXPERTS
COOPERATIVE DESIGN-IN FOR BEST
PPA WITH FIRST TIME SILICON SUCCESS
SUPPORT FROM DOLPHIN’S SOC INTEGRATION EXPERTS
Optimized Power Regulation network
ü Foundation IPs ü Feature IPs
ü Total solution of Power Management
IPs
The industry’s lowest power IoT application processor, enabling groundbreaking Artificial Intelligence at the edge
ü 200 MOPS at 1 mW
ü Minimum 70 nA standby current
ü Power dissipation: 60 mW
ü Designed in less than 18 months
ü First Time Silicon Success
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GAP8
ENERGY-EFFICIENCY, THE NEW METRIC
Cloud Already developped
(More’s Moore driven)
Edge Emerging
Multiple techno/standards
Very Edge Future
Source:IMEC,ITF2018
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Under copyrights 2018/09/06 Page 12
Frederic Renoux
Executive VP Sales
Mobile: + (33) 772 451 540
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