Advanced methodology for electrical characterization of metal/high-k interfacesRosario Rao, Paolo Lorenzi, and Fernanda Irrera

Citation: Journal of Vacuum Science & Technology B 32, 03D120 (2014); doi: 10.1116/1.4868366 View online: http://dx.doi.org/10.1116/1.4868366 View Table of Contents: http://scitation.aip.org/content/avs/journal/jvstb/32/3?ver=pdfcov Published by the AVS: Science & Technology of Materials, Interfaces, and Processing Articles you may be interested in Electrical characterization of high- k based metal-insulator-semiconductor structures with negative resistanceeffect when using Al 2 O 3 and nanolaminated films deposited on p -Si J. Vac. Sci. Technol. B 29, 01A901 (2011); 10.1116/1.3521383 Fabrication of advanced La-incorporated Hf-silicate gate dielectrics using physical-vapor-deposition-based in situmethod and its effective work function modulation of metal/high- k stacks J. Appl. Phys. 107, 034104 (2010); 10.1063/1.3284952 Observation of band bending of metal/high- k Si capacitor with high energy x-ray photoemission spectroscopyand its application to interface dipole measurement J. Appl. Phys. 104, 104908 (2008); 10.1063/1.3021461 Influence of interface layer composition on the electrical properties of epitaxial Gd 2 O 3 thin films for high- Kapplication Appl. Phys. Lett. 90, 113508 (2007); 10.1063/1.2713142 Fluorine incorporation at Hf O 2 Si O 2 interfaces in high- k metal-oxide-semiconductor gate stacks: Localelectronic structure Appl. Phys. Lett. 90, 112911 (2007); 10.1063/1.2712785

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Advanced methodology for electrical characterization of metal/high-kinterfaces

Rosario Rao,a) Paolo Lorenzi, and Fernanda IrreraDepartment of Information Engineering, Electronics and Telecommunications, “Sapienza”University of Rome, via Eudossiana 18, 00184 Rome, Italy

(Received 1 December 2013; accepted 3 March 2014; published 14 March 2014)

A methodology for the quantitative electrical characterization of defects at metal/high-k interfaces

is proposed. It includes modelling of trapping in the oxide, fit of experiments, and calculation of

the system band diagram after trapping. As a result, the defect concentrations and energy levels are

extracted. The methodology is demonstrated on metal-oxide–semiconductor systems, but its results

can be extended on whatever structure containing an interface between a metal and a high-k

dielectric film. VC 2014 American Vacuum Society. [http://dx.doi.org/10.1116/1.4868366]

I. INTRODUCTION

A few years ago, the International Technology Roadmap

for Semiconductors urged the introduction of high-k dielec-

trics in the gate stack of metal-oxide–semiconductor (MOS)

field effect transistors.1,2 As a result, today most electronic

devices in mass production use high-k dielectrics,3 as well as

all devices designed beyond the Moore’s law (as, for exam-

ple, FinFet for logic applications4,5 or resistive random

access memory6,7)

Also, it has become evident that replacing the dielectric

with no concurrent change of the electrode material (respect

to heavily doped poly-Si) is not feasible, as poly-Si is funda-

mentally incompatible with many high-k dielectrics. The

features of the metal/high-k (M/HK) interface not only

depend, of course, on the type of the dielectric and of the

metal but also on the process parameters of the gate deposi-

tion, as temperature and atmosphere, and also on eventual

postdeposition treatments.

In order to create a sufficient barrier against Schottky

emission at the interface, the dielectric should be contacted

with high workfunction metal electrodes (>4.5 eV).

However, the effective workfunction of a metal in contact

with a high-k dielectric can differ substantially from its vac-

uum value, due to the Fermi level pinning.8–10 In fact, chem-

ical bonding and reactions may imply the degradation of the

interface and the creation of border defects causing also

charge transients and flat band voltage instability.11

Characterization of the M/HK interface is thus crucial for en-

gineering and optimizing the structure of electronic devices

respect to performance and reliability. For this purpose, a

quantity of structural and microscopic investigations is usu-

ally used. Very recently,12 the x-ray reflectivity and the time

of flight secondary ion mass spectroscopy were used to

investigate the properties of M/HK systems before and after

the metal gate deposition (with Ru and RuO2 metal electro-

des and Hf-doped Ta2O5 dielectric films). As a result, they

demonstrated that the gate deposition modified significantly

the interfacial layer parameters. Forming gas anneal of

M-gated stacks caused a reduction of the defect pinning

contribution and an increase of the effective workfunction.

O2 annealing of M-O2 gated stacks caused substantial struc-

tural modification in the dielectric stack with a decrease of

the permittivity and a dipole formation with a reduction of

the workfunction. These modifications impact on the per-

formances and the reliability of electronic devices based on

the metal/high-k technology.

In spite of the relevance of the item, if detailed structural

studies are reported on a wide range of M/HK systems, the

electrical characterization is still lacking. Therefore, a reli-

able tool for systematic and quantitative electrical study of

M/HK interface is required. However, there is a great experi-

mental difficulty in this, due to the fact that capture and

emission of electrons in the metal border occur on extremely

short timescales. Conventional steady-state capacitance or

current techniques require measurement times on a second/

minute timescale, during which transient phenomena related

to electrons may have exhausted. To overcome the problem,

new experimental techniques have been proposed in the last

few years to monitor electrical transients at short

timescales13–25 and, in few cases, they have been used for

qualitative investigation of M/HK systems.13–17

In this paper, we propose a methodology for quantitativeelectrical characterization of M/HK interfaces. The proposed

methodology includes modelling of trapping in the oxide,

measurements of flat band voltage at extremely short times,

fit of experimental data, and calculation of the band diagram

after trapping. Test structures are MOS capacitors because

the parameter to be monitored is the flat-band voltage. This

does not limit the range of validity of the methodology to

MOS devices, since the investigated interface is the M/HK

one and, in general, results can be extended to any other

structure containing that junction. The MOS capacitors fea-

ture p-type substrate. The experiment forces electron injec-

tion from the metal and hole injection from the substrate, as

depicted in Fig. 1. For this reason, the electrical stress will

be performed applying a negative pulse to the metal elec-

trode of the MOS capacitor, pushing the substrate under

accumulation.

The principal novelties introduced in this work with

respect to Refs. 13 and 26 are the analytical study of trapping

at the M/HK interface, which includes the effect of the

trapped charge on the electric field, the extraction of trap

a)Author to whom correspondence should be addressed; electronic mail:

rao@die.uniroma1.it

03D120-1 J. Vac. Sci. Technol. B 32(3), May/Jun 2014 2166-2746/2014/32(3)/03D120/7/$30.00 VC 2014 American Vacuum Society 03D120-1

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concentration and energy position, and the simulation of the

charge propagation in the oxide.

II. METHODOLOGY

The model proposed here assumes elastic processes of

capture in defect sites. In the last years, many analytical mod-

els of trapping based on elastic tunnel have been

developed,26–30 whereas in nanoscaled devices where thermal

and bias effects were demonstrated the inelastic switching ox-

ide trap picture (first developed for SiO2) was invoked.31–33

Today, the question if elastic or inelastic trapping better apply

in the case of high-k dielectrics is still open and under debate.

The fact that quasiuniform energy distributions of traps char-

acterize most high-k dielectrics helps to make feasible the

assumption of elastic trapping, as opposed to the case of few

localized gap states (as in the case of SiO2), which imply

energy misalignment between an reference level of injection

and the trap level. The starting point of the proposed model is

that only a fraction of the total site concentration is involved.

This fraction is discriminated by the energy position of the

level (ET) referred to the energy level of injection (Eref), and

follows a Fermi-like distribution26

�NT ¼NT

1þ exp �b ET x; tð Þ � Eref½ �� � ; (1)

where NT is the total trap concentration, b¼ (KT)�1, K is

the Boltzmann constant, T is the absolute temperature,

ET(x,t) is the energy level of the defect involved in the trap-

ping mechanism at time t and at a distance x from the

injecting interface. ET depends on the location and, being

referred to Eref, it depends also on the electric field in the

high-k film (FHK), in the sense that varying the band bend-

ing different levels are involved in the trapping mechanism.

In practice, FHK is a probe able to scan the energy level of

the involved trap. In the case of electron injection from the

metal interface, the reference level Eref is the workfunction

while, in the case of holes injection from the substrate, the

reference value is the silicon valence band edge. In our pic-

ture, traps are distributed with continuity both in energy

and space. The assumption of elastic trapping implies that

at any instant and bias condition there are involved only

those traps, which lie at the reference energy level and

along the x axis in the portion of dielectric where trapping

takes place. To clarify the concept, in Fig. 2(a), the band

diagram of a monolayer MOS structure in flatband condi-

tion is sketched. In the figure, only two trap sites are

depicted for the sake of clarity, since the sketch with a uni-

form distribution would be unclear: ECT1¼EC-ET1 (circle)

and ECT2¼EC-ET2 (square). In flatband condition and with-

out trapped charge the two sites are not aligned with the

injection reference level Eref (the metal workfunction).

During electrical stress, the band diagram bends due to the

applied voltage and to trapped charge. For example, refer-

ring to Fig. 2(b), when a voltage VG¼V1 is applied, a cer-

tain amount of charge n1 will be trapped and the band

bending induced by V1 and n1 makes the site ET1 to be

aligned to Eref, but not so ET2. In another condition

(VG¼V2 with jV2j> jV1j), a different amount of charge will

be trapped (n2> n1), and the different band bending makes

the trap site ET2 to be aligned to the level Eref, but not so

ET1 [see Fig. 2(c)]. Extending to a uniform distribution of

traps, this reflects in the fact that for different spatial distan-

ces from the injection interface the involved traps lie at dif-

ferent energy distances from the oxide conduction band

edge. Relying on these considerations, in the portion of

dielectric in which trapping takes place the trap level is

aligned with the reference level (ET(x) � Eref¼ 0) so that

Eq. (1) can be simplified into �NT ¼NT/2. For electron trap-

ping, the portion of dielectric involved in the trapping

mechanism is confined between x¼ 0 (M/HK interface) and

x¼ xTe, while for hole trapping it is confined between

x¼ xTh and x¼ tHK, where tHK is the high-k film thickness.

The relationship between the flatband voltage shift (DVFB)

and the trapped charge distribution (nT(x,t)) is

FIG. 1. (Color online) Sketch of a p-type MOS capacitor in accumulation

condition during electrical stress. Electron injection from the metal gate and

hole injection from the substrate are forced.

FIG. 2. (Color online) Band diagram of a MOS structure in three different

conditions: (a) Flatband without trapped charge (ECT1¼EC-ET1 and

ECT2¼EC-ET2 not aligned with the reference injection level Eref); (b) a neg-

ative voltage applied to the gate (VG¼V1, nT¼ n1: the band bending aligns

the site ET1 to Eref); (c) a negative voltage applied to the gate (VG¼V2 with

jV2j> jV1j and nT¼ n2> n1: the band bending aligns the site ET2 to Eref).

03D120-2 Rao, Lorenzi, and Irrera: Advanced methodology for electrical characterization of metal/high-k interfaces 03D120-2

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DVFB tð Þ ¼ q

CHK

�ðxTe

0

x

tHK

nT x; tð Þdx�ðtHK

xTh

x

tHK

nT x; tð Þdx

264

375;

(2)

where CHK is the capacitance per unit area of the high-k

stack, and q is the electron charge. In order to obtain the ana-

lytical solution of Eq. (2), we have to solve the rate equation

describing trapping/detrapping mechanisms34–36

@nT x; tð Þ@t

¼�NT � nT x; tð Þ

snT� nT x; tð Þ

snD; (3)

where snT and snD are, respectively, the characteristic trap-

ping and detrapping time. During electrical stress, electron

detrapping toward the gate is prevented by the negatively bi-

ased gate, while detrapping toward the substrate is negligible

because no electrons reach the substrate interface (as will be

demonstrated in Sec. IV). Hole detrapping toward the sub-

strate is prevented by the electric field. This ensures that

only charge trapping takes place. For this reason, snD tends

to infinite and the detrapping contribution in Eq. (3) can be

neglected.

According to literature,34,35 we define snT¼ s0 exp(x/c),where c is a constant, defined by the barrier height at the

injection interface (W)

c ¼ �h

2ffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi2m� �Wp ; (4)

where �h is the reduced Plank constant and m* is the effective

mass. The time constant of the trap s0 is directly related to

the capture cross section as reported in Ref. 37

s0 ¼ ns�vr0ð Þ�1; (5)

ns and r0 are, respectively, the carrier concentration and the

trap capture cross section, both defined at the injection inter-

face and �� is the average thermal speed. Thus, we can write

the solution of Eq. (3) as

nT x; tð Þ ¼ �NT � 1� e�t=sð Þ: (6)

The term xTe can be regarded as the front of a charge wave

propagating into the oxide.34–36 The position of the wave-

front is a logarithmic function of time

xTe ¼ cln t=s0ð Þ: (7)

Therefore, the solution of Eq. (2) becomes

DVelectronsFB tð Þ ¼ qNT

4e0k� c2ln2 t

s0

� �; (8)

where e0 is the vacuum permittivity and k is the dielectric

constant of the high-k material. Equation (8) is valid only for

capture of electrons injected from the metal. In the case of

holes injected from the substrate, the solution of Eq. (2) is

DVholesFB tð Þ ¼ qNT

4e0k� 2tHKcln

t

s0

� �� c2ln2 t

s0

� �� �: (9)

The modelling procedure consists in three steps. At the end

of the procedure, the quantities NT, ET, xTe, xTh, and s0 will be

got and the electronic defects completely characterized.

For the sake of clarity, a flow-chart describing the proce-

dure is sketched in Fig. 3. Step 1 requires the acquisition of

experimental curves of flat band shift in a wide time range

and the definition of noticeable intervals in it. Step 2 of the

flow-chart is data fitting in those intervals, obtained using

Eqs. (8) and (9) with extraction of some physical parameters.

Step 3 requires solution of the Poisson equation using the

defect parameters extracted at step 2 and leads to the extrac-

tion of the energy levels of traps.

III. PROCESSING OF EXPERIMENTAL DATA

In order to demonstrate the methodology, experimental

data extracted from literature are used.13 It is worth noticing

that the methodology is independent of the particular M/HK

system considered, since the constrain is the measurement

timescale rather than the materials. The data used here were

obtained with a transient capacitance technique in a time

interval from some hundreds of microseconds to tens of

seconds.

For clarity, the cornerstones of the transient capacitance

technique are briefly recalled below. Short negative “stress”

voltage pulses are applied to the gate (VG) of p-type MOS

capacitors. The displacement current detected at the sub-

strate is displayed on an oscilloscope through an amplifier

with gain G. Denoting with RR the pulse ramp rate

(RR¼DV/Dt) and with C the capacitance value, the voltage

value measured on the oscilloscope during the pulse rise

(and fall) ramp is given by: VMEAS¼G�RR�C. Starting from

the values measured during the pulse front and using post

processing algorithm, it is possible to build the C-V curve

and extract the flat band voltage VFB.19 Measurements of the

flat band voltage during the first (extremely short) front of

the pulse are “trap-free” (VFBfresh). The pulse duration is the

FIG. 3. (Color online) Flow-chart of the proposed methodology: the three

steps are described in Sec. III (steps 1 and 2) and Sec. IV (step 3).

03D120-3 Rao, Lorenzi, and Irrera: Advanced methodology for electrical characterization of metal/high-k interfaces 03D120-3

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stress time and can be varied in the experiment. At the end

of the stress pulse, during the second front, the flatband

voltage in trapped condition is measured (VFBtrapped).

Typical curves got during the measurement are drawn in

Fig. 4. The shift of flat band voltage is thus defined as: DVFB

¼VFBtrapped � VFBfresh.

The devices used here to validate the methodology are

TaN/Al2O3/IL/p-Si MOS gate stack featuring 15 nm thick

Al2O3 film and 1 nm thick interface layer (IL).

Capacitors featured equivalent oxide thickness

EOT¼ 7.6 nm, and area of 1.1� 10�3 cm2. The high-k film

was deposited by atomic layer deposition and the TaN gate by

PVD at low temperature. No postdeposition treatment was per-

formed. Substrate doping was 9� 1017 cm�3.

The measured data of DVFB are drawn in Fig. 5 as a func-

tion of the stress time. We expect that at any time the net

charge trapped in the dielectric is given by the sum of two

contributions: a positive charge (holes) and a negative

charge (electrons).

It is worth noticing that during the experiment, the sub-

strate is always biased in accumulation condition and

therefore electrons cannot be injected from the substrate, but

only from the metal. A preliminary consideration is that the

shift is always positive, and therefore, the contribution to

DVFB from electrons always prevails on the contribution

from holes. However, the curve is not monotonic, and there-

fore, the relative role of the two contributions changes with

time. Step 1 in the flow-chart asks for the definition of a

number of time intervals in the experimental curve in which

the trend looks uniform. In the case of the curve in Fig. 5,

three intervals can be identified. The first region lies at short

times (t< t1, 600 ls�4 ms), where the positive shift is

increasing. Therefore, electron trapping prevails and

increases. In this time interval, only the defects located close

to the injecting metal interface play a role. At intermediate

times, between t1 and t2 (4 ms< t< 30 ms), the positive de-

rivative progressively reduces and the curve features a pla-

teau, as a consequence of a progressively lower contribution

from the negative charge. At long times (t> 30 ms), the de-

rivative is negative, and the decreasing shift reflects the fact

that the contribution from hole trapping prevails.

Step 2 of the flow-chart consists on fitting DVFB data in

the three time regions using Eqs. (8) and (9). Quantities s0

and NT are extracted from fits, and xT is calculated using Eq.

(7). In the specific case, it comes out s0< 600 ls for elec-

trons and s0< 30 ms for holes.

A picture of the propagating trapped charge is shown in

Fig. 6(a). Initially, only negative charge injected from the

metal is propagating inward the dielectric: the distance cov-

ered at time t¼ t1 is xT1 (region 1) and the density of traps

inside that region is NT1. The negative trapped charge con-

centration progressively decreases increasing the distance

from the metal interface. At time, t¼ t2 electrons have pene-

trated deeper inside, and the trap concentration in region 2 is

NT2. In region 3, the trap concentration further decreased.

So, after t2, the negative charge contribution to the flatband

shift can be assumed negligible. For this reason, region 3 in

the picture of Fig. 6(a) is not colored. Hole capture is much

slower and only after t2 this contribution becomes meaning-

ful being favored by the position respect to the substrate,

even if the trap concentration NT4 is lower than NT2. At time

t¼ t3 the positive charge injected from the substrate has

been captured within a distance xT3. The calculated trapping

lengths of electrons and holes are drawn in Fig. 6(b) (distan-

ces are calculated starting from the injecting interface). At

t1¼ 4 ms, it is xT1¼ 1.5 nm (NT1¼ 1014 cm�2), and at

t2¼ 30 ms, it is xT2¼ 1.9 nm (NT2¼ 2� 1013 cm�2). At

t3¼ 60 s, the distance covered by trapped holes is 0.5 nm

(NT4¼ 2� 1012 cm�2). As one can see, the slope of the curve

related to electrons is steeper than the one relative to holes,

indicating that electrons are faster than holes. In the semilog

plot of Fig. 6(b), this is represented by the quantity c [see

Eqs. (4)–(7)], which is inversely related to the corresponding

barrier height in the elastic tunnel.

As a final remark, we wish to underline that at times

shorter than t2 (30 ms, in this case), only the M/HK interface

play a role in the experimental curve of Fig. 5. This explains

why it is not possible to employ steady-state techniques to

study the M/HK interface.

FIG. 4. (Color online) Example of typical curves of capacitance vs voltage

of a p-type MOS capacitor in the fresh condition (left) and after trapping

(right) detected with the transient capacitance technique during, respec-

tively, the first (fresh) and the second (trapped) front of the negative stress

pulse applied to the gate. The pulse duration is the stress time and can be

varied in the experiment.

FIG. 5. (Color online) Experimental data of flat band voltage shift (symbols)

as a function of the stress time (Ref. 13). The continuous line is the fit

obtained with the proposed model.

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IV. ENERGY LEVELS EXTRACTION

Step 3 of the modelling procedure (depicted in the flow

chart of Fig. 3 regards the extraction of the energy levels of

traps. The correct electric field needs to be evaluated

accounting for the trapped charge as function of time and

depth. For this purpose, the Poisson equation needs to be

solved in the whole structure using the defect parameters

extracted at step 2.

In region 1 (0� x� xT1) and region 2 (xT1� x� xT2),

electron trapping occurs and the total trap concentrations

are, respectively, NT1 and NT2. In region 3, charge capture

can be neglected. In region 4 (xT3� x� tHK), hole trapping

occurs and the trap concentration is NT4. We can write the

Poisson equations in region i (1,2,.4) as follows:

r � Fi ¼ �qNTi

e; (10)

where Fi and NTi are, respectively, the electric field and the

trap concentration in region i and e¼ e0 k is the dielectric

constant of the high-k film. The boundary conditions at the

edges xT1, xT2, and xT3 imply continuity of the electric dis-

placement field and the electrostatic potential. Solution of

Eq. (10) in the four zones can be written as

F1 xð Þ ¼ �qNT1

ex� xT1ð Þ þ q

NT2

exT2 � xT1ð Þ þ F3

F2 xð Þ ¼ �qNT2

ex� xT2ð Þ þ F3

F3 xð Þ ¼ F3

F4 xð Þ ¼ qNT4

ex� xT3ð Þ þ F3:

8>>>>>>>><>>>>>>>>:

(11)

F3 can be calculated imposing that the calculated voltage

drop must be equal to the applied voltage. The result is

F3 ¼eIL

eILtHK þ ktIL� Vox �

qNT4

2etHK � xT3ð Þ2

�

� qNT2

2ex2

T2 � x2T1

�� eIL

eILtHK þ ktIL� qNT1

2ex2

T1

� ktIL

ktIL þ eILtHK

� qNT4

etHK � xT3ð Þ; (12)

where Vox is the voltage drop across the dielectric stack; eIL

and tIL are, respectively, the dielectric constant and the thick-

ness of IL. We can integrate Eqs. (11) and (12) to calculate

the energy position of the involved traps respect to the high-

k conduction band edge: ECT(x)¼EC(x)-ET(x). Solutions for

the regions 1, 2, and 4 are reported, respectively, in follow-

ing equations:

ECT xð Þ ¼ q2 NT1

2ex2� 2xT1x

�NT2

exT2� xT1ð Þx

� �

� q F3x� vHKð Þ�WM region1ð Þ; (13a)

ECT xð Þ ¼ q2 NT2

2ex2 � 2xT2x

� NT1 � NT2

2ex2

T1

� �

� q F3x� vHKð Þ �WM region 2ð Þ; (13b)

ECT xð Þ ¼ �q2 NT4

2ex� tHKð Þ xþ tHK � 2xT3ð Þ

� �

þ q vHK � F3 x� tHKð Þ½ � þWoff region 3ð Þ;(13c)

where vHK is the electron affinity of the high-k material; WM

is the metal workfunction; Woff is an offset energy defined as

qDVIL-qvSi-EgSi; DVIL is the potential drop across the inter-

face layer; vSi and EgSi are, respectively, the electron affinity

and the bandgap of silicon. The dependence of ECT on time

is included in the terms xT1, xT2, and xT3 [Eq. (7)].

As an example, in Fig. 7 the band diagram at t¼ 60 s is

sketched, with the defect energy level indicated by dashed

line. The distance of the defect level from the conduction

band edge changes moving inward. On the metal side, the

bending due to trapped electrons is well appreciable in the

figure, while on the substrate side the scale hides the bending

due to trapped holes.

A 3D plot obtained combining Eq. (13) with Eqs. (8)

and (9) is reported in Fig. 8 in which the defect energy

level respect to the conduction band edge (ECT) is shown as

a function of time and position. This plot gives a picture of

what happens in the dielectric gap during the trapping time.

At extremely short times, only electrons are trapped nearby

the metal interface. Since elastic tunnel drives the trapping

mechanism, the trap energy level at extremely short time

FIG. 6. (Color online) (a) sketch of trapped charge fronts propagating into the high-k film at three noticeable time instants: electrons are injected from the left

(metal, x¼ 0), holes from the right (substrate); (b) calculated distances covered by electrons and holes. The value of two slopes (ce and ch) are also shown.

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coincides with the metal workfunction at about 3.75 eV

from EC (see Fig. 8). Increasing time, the trapped electrons

propagate into the dielectric inducing a band bending,

which alters the electric field. For this reason, moving to-

ward the substrate, defects with energy levels far from EC

are involved. At time t2, where the electron propagation

length is xT2¼ 1.9 nm, the involved trap lies around the

energy 6 eV below the conduction band edge (the charge

front is represented by the shadowed plane in Fig. 8. At

longer times, holes start to be captured nearby the substrate

interface.

As a final remark, we wish to point out that the energy

loss associated to inelastic tunnel may give rise to the crea-

tion of new traps with consequent electrical degradation of

the material, whereas in all our experiments, no electrical

degradation of the dielectric was observed. In fact, at the end

of experiments and measurements, the trapped charge was

completely released, and no change of conduction or perma-

nent shift/stretching of the C-V curves was observed. This

fact, in conjunction with the realistic hypothesis of a quasiu-

niform distribution of trap levels in the gap, substantially

supports the assumption that elastic tunnel prevails and gives

physical validity to the proposed model.

V. CONCLUSIONS

In conclusion, a methodology for the quantitative charac-

terization of defects at metal/high-k interfaces is proposed. It

relies on a procedure consisting on modeling of charge

trapping, fit of experimental data and solution of the

Poisson’s equation in MOS capacitors. Respect to previous

works, its strength lies in the possibility to: (1) investigate

analytically trapping at the M/HK interface including the

effect of trapped charge on the electric field; (2) extract the

space concentration and energy levels of the defects

involved in trapping during stress experiments; (3) evaluate

the charge propagation into the oxide. The proposed method-

ology is experimentally validated in a very wide time inter-

val using metal/high-k/silicon capacitors, but results are not

limited to MOS structures and can be extended to whatever

structure including a metal/high-k interface. The quality of

data fit is excellent in the whole studied range and allows to

study separately the time evolution of the negative charge

trapped nearby the metal/high-k interface at a microsecond

timescale, as well as that of positive charge trapped nearby

the substrate at longer times.

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FIG. 7. (Color online) Band diagram at t¼ 60 s including the effects of

trapped charge.

FIG. 8. (Color online) Energy level of traps involved in the capture mecha-

nism plotted as a function of time and position in the oxide layer. The propa-

gating front of trapped electrons is outlined.

03D120-6 Rao, Lorenzi, and Irrera: Advanced methodology for electrical characterization of metal/high-k interfaces 03D120-6

J. Vac. Sci. Technol. B, Vol. 32, No. 3, May/Jun 2014

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JVST B - Microelectronics and Nanometer Structures

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