Under the Supervision of Mr. KARRAR HUSSAIN Associate professor Fast Fourier Transform (FFT) is used to convert signal from the time domain to frequency domain. FFT is widely used in digital signal processing, like the analysis, design, and implementation of discrete-time signal processing algorithms and systems. FFT are used to reduce the computational complexity, computational time and hardware requirement. FFT and IFFT is an important part in OFDM system and in many more communication systems. FFT algorithms can be approximately classified as fixed-radix type and split-radix type. Fixed-radix Type Radix-2 DIF FFT Algorithm Radix-4 DIF FFT Algorithm Radix-8 DIF FFT Algorithm Radix-2^2 DIF FFT Algorithm Split-radix Radix-2/4 DIF FFT Algorithm Architectures Advantages Disadvantages Pipeline-based architectures High throughput rate High hardware cost Regularity Memory-based architectures Low hardware cost A loss of the throughput rate FFT processors architecture can be divided into two types. One is pipelined-based architecture and other is memory-based architecture. Pipelined-based architecture is designed for speeding up the digital circuit (high throughput rate) and regularizing the data paths of the design. In pipelined-based FFT, there are series of smaller memories (FIFO) used for stored the incoming data and butterfly units used for data path switching and addition and subtraction between two input data of each stage. Buffer means the memories for storing incoming data from the previous stage to provide the correct data scheduling, and BF is butterfly unit The MDC pipeline architecture adopts the Delay Commutator (DC) approach for data buffering. By using this approach, intermediate data are directly output to the next stage or coefficient multiplier instead of being written back in the MDC architecture. The input sequence has been break into r depend on the radix-r parallel data streams flowing forward with correct ordering for the data elements entering the butterfly unit by proper delays. the first two stages of N-point R2MDC architecture. SDF architecture uses a series-in-serious-out (SISO) shift register to be the delay element and feedback the previous input data to compute the DFT. 8-point radix-2 single path delay feedback architecture (a) operational mode 1 (b) operational mode 2 The butterfly unit in Figure shows two kinds of operation modes. In operation mode 1, PE pushes input data into the last location of shift register and pops the data from the first location to output port. In operation mode 2, the output data of addition part of butterfly unit is directly passed to the next stage and the output data from the subtraction part of butterfly unit is written back to shift register. 16-point radix-2^2 single path delay feedback architecture SDF architecture has less hardware requirement and higher utilization rate. SDF FFT requires less memory space N-1 Its multiplication computation utilization being less than 50 %. Its control unit begin less complex and simpler to design Such implementations are advantageous to low power design especially for application of portable DSP devices Architecture No. of Complex Multipliers No. of Complex Adders Complex Memory Size Multiplicative Complexity R2SDF 2(log4 N 1) 4log4 N N-1 Radix-2 R4SDF log4 N 1 8log4 N 2 N-1 Radix-4 R8SDF log8 N 1 (24 + 2T) log4 N N-1 Radix-8 R 22 SDF log4 N 1 4log4 N N-1 Radix-22 R2MDC 2(log4 N 1) 4log4 N 1.5N-2 Radix-2 R4MDC 3(log4 N 1) 8log4 N 2.5N-4 Radix-4 Hardware requirement comparisons of several pipeline structures. Performance Architecture Utilization rate of Multipliers Utilization rate of Adders Utilization rate of Registers R2SDF 50% 50% 100% R4SDF 75% 25% 100% R8SDF 87.5% 12.5% 100% R22SDF 75% 50% 100% R2MDC 50% 50% 50% R4MDC 25% 25% 25% R 22 MDC 37.5% 50% 50% Hardware utilization rate comparisons of several pipeline structures Comparison of Pipeline Architectures The design consist of two butterfly structure BF2I, BF2II, shift registers, complex multipliers, ROM, and control unit Radix-2^2 single path delay feedback architecture for N=1024 1 1 2 1BF I BF I( 2 )1 2 3 3 3 3 3BF II3( , , ) ( ) ( 1) ( ) ( ) ( ) ( 1) ( )2 4 4k k k kN N NH k k n x n x n j x n x n+ ( (= + + + + + + ( ( Based on this algorithm new efficient pipeline R2^2 SDF FFT architecture is design for N=1024.