An investigation into the use of intracellc.c.d.s for analogue and digital

signal processing

N.E. Evans, H.S. Gamble and S.H. Raza

Indexing terms: Charge coupled devices, Signal processing

Abstract: An exploratory electronically programmable transversal filter suitable for analogue signal pro-cessing has been realised and successfully operated. The basic element of the system is an eight sampleparallel-operated intracell charge-coupled device. Results obtained in optimising the drive parameters of pulseamplitude, width and time arc presented and discussed in relation to device physics and operation. Auto-correlations of unipolar analogue and digital signals are presented. These devices are ideally suitable forincorporation in a system using digital storage of the weighting information. An advantage of introcell c.c.d.swith integrated on-chip control logic would be the ease with which such devices could be interconnectedto provide any desired signal-processing capability. This would enable a flexible modular approach to beadopted when designing complex signal processors.

1 Introduction

A transveral filter may be regarded as a system in whichthe output is obtained by summing weighted samples ofthe input signal. In the system realisation shown in Fig. 1,a tapped delay line is used in conjunction with a weightingand summation network to give the filter output

The use of serial c.c.d.s to achieve fixed digital weighting1

(i.e. + 1 and — 1) is well known, as is the principle of ef-fecting fixed analogue weights by way of the split electrodetechnique.2 In many signal processing applications, how-ever, variable analogue weighting is a basic system require-ment. Conventionally this is achieved using a completelydigital system. Recently a fully analogue approach hasbeen followed by several workers employing tapped serialcharge-coupled devices. MacLennan et al. have demonstatedthe application of off-chip variable-conductance weightingto each c.c.d. tap output, followed by summation.1 Hybrid-analogue correlators comprising of two c.c.d. shift registerswith off-chip multipliers have also been developed,3 and

Vk k

Fig. 1 Transversal filter

Paper T262 S, first received 24th May and in revised form 15thSeptember 1978The authors are with the Department of Electrical & ElectronicEngineering, Queen's University of Belfast, Belfast BT7 INN,Northern Ireland

Mavor et al. have demonstrated the feasibility of obtainingon-chip multiplication using m.cs.t.s.4

This paper reports on a digital/analogue system inves-tigated as a possible alternative to the purely analoguec.c.d. correlator. A parallel architecture charge-couplingstructure with digital processing of the analogue-signalsamples is used to perform the transversal filtering function,thereby eliminating the need for analogue multipliers.

2 Intracell c.c.d.

2.1 Structure

The intracell c.c.d. was first suggested by Tiemann et al.in 1974.5 The signal-processing properties of the deviceare based upon its ability to store charge packets rep-resenting analogue-signal samples in fixed locations or'cells'. The controlled movement of a charge packet withina cell permits the functions of signal sampling, delayingand weighting to be implemented. The structure inves-tigated is shown schematically in Fig. 2.

The c.c.d. consists of separate cells that are driven bycommon clock lines but are otherwise independent. Eachcell consists of two independently controlled transfergates, two gates common to all cells, and a common inputdiffusion. The signal is applied to the input diffusion,and an analogue sample of it is selectively stored in a cellby pulsing on the appropriate input-transfer gate. Oncecharge has entered a specific cell, it remains in that cell

nthcell

'9(n-0

t.g (n-1)

input diode '

-n 11 1 ig-(n-1) ]

t g tg '(n-1)

Fig. 2 Intracell charge coupling structure

i.g. = input gatet.g. = transfer gate

SOLID-STATE AND ELECTRON DEVICES, NOVEMBER 1978, Vol. 2, No. 6 215

0308-6968/78/060215 + 09 $ 01-50/0

for the Jotal delay of the register, when it is replaced bya new sample. The charge stored in a cell can be nonde-structively read by transferring the packet from under oneof the common gates to under the other. A sample is onlyread if the weighting transfer gate is pulsed open, allowingthe charge transfer to proceed. The weighting transfer gatetherefore gives the capability of reading, or not reading,a sample, i.e. + 1 and 0 weighting.

Variable but quantised tap weights are possible byoperating several devices in parallel and combining theiroutputs in binary weighted levels. In addition, becauseonly digital control signals and not analogue charge samplesare passed from one chip to another, it is relatively easyto connect the devices in series. As the charge alwaysmoves between the same two electrodes, transfer lossesare not cumulative, and therefore the number of samples(i.e. the size of the system) is not limited by transfer losses.

2.2 Fabrication

Eight-sample intracell c.c.d. structures were fabricated onnominally 1 x 10ls cm"3 TV-type (111) silicon substrates.A 1 jum thick wet oxide was used to define the cells andmask against the boron diffusion. Oxidised boron-nitridewafers were used for the diffusion source and the depo-sition was done at 1000° C for 15 min.

The oxide in the device wells was grown in a dry oxygenplus t.c.e. atmosphere at 1150°C and is 1500 A thick.Since a single-level aluminium structure was used, thecommon 02 gates were taken out to a diffused rail toallow metal access to the weighting transfer electrodes.Submicron electrode spacing was obtained using theshadow-etch technique developed by Browne et al.6 Inthese devices all the gates have the same dimensions:30/^mx 150 Mm.

2.3 Operation

The basic intracell c.c.d. operation is illustrated in Figs.3 and 4, that show the surface potential changes anddrive waveforms used in a typical charge input/weightingsequence. For a read operation, the charge packets inall the individual cells are initially held under the common02 electrode that is at —Vg/2. Common electrode 0!is set at — Vg and then isolated from its driver circuitryby switching off a series-connected m.o.s. transistor.The samples that are to be weighted 1 are allowed totransfer under the 0X electrode by pulsing the relevanttransfer gates. (Pulse 2 in the transfer gate triple-pulsesequence of Fig. 4b). The influx of charge under thefloating 0! electrode changes its voltage in proportion tothe total charge transferred. As the 0j electrode is common,the voltage change is proportional to the sum of all thesamples weighted 1. Therefore, signal summation, asrequired by transversal filtering theory, is carried outautomatically. Assuming that the silicon depletion capa-citance of each individual cell Cs remains invariant withcharge magnitude, and all cells are identical, then theoutput voltage VE from the c.c.d. is given by

VE =

where Qk is the charge contained in the fcth cell, Co theunicellular-oxide capacitance, Q the device external-loadcapacitance, and 5fe is the transfer vector. For a particular

cell, 6 = 1 if a charge sample is weighted 1 and 6 = 0 ifa weight of 0 is used. Charge samples weighted 0 remainunder the 02 electrode during the 0! float time. Thisnecessitates the use of the d.c. - offset clocking system,and the intracell c.c.d. effectively operates with a maximumcharge-handling capability (Q max) of half a full well.At a time corresponding to possible readout, a storagelocation is provided under 02 for charge packets weighted0, while a deeper potential well is created beneath 0i topromote the transfer of those packets weighted 1. Whenthe readout sequence is complete the m.cs.f.e.t. switch

i d . i.g. <p] t.g.O

111

substratea

surfacepotential

M vzrt

e

Fig. 3 Plots of surface potential in an Intracell c.c.d, during acharge input and readout sequence

a Intracell c.c.d.b Input gate pulsed openc 0, equilibrates with input diode

Input gate closesCharge packet isolated

d Tranfer gate opensCharge packet transferred to 02 location

e Tranfer gate closes/ 0, and 02 voltages adjusted for possible readout but charge

packet weighted '0'g Charge packet weighted ' 1 '

216 SOLID-STATE AND ELECTRON DEVICES, NOVEMBER 1978, Vol. 2, No. 6

is turned on again, returning control of 0i to its externaldriver stage. The charges previously weighted 0 are thentransferred under 0 t , but not sensed (pulse 3 in Fig. 4b).This ensures that all the charge samples are in their 0t

storage sites at the end of each read sequence, irrespectiveof whether 1 or 0 weighting has been effected. The voltageon the 0i electrode is returned to —Vg/2. If desired, anypacket of charge may now be updated by pulsing theinput gate of the cell concerned. The charge under 0!then adjusts to a new value which is proportional to theamplitude of the input signal. Alternatively, the originalpacket may be retained for further processing and trans-ferred back to beneath 02, (pulse 1 in Fig. 4b) along withall the other packets contained in their respective 0ilocations, ready for the next reading operation. Anysignal delay imposed by the device is dependent on the

-0V-V

1 2 3 T 3 tg

-0V

n

1•ov

OV

--V,bias

Fig. 4 Intracell c.c.d. drive waveforms

a Input gateb Tranfer gatec 0,d0 2e 0, switch control

samplepulse

generator

travelling-oneshift-register

' " I ;

AND

i.g.1

;T

weightingshift-register

L.

AND

digitalweights

Vv

OR

readpulse

generator

|ig.8

t.g1

ltg.8

analogeinput Vx

input inputgates diode

intracellc.c.d.

transfergates

set/resetpulse

generator

2-0 clockgenerator

externally selectable time interval between reading chargein and subsequently weighting it 1, and is limited by thedistortion introduced by dark current.

2.4 Drive requirements

The circuitry used to operate the intracell c.c.d. is shownschematically in Fig. 5. To provide the input address forupdating the information contained in the c.c.d., a pulseis moved sequentially along the 'travelling-one' shift register.A short sample pulse is used to enable the AND gates,thereby ensuring correct timing relative to the 0i and 02

clocks.The digital weighting code is circulated continuously

by the other shift register, effectively moving the weightspast the stored analogue samples. Again AND gates areused to ensure correct timing of the read pulse while theOR gates are used to set and reset the samples under theappropriate electrode.

In this investigation all the circuitry in Fig. 5 was im-plemented external to the chip, but the shift registers andlogic contained within the dashed lines could easily beintegrated on-chip in either m.o.s. or c.c.d. technology.

2.5 Extraction of output information

The change in voltage at the floating 4>x electrode as aresult of reading out charge samples is small, in the regionof IV for eight packets of maximum size, and is super-imposed on the comparatively large 0i clock waveform.Also present are feedthrough pulses from the gate of them.o.s.f.e.t. switch connected to 0i . These pulses may beup to a few volts in amplitude, depending upon the internalcapacitances of the m.o.s.f.e.t. used, and represent thezero level for any subsequent change in voltage broughtabout by the influx of signal charge. The situation issummarised in Fig. 6a. Consequently, before any ampli-fication of the output takes place, the composite 0! signalis firstly transformed to a low impedance by a sourcefollower; it then undergoes d.c. restoration so that thepulses containing the desired data are positive-going relativeto earth (Fig. 6b). Extraction of the output informationis accomplished by sampling followed by a diode pick-offcircuit to eliminate almost all of the 'float-pulse' feed-through, and d.c. restoration of the data pulses to earth.

2.6 Substrate bias

Maintaining depletion conditions at the active silicon sur-face in a c.c.d. is necessary to ensure that pumping ofsignal charge7 to the substrate does not occur. In the testIntracell device, the charge-loss mechanism was investigated

flOOt 9control J -<

JL ah

?

Joy

1

\cwcns

'g-*bw breakthrough pulseb: from gate of & mosfet

switch n

outputcontrol 5V

Fig. 5 Drive conditions for the Intracell c.c.d.

Fig. 6 Extraction of output information

a <t>i electrode waveformb Output circuitry

SOLID-STATE AND ELECTRON DEVICES, NOVEMBER 1978, Vol. 2, No. 6 217

by monitoring the c.c.d. substrate current. This was foundto have two components:

(a) the reverse-bias leakage current /[ of the 02 diffusedrail

(b) Ip due to minority signal charge being pumped intothe substrate.A set of results obtained using bias voltages in the range0 to 5-5 V are presented in Fig. 7. Removing the positive-going pulse fed to the input diode resulted in no chargebeing stored in the c.c.d., so that only the leakage current/; was measured [plot (a)]. When the first charge packet(Qmax m size) was introduced to the device, the substratecurrent changed sign initially, reached a maximum at abias voltage of 2-2 V, and attained the value exhibitedby the junction leakage mechanism at 4-95 V [plot (b)].By extending the length of the input diode pulse, all thec.c.d. cells were made to store charge, and the currentsmeasured for 2, 4, and 8 packets are shown in plots (c),(d) and (e), respectively. The characteristic shape obtainedfor the single packet is repeated in each case, with thesubstrate current peaking at a bias voltage of 2-2 V; themeasured flat-band voltage Vfb for these devices was— 2-8V. For \VR\<\Vfb\ the silicon surface beneath thecontrol gates in the 'off state is accumulated, but theamount of charge stored beneath the <pi electrode at read-in increases as VR increases positively from zero. Becausethe surface state density is invariant, approximately thesame amount of charge is pumped into the substrate oneach transfer, but the average current pumped during thesixteen transfer cycle will be dependent on the size of theoriginal charge packet. For IKRl>|Kfb| the magnitudeof the stored charge still increases, but the silicon surfaceremains depleted when the control gates are turned 'off.The pump current therefore decreases until it is finallyeliminated at VR =4-95V, and only the leakage currentis evident.

2.7 Con trol pulses

With 0, and 02 clock swings of —9V to —18V, controlpulse amplitudes in the — 9V region are to be expectedbecause the creation of potential barriers or wells duringsignal input/readout must be avoided; this action ensures

that the undesirable effects of charge blocking and part-itioning are minimised. Both mechanisms are illustratedin the transfer-gate characteristic of Fig. 8. This showsplots of output voltage versus transfer-gate amplitudeobtained for the eight-cell operation of a test c.c.d. Twoinput diode d.c. voltages corresponding to charge packetsof Qmax and 0-75 Qmax are used. The graphs indicatean output maximum at Vtg — —10-5 V in both instances.Employing more positive pulses produces potential barriersunder the transfer gates that prevent full communicationbetween the 0j and 02 electrodes.

Thermal generation causes charge to build up under the02 electrode, to a level such that when the electrode isswitched 'off to —9 V the silicon surface potential is equalto that of the barrier. When pulsed to —18 V the 02 poten-tial well accepts minority carriers from beneath electrode0!, and transfers back the same amount of charge to 0!when 02 switches 'off again. The amount of charge trans-ferred from beneath 0i to 02 is, however, limited by anypotential barrier underneath the transfer gate, as thermallygenerated carriers under the 0i electrode are removedeach cycle.

The use of transfer pulses more negative than —10-5 Vcause the creation of deep potential wells in the siliconsurface that are capable of holding some signal chargeduring transfer. This charge is then distributed betweenthe wells under 0! and 02 when the gate is turned 'off.Thus during readout there is a net reduction in the amountof charge presented to the floating 0i electrode. An opti-mum value of Vtg therefore exists. Because the transferof charge from one clock electrode to the other is alwaysunder the influence of a fixed potential difference, themeasurement of this optimum value at —10-5 V (1-5Vmore negative than the clock electrode 'off voltage) isnot unexpected, because charge movement is enhancedby the resultant potential gradient at the silicon surface.

The minimum width of the tranfer-gate pulse is deter-mined by the time required to transfer charge from a finitesource of minority carriers. Because the gates in the deviceare 30/xm wide, the fringing and thermal fields are bothweak,8'9 with the result that the transfer efficiency isprobably not greater than 99% in the 2jus allowed forcharge movement in normal operation. The overall per-formance of the c.c.d. is not severely limited by suchincomplete transfer, as any charge left behind on one cycleis recombined with the transferred charge prior to thenext readout cycle. Extending the width of the transfer-gate pulses beyond 2]us in an effort to achieve the bestpossible efficiency would, however, impose a restrictionon the maximum operating speed of the device. The same

2 085a o-6o-ci 0 A

u

0 2

0-8 -12 -16

transfer gate voltage, Vtg

Fig. 7 Effect of substrate bias on device performance Fig. 8 Eight-cell transfer gate characterisitc

218 SOLID-STATE AND ELECTRON DEVICES, NOVEMBER 1978, Vol. 2, No. 6

pulse width is used at the input gate to allow charge tospill back into the input diode when a cell is being upgradedwith a smaller signal.

3 Signal-processing capability

3.1 Input/output characteristics

The ideal building block in many analogue signal-processingapplications has a linear-transfer function, i.e. the outputis either an amplified or attenuated replica of the input.In c.c.d. transversal filtering it is also desirable to makethe tap outputs linear with input signal amplitude. In theintracell device the use of what is effectively the diodecutoff input method and a voltage-sensing output stagegives the typical eight-cell transfer characteristic shown inFig. 9; this exhibits a useful almost linear region over therange Vid = —4-5 V to —2-5 V. For very large packets ofcharge (Vid more positive than —2-5 V) a saturation effectis evident, thought to be due primarily to large changesin the 0i (readout) electrode-depletion capacitance. Chargeflooding of this test device occurs after Vid = —0-85 V,approaching the silicon surface potential induced by thesubstrate bias voltage of 4-95 V. Making the input diodemore negative than —4-5 V results in an exponential de-crease to the zero output level. The overall linearity andsummation properties of the device are demonstratedby the examples of analogue delay and square-wave corre-lation shown in Figs. 10a and b respectively. The delayof the sawtooth signal was obtained by circulating a single1 in the weighting shift-register to effect the readout ofa specific cell 400/us after that cell had stored charge underthe influence of the sample pulse. Note that the inputwaveform sweeps all of the 2 V linear region of the c.c.d.transfer characteristic.

i 0 r

0 8

0 6

•5 0a

02

0 -2 - 4 -6

input diode voltage V. (relative to substrate)

Fig. 9 Eight-cell input/output characteristic

0,, 02 amplitude - 9 18VVjg amplitude Q 9 VVtg amplitude 0 10 Vvsub + 4-95 V

Fig. 106 shows the result of correlating a square wavewith the eight filter weights, all of which were set at 1 andcirculated continuously. The amplitude of the input wave-form, and its bias level relative to the c.c.d. substrate,were set such that the input diode was switched between- 7 V and - 3 V . With all the cells empty (Vid = - 7 V )there is no output: when the input waveform switches to— 3V an equal amount of charge is placed in each cell inturn by the circulating sample pulse, and the c.c.d. out-put voltage increases linearly for the next eight clockperiods. It then remains constant for four clock periodsbefore the input diode is switched back to — 7 V, andeach cell is emptied in sequence. Careful inspection of boththese observed outputs indicates small differences betweenthe output contributions from each cell. This effect is aresult of slight variations in

(a) the dimensions of the individual starage locations(b) the electrode threshold voltages along the register.

Fig. 10c.c.d.

Simple signal-processing applications of the Intracell

a Analogue delayTop trace: sawtooth input signalBottom trace: c.c.d. output after sampling and amplificationHorizontal scale: 0-5 ms/divisionVertical scale: 2V/division

b Square-wave correlationHorizontal scale: 0-5 ms/divisionVertical scale: lV/division

SOLID-STATE AND ELECTRON DEVICES, NOVEMBER 1978, Vol. 2, No. 6 219

Such variations act as extra noise sources when comparedto serial c.c.d. signal processing systems.

3.2 In tracell digital correla tor

If a repetitive digital sequence is applied to the input diodeof an Intracell c.c.d., and the input gates are addressedat a rate sufficient to prevent distortion by thermal gen-eration mechanisms, then the input word is effectivelystored in a fixed location, and another 8-bit weightingsequence can be moved along the device to give the cor-relation between the two signals.

This is demonstrated in Fig. 11 where the test devicewas used to store the sequence '0 1 1 10 0 10 ' (shownin the middle trace) in cells 1 to 8. The input diode wasswitched between — 2-5 V and —7-5V relative to thesubstrate, giving charge packets of about 0-75 Qmax j n

the four cells corresponding to a 1, and no charge in theothers. The upper trace in Fig. 11 shows the digital weight-ing word, 8-bits long, separated by blocks of eight 'zeros':this was monitored at the input to the t.t.l. shift registerfeeding the transfer-gate timing circuitry, and thereforelags the weighting pulse sequence applied to cell 1 of thec.c.d. by one clock period (100 jus). In this case the weightsare selected to give an impulse response (the output withcharge stored in cell 1 only) identical to the stored digitalword reversed in time. The system therefore representsa matched filter for the input word, and the responseshown (in the lower trace of Fig. Ma) is the latter's auto-correlation function. As required by the theory of matchedfiltering, the peak output occurs at a time when the inputand weighting signals are coincident, i.e. at zero time shift.The output levels obtained during the correlation sequencemay be compared with those shown in Table 1 where vrepresents the change in system output voltage obtainedby reading a single cell containing charge.

Stored sequenceWeighting sequencec.c.d. output

Table 1 : Output levels

0 1 1 1 0 0 1 0,. . 0 , 0 1 0 0 1 1 1 0 , 0 0 0 0 0 0 0 0 , 0 1 .. . -, - - v v v v 2v 4v 2vv v v v • • -, - -

Fig. 11 Digital matched filtering

Top trace: transfer-gate weighting sequenceMiddle trace: c.c.d. inputBottom trace: c.c.d. output after sampling and amplificationHorizontal scale: 0-5 ms/divisionVertical scale: 5V/division

3.3 Implementation of programmable, multilevel impulseresponse

Variable but quantised weighting of stored charge samplesmay be effected by operating n intracell devices in parallel,and combining their outputs in a binary fashion to give2" weighting levels.10 As many devices as required to givethe desired resolution may be driven in parallel, and thenumber of charge samples accommodated can be increasedby connecting banks of the c.c.d.s in series: such systemexpansion is simplified by the fact that the charge packetsremain in fixed locations, and only the digital controlsignals need to be passed from chip to chip.

To demonstrate the practicality of multilevel weighting,four 8-sample devices were selected from the same parentwafer and driven as indicated in the block diagram ofFig. 12. A single circuit is used to drive all the 02 clocklines, and a similar one is used to drive the 0! electrodes,that are fed via individual m.o.s.t. switches. The input-gate pulse train is also common to all four c.c.d .s ensuringthat with the input diodes connected to a common signalsource, the devices store identical charge packets in theircorresponding cells. The four transfer-gate waveformsrequired are generated separately, with a bank of eightswitches used to select the readout codes for each c.c.d.

The output information is extracted from the 0i clockin the manner described in Section 2.5. After the final

input

sampling anddc. restoration

id. c.c.d

*2A.3

idc.c.d.3

\

analogue input

R=47kn

summingamplifier

sampledsummationoutput

amplifiers

Fig. 12 Sixteen-level weighting using four Intracell c.c.d.s

Fig. 13 Output waveform for a sixteen-level programmablesystem

Horizontal scale: 0-2 ms/divisionVertical scale: 0-2 V/division

220 SOLID-STATE AND ELECTRON DEVICES, NOVEMBER 1978, Vol. 2, No. 6

d.c. restoration stage, however, each of the four outputs istaken to an inverting amplifier provided with a variablegain control. This enables amplification of the outputpulses from the c.c.d.s to be effected in the ratio, 8, 4, 2and 1. Another inverting amplifier stage is then used tosum the resultant binary weighted responses, giving thefinal output. Any variation between the different devicescan be taken into account by optimising the substratebias on each, and if necessary, adjusting the relevent am-plifier gains to give the correct weighting levels. The abilityof such a system to provide a programmable 16-levelimpulse response is demonstrated by the summing amplifieroutput shown in Fig. 13. In this case the four sets ofdigital weights given in Table 2 were circulated continu-ously and a short pulse was applied to the system input togive a charge level of 0-75 Qmax in one specific cell in eachc.c.d., with all other cells remaining empty. For com-parison purposes the theoretical decimal sum is also givenin Table 2.

Table 2: Four sets of digital weights

X8X4X2X1

sum

0000

0

0000

0

0000

0

0000

0

0000

0

0000

0

1111

15,

1001

9

0000

0

0011

3

0110

R

1001

9

1100

12,

1111

15,

0000

0

0000

0

0000

0

0000

0

0000

0

0000

0

3.4 Unipolar analogue correlation

Having demonstrated the programmable nature of theIntracell correlator impulse response, the system was usedto perform the autocorrelation of a ramp signal: a common2 V p-p sawtooth waveform was connected to the fourinput diodes, biased such that the positive going ramp-upswept the linear part of the input/output characteristicappropriate to the devices used. By varying the phase ofthe 800 jus ramp relative to the sample pulses charge packetscorresponding to relative signal levels of 1,3, 5, 7, 9, 11,13 and 15 were stored in cells 1 to 8 of the c.c.d.s. Theoverall system impulse response was switched to give thetime-inverse of this signal, i.e. a negative-going sampledramp sweeping from 15 levels to 1 level relative to thezero-charge condition was obtained upon introducing asingle charge packet into each of the four devices. The out-put from the correlator (that is, in effect, a filter matchedto the ramp signal) is shown in Fig. 14. A comparisonbetween the observed waveform, normalised by its peakvalue, and the theoretical output is given in Fig. 15a. Bysumming the moduli of the differences between the practi-cal and ideal outputs at individual sample points, andexpressing their mean value as a percentage of the theo-retical output signal mean, an error term Se can be defined:in this instance Se was calculated as 6-1 %.

For the case of a ramp input signal corrupted by noise,the response is as shown in Fig. 14b: note that there isstill a definite peak corresponding to the correlation point.

The result of another unipolar correlation is shown inFig. 16. Here, samples representing one cycle of a fullwaverectified sinusoid were stored in cells 1 to 8 of the fourdevices, with the input phasing adjusted for symmetricalsampling, i.e. assuming the pulse has a peak value of unity,then the stored samples in cells 1 to 8 of each c.c.d. ideallyrepresent the normalised amplitudes given in Table 3. Theweights in this case cannot all be set to the correct valuesrequired for autocorrelation due to the limitations imposed

by quantisation. With the available weighting range splitinto its sixteen levels from 0 to 15, however, the normal-ised values used are shown for comparison with the idealcase in Table 3. Using the full 15 levels for the maximumsample amplitudes, the remaining three quantised weightsin the symmetrical sequence are all within 4-5 % of theirnominal values. Taking into account these inaccuracies inthe weighting function, the theoretical and observedresponses for this particular 'autocorrelation1 are shown inFig. 15b, and calculating Se gave a value of 3-2 %.

3.5 Discussion

The performance of the four-chip system can be assessedby comparing the observed and theoretical outputs shownin Fig. 15.

Some deviation from the ideal case is expected, due to:(a) Inaccuracies in setting-up the binary weighting

amplifier gains.(fc) Mismatch in the drive characteristics of individual

c.c.d.s. Although a good compromise can be achieved by

Fig. 14 Autocorrelation of a ramp signal using a four-chip Intra-cell c.c.d. system

a Top trace: input waveformBottom trace: sampled data autocorrelation function output

b Response of the matched filter to a noisy input signalHorizontal scale: 0-5 ms/divisionVertical scale: 2 V/division

SOLID-STATE AND ELECTRON DEVICES, NOVEMBER 1978, Vol. 2, No. 6 221

setting the substrate bias on each device separately, identi-cal outputs are unlikely to be obtained from all fourc.c.d.s over the same input voltage ranges.

(c) Nonlinearity of the c.c.d. input/output characteristic.This is probably the most dominant factor affecting theanalogue operation of a specific Intracell device. For thecases discussed in the previous section the ramp input isespecially affected, since the first sample, corresponding toone storage level, is distorted by the exponential 'tail' ofthe characteristic.

(d) Cross modulation between signal samples, producedby the variations in depletion capacitance when potentialwells are filled to different charge levels.

Table 3: Normalised amplitudes

Cell number 1 8

sample numberb

Fig. 15 Comparison of theoretical and measured Intracell systemresponsesa The autocorrelation of a rampb The autocorrelation of a unipolar sinusoidal pulse-o— o— Theoretical response- o . . o Intracell system output

Fig. 16 Autocorrelation of unipolar sinusoidal pulse

Top trace: system inputBottom trace: sampled-data outputHorizontal scale: 0-5 ms/divisionVertical scale: 2 V/division

222

Normalised 0-342 0-643 0-866 0-985 0-985 0-866 0-643 0-342sampleamplitudes

Number of 5 10 13 15 15 13 10 5levels inweightingfunction

Normalised 0-328 0-657 0-854 0-985 0-985 0-854 0-657 0-328weightingfunction

(e) Feedthrough of the transfer-gate drive waveforms tothe floating 0i sense electrode.This proved to be a problem in the initial testing of theIntracell devices, and although reduced by the use ofscreened interconnections and isolation of the 0! circuitry,is always present to some small extent. Such residualfeedthrough appears to be due to a combination of onchipinterelectrode coupling and the interpin capacitance of theceramic packages used. As the transfer-gate readout codesare continuously moving (and may be changing fast in anadaptive system, for example), the effect is that of a semi-incoherent noise source which is difficult to remove. Theuse of a shielding d.c. gate placed between the 0! and trans-fer electrodes would, however, be beneficial to deviceperformance.

if) Variation in the output voltages obtained fromdifferent cells on the same device when using an invariantinput signal, as discussed in Section 3.1.

4 Conclusion

An electronically programmable alternative to the serialc.c.d. transversal filter has been described. A multichipsystem employing quantised weights has been demon-strated for analogue applications.

In terms of operating frequency the Intracell c.c.d.sdiscussed in this paper are slow. For effective charge trans-fer, the upper limit is in the region of 400 kHz. This is duemainly to the wide (30/urn) gates employed, the inter-electrode gaps, and the low mobility of holes. Devicesfabricated on P-type substrates with overlapping 10/urnelectrodes should result in a useful increase in operationalspeed.

The need for the weighting function to be quantisedprevents the direct correlation of one analogue signalby another unless an analogue to digital converter is usedon one of the signals. In many practical cases, however,correlation is not required between two incoming signals.Often one filter input is in the form of a stored referenceor 'template' and the other is derived from an externalsource. In such instances digital storage of the weightingfunction is convenient, and the intracell c.c.d. could beused with advantage in performing the necessary processingoperation, possibly under the control of a microcomputer.

Although many eight-sample devices could be combinedin series and parallel to increase the processing capability ofa system, it is obviously desirable to use devices with agreater number of sample cells.

The number of samples used in the simple Intracellstructures investigated was limited by the number of inter-connections required. Because the operation of an intracelldevice is controlled mainly by two digital shift registers

SOLID-STATE AND ELECTRON DEVICES, NOVEMBER 1978, Vol. 2, No. 6

and simple AND/OR logic gates, it is feasible to implementthese functions on the c.c.d. chip, either with standardm.o.s. techniques or c.c.d. logic structures.11 This wouldnot only reduce the number of connections per device(regardless of the number of sample cells) but wouldgive the added bonus that the output errors due to vari-ations in individual cell characteristics tend to cancel outas their number increases.12 To maintain a satisfactory out-put signal/noise ratio for a single charge packet, however,the maximum number of cells is limited by the increasingcapacitance of the readout.electrode.

Intracell devices with the shift registers and logic circuitsintegrated on chip could be driven in series or parallel withcommon external clocks. These would consist of the 2-phase intracell clock, the transfer control pulses and, say,

, a 2- phase clock for the shift registers. If digital storage of\the weighting function is used then the necessary inputsignal to the weighting shift register is readily available.Integration of dual intracell c.c.d.s using a common travell-ingN T input shift register is envisaged thereby enablingsixteen levels of weighting to be achieved using two chips.It is also feasible to integrate on-chip output-signal recoverycircuitry, including a gain stage,13 thereby requiring onlyone external summing amplifier to provide the requiredoutput from this type of digitally controlled analogueprocessor.

Because only digital control and weighting signals needto be passed from chip to chip, expansion of such a systemis relatively easy. Hence, given a basic set of drive clocks,these dual intracell c.c.d. modules could be interconnectedin series and/or parallel to provide any desired level ofprocessing complexity. The price paid for increased capa-bility would therefore be only the number of intracellmodules required.

6 References

1 MACLENNAN, D.J., MAVOR, J., and VANSTONE, G.F.:'Technique for realising transversal filters using charge-coupleddevices',Proc.IEE, 1975,122, (6), pp. 615-19

2 BEYNON, J.D.E.: 'Charge-coupled devices - concepts, technolo-gies and applications', Radio & Electron. Eng., 1975, 45, pp.647-56

3 HARP, J.G., VANSTONE, G.F., MACLENNAN, D.J., andMAVOR, J.: 'Analogue correlators using charge coupled devices'.Proceedings of the international conference on the applicationof c.c.d.s,San Diego, 1975, pp. 229-35

4 MAVOR, J., ARTHUR, J.W., and DENYER, P.B.: 'Analoguec.c.d. correlator using monolithic m.o.s.t. multipliers', ElectronLett., 1977, 13, pp. 373-74

5 TIEMANN, J.J., ENGELER, W.E., BAERTSCH, R.O., andBROWN, D.M.: 'Intracell charge-transfer structures for signalprocessing',IEEE Trans., 1974, ED-21, pp. 300-08

6 BROWNE, V.A., and PERKINS, K.D.: 'A non-overlapping gatecharge coupling technology for serial memory and signal process-ing applications', ibid., 1976, ED-23, pp. 272-75

7 BRUGLER, J.S., and JESPERS, P.G.A.: 'Charge pumping inm.o.s. devices', ibid., 1969, ED-16, pp. 297-302

8 CARNES, J.E., KOSONOCKY, W.F., and RAMBERG, E.G.:'Free charge transfer in charge-coupled devices', ibid., 1972,ED-19, pp. 798-808

9 CARNES, J.E., KOSONOCKY, W.F., and RAMBERG, E.G.:'Drift-aiding fringing fields in charge-coupled devices', IEEEJ. SolidState Circuits, 1971, SC-6, pp. 322-326

10 EVANS, N.E., and GAMBLE, H.S.: 'Intracell c.c.d. programm-able correlator', Electron. Lett., 1977,13, pp. 69-71

11 HANDY, R.J.: 'Use of c.c.d. in the development of digitallogic', IEEE Trans., 1977, ED-24

12 TIEMANN, J.J., ENGELER, W.E., and BAERTSCH, R.D.: 'Asurface charge correlator', IEEE J. Solid-State Circuits, 1974,Sc-9

13 DENYER, P.B., and MAVOR, J.: 'Novel m.o.s. differentialamplifier for sampled-data applications', Electron. Lett., 1978,14,pp. 1-2

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