Unclassified

High Speed Electronics GroupFaculty of Electrical Engineering

(1 )RAFAEL, Armament Development Authority Ltd., Microelectronic Directorate(2 )Department of Electrical Engineering, Technion-Israel Institute of Technology

T. Magrisso T. Magrisso (1)(1)

D. Elad D. Elad (1)(1)

N. Buadana N. Buadana (1)(1)

S. Kraus S. Kraus (2)(2)

D. Cohen Elias D. Cohen Elias (2)(2)

A. Gavrilov A. Gavrilov (2)(2) S. Cohen S. Cohen (2)(2) D. Ritter D. Ritter (2)(2)

Unclassified

High Speed Electronics GroupFaculty of Electrical Engineering

InP Based VCOsInP Based VCOs

• Record frequencies• Optoelectronic integration: Optoelectronic Oscillitor, Clock recovery, etc..

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High Speed Electronics GroupFaculty of Electrical Engineering

Previous work on InP HBT circuits at TechnionPrevious work on InP HBT circuits at Technion::

75 GHz TWA 43 GHz integrated TWA photoreceiver

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High Speed Electronics GroupFaculty of Electrical Engineering

Varactors in InP HBT VCOsVaractors in InP HBT VCOs

• Previous InP HBT VCOs used base collector layers as varactor layers.

• Optimized HBT requires fully depleted collector at Vbc=0, for minimum VCO’s phase noise.

• As a results, small tuning range is obtained

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High Speed Electronics GroupFaculty of Electrical Engineering

InP Semi-insulating Substrate

Ga InAs N+ Sub-Collector

Ga InAs N Collector

Ga InAs P BaseInP N+ Emitter

N+

NP

N

N+

NP

Conventional InP HBT technologyConventional InP HBT technology

10um

1um

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High Speed Electronics GroupFaculty of Electrical Engineering

Separate varactor layersSeparate varactor layers

• Varactors and HBTs can be separately optimized.

• Varactor layers can be grown either above or underneath the transistor layers.

• Varactor layers underneath transistor layers complicate interconnect.

• Varactor layers above transistor layers require stepper technology.

Unclassified

High Speed Electronics GroupFaculty of Electrical Engineering

InP Semi-insulating Substrate

InP N+ Varactor Connect

InP N Varactor NGa InAs P BaseInP N+ Sub-Collector

InP N CollectorGa InAs P Base

InP N+ Emitter

N+

NP

N+

NP

N

InP HBT technology with Separate Varactor LayersInP HBT technology with Separate Varactor Layers

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High Speed Electronics GroupFaculty of Electrical Engineering

This WorkThis Work

• Carried out by contact lithography-varactor layers underneath transistor layers. • Wide tuning range Colpitts X band VCO demonstrated as first attempt.

• Simplified VBIC transistor model predicts well VCO’s performance.

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High Speed Electronics GroupFaculty of Electrical Engineering

Transistor PropertiesTransistor Properties

•Ft=180 GHz

•Fmax=200GHz

•Vturn-on=0.5V

•Vce-breakdown=5V

•Ic max )Vce=3v(=30mA

•βAC=50

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High Speed Electronics GroupFaculty of Electrical Engineering

Transistor ModelingTransistor Modeling

• DC Measurements and s-parameters

• Small-signal equivalent circuit parameters extraction.

• Degenerate VBIC model with 18 parameters only

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High Speed Electronics GroupFaculty of Electrical Engineering

VBIC large signal modelVBIC large signal model

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High Speed Electronics GroupFaculty of Electrical Engineering

VBIC model parameters extracted at specific biasVBIC model parameters extracted at specific bias , ,Does it work for large signal VCO modelingDoes it work for large signal VCO modeling? ?

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High Speed Electronics GroupFaculty of Electrical Engineering

Varactor Design & ModelingVaractor Design & Modeling

Varactor's C)V( [20X30um]

0

0.2

0.4

0.6

0.8

1

0 1 2 3 4 5

Voltage [V]

Ca

paci

tanc

e [p

F]

BC layers, Nd=1E16

New layers, Nd=1E17 Separate

We have compared 2 types of varactors:

1. Base-Collector layers.

2. Separate layers with Nd=1017 cm-3.

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High Speed Electronics GroupFaculty of Electrical Engineering

Varactor ModelingVaractor Modeling

• Different size varactors, for scaleable model extraction.

• Semi-lumped model

• Rectangular varactors achieving 1 ohm series resistance.

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High Speed Electronics GroupFaculty of Electrical Engineering

Varactor modelingVaractor modeling

Using simple model with text book equations.

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High Speed Electronics GroupFaculty of Electrical Engineering

VCO schematics – Colpitts configurationVCO schematics – Colpitts configuration

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High Speed Electronics GroupFaculty of Electrical Engineering

Vout

VE

VB

RR5R=50 Ohm

VARVAR4Vtune=4

EqnVar

HBT_Model_NL_Biased_3212X68Vcc=6

ParamSweepSweep1

Step=5Stop=20Start=0SimInstanceName[6]=SimInstanceName[5]=SimInstanceName[4]=SimInstanceName[3]=SimInstanceName[2]=SimInstanceName[1]="HB1"SweepVar="Vtune"

PARAMETER SWEEP

HarmonicBalanceHB1

OscPortName="Osc1"OscMode=yesMaxShrinkage=1.0e-5MaxStepRatio=400StatusLevel=2Order[1]=5Freq[1]=8 GHz

HARMONIC BALANCE

EM_ind3_10X61

3

21

HBT_Varactor_3196X64VR=Vtune

12

VCO_2ind_4_cap_resX51

21

I_ProbeIout

BE_capX44

2

4

1

5

3

VCO_collector_cap_N3X69

2

4

1

3

OscPortOsc1

MaxLoopGainStep=FundIndex=1Steps=100NumOctaves=3Z=2 OhmV=

Full EM SimulationFull EM Simulation

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High Speed Electronics GroupFaculty of Electrical Engineering

Testing VCOTesting VCO

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High Speed Electronics GroupFaculty of Electrical Engineering

Simulation vs. Measurments

7.8

8

8.2

8.4

8.6

8.8

9

0 0.5 1 1.5 2 2.5 3 3.5 4

Voltage [V]

Fre

q. [

GH

z]

Measurment

Simulation

Comparison between Measurement and Comparison between Measurement and Simulation with degenerate VBIC model Simulation with degenerate VBIC model

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High Speed Electronics GroupFaculty of Electrical Engineering

Measured phase noiseMeasured phase noise

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High Speed Electronics GroupFaculty of Electrical Engineering

Phase Noise SimulationPhase Noise SimulationPhase noise parameters extraction for VBIC model

Kfn=1E-12

Afn=1

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High Speed Electronics GroupFaculty of Electrical Engineering

ConclusionsConclusions

• InP HBT X band VCO with separate varactor layers underneath transistor layers achieved tuning range of 12% and phase noise of -94dB/Hz at 100KHz.

• Future work: VCO layers on top of transistor layers for higher frequencies, and optoelectronic applications. .

Unclassified

High Speed Electronics GroupFaculty of Electrical Engineering

AcknowledgementAcknowledgementWe would like to thank …..

• Dr. David Rosenfeld for supporting the project.

• Rafael Microelectronic Direcrotate Design groupe and Testing House.

• Technion Russell Berrie Nanotechnology Institute.

• Liron Arazi and Kochavi Shemuel for design and testing assistance.

• Dr. Asher Madjar.