Analog and Mixed Signal Designs Analog and Mixed Signal Designs

using FinFET Technologyusing FinFET Technology

Advanced Technology Architecture,

Office of the CTO

Gopal Srinivasan

Analog, Power & Mixed Signal Group

Srinivas.saripalle@globalfoundries.com

Srinivas Saripalle

ContentsContents

Challenges for Analog Design in Advanced Planar

Deep Sub-Micron Processes and FinFET as a

solution

Extra Care Abouts for FinFET

Page 2

Analog Benchmark FinFET vs. Planar

Broad Range of Platforms

Center of Excellence

- Analog & Mixed Signal Technologies

2GLOBALFOUNDRIES Confidential

Challenges for Analog Design in Advanced Planar Challenges for Analog Design in Advanced Planar

Deep SubDeep Sub--Micron Processes and FinFET as a Micron Processes and FinFET as a

solutionsolution

Page 3

Intrinsic Gain (Gm*Rout) decreases as we go from 28nm To Intrinsic Gain (Gm*Rout) decreases as we go from 28nm To 20nm 20nm

Av: Normalized to 28nm

Page 4

@ Same Bias Conditions

Headroom decreases as we go from 65nm Headroom decreases as we go from 65nm --> 20nm> 20nm

65nm

Page 5

Headroom = Vgs-Vt(sat)

45nm

28nm

20nm

For a given Useful Power Standby Power increasesFor a given Useful Power Standby Power increases

Normalized to 65nm

45nm65nm

Page 6

3x increase inStandby Power

20nm

28nm

Planar CMOS on bulk substrate has been the workhorse of the foundry industry for high performance and low power

Cost effective substrate, easy to integrate SoC passives (diodes, capacitors, varactors, resistors)

No Generic Process and Design solution to these No Generic Process and Design solution to these Challenges Challenges --> End of the Planar CMOS Era> End of the Planar CMOS Era

HK

MG

Page 7

P. Packan, IEDM 2009

Punchstop

Well

Source Drain

HK

MG

Halo

Higher doping to control drain degrades

sub threshold slope, mobility, junction

leakage, and increases variation

@fixed IOFF

‘Beyond Planar CMOS Era – Andy Wei ICICDT 2012

Evolution from Planar to FinFETEvolution from Planar to FinFET

G

Gate

S/D

S/D

Device Width

Page 8

Increase gate control by wrapping the Gate around the channel and

reduce drain control for steeper sub-threshold slope for lower voltage

operation and better short channel effects

‘Beyond Planar CMOS Era – Andy Wei ICICDT 2012

S D

PS

PSSTI

Channel

Introduction to FinFETs and Analog Advantages of Introduction to FinFETs and Analog Advantages of

FinFETsFinFETs

Page 9GLOBALFOUNDRIES Confidential

Fin Geometry, Dimensions & Operation for Bulk Fin Geometry, Dimensions & Operation for Bulk FinFETFinFET

WF = Fin WidthThis is critical for maximizing

FET density.

HF = Fin HeightThis directly effects FET

performance.

Effective Width = 2HF+WF

LG

Device Width

Page 10

Effective Width = 2HF+WF

LG = Gate Length

WF

HF

Regions of Current Flow

Region where gate will cover

Shallow Trench Isolation

(STI) or Local Isolation

FinFET (14XM) vs. Planar : Better Short Channel Effects FinFET (14XM) vs. Planar : Better Short Channel Effects

(SCE)(SCE)

Decrease in Vt:Planar -> FinFET

Page 11

Better SCE due to the fin leads to -•Larger Head room• Better SS at lower Lg• Higher Gain at lower (W eff / Lg)

Analog Performance : FinFET (14XM) to Planar : Better Analog Performance : FinFET (14XM) to Planar : Better

Gate Control leads to Higher GmGate Control leads to Higher Gm

@ Same Bias Conditions

Page 12

Gm is higher between FinFET and Planar and scales well with Length.

4x lower

Analog Performance : FinFET (14XM) to Planar : Better Analog Performance : FinFET (14XM) to Planar : Better

Gate Control leads to Lower GdsGate Control leads to Lower Gds

Page 13

Gds is lower for FinFET compared to Planar.

@ Same Bias Conditions

Analog Performance : FinFET (14XM) to Planar : Analog Performance : FinFET (14XM) to Planar : Better SCE, Better SCE,

High Gm and Lower Gds leads to Higher Intrinsic GainHigh Gm and Lower Gds leads to Higher Intrinsic Gain

Planar FinFET

~45%

@ Same Bias Conditions

Page 14

.

Av: Normalized to 28nm

RF RF Performance : FinFET (14XM) to Planar Performance : FinFET (14XM) to Planar Similar in Similar in

the Operation region of importance to RFthe Operation region of importance to RF

Vgs-Vt ~0.2

Page 15

•FinFETs and Planar have similar cutoff frequencies in Vgs-Vt~0.2V region over lengths.

(Vds =VDD)

•For the bias conditions where the transistor operates in most of the low power

Analog/RF applications, intrinsic fT are comparable to the planar 20LPM devices.

FinFETs vs. Planar : Low Freq Noise: NMOS : FinFETs vs. Planar : Low Freq Noise: NMOS : Similar Slopes and MagnitudeSimilar Slopes and Magnitude

Saturation Region

Page 16

γ ( 1/fγ ) are similar between Planarand FinFET

@ Same Bias Conditions

FinFET Process has Finified Passives:FinFET Process has Finified Passives:Characteristics of P+/NW Diode better than PlanarCharacteristics of P+/NW Diode better than Planar

At least 5 orders

of linear region

Page 17

Extra careExtra care--Abouts FOR FINFET of analog BLOCKSAbouts FOR FINFET of analog BLOCKS

Page 18

SoC ElectroSoC Electro--Migration Issue for FinFETsMigration Issue for FinFETs

Page 19

Requires

improved

Power grid

No FinFET Solution without solving EM Issue!

Effect of REffect of REXT EXT on Analog FoMson Analog FoMs

~20%

Page 20

Gate Length Limitation is not really a Gate Length Limitation is not really a Limitation!!!Limitation!!!

�Higher ROUT OR Lower GDS

� Similar GDS can be got with much smaller length

�Mismatch Criterion� AVT targets for FinFET are lesser than Planar, LFinFET ~ is

significantly smaller than LPlanar for similar σVT for same width.

Page 21

� Quantized Width� Quantized Width could lead to some limitations on sizing of the

device

Generic Process Flow: Mandrel Position Generic Process Flow: Mandrel Position determines Fin Positiondetermines Fin Position

Poly

mandrel

SiN

spacer

Poly

mandrel

SiN

spacer

Page 22

finfin

Post MOLFins created at the sides of the MandrelBy SIT process.

One more layer to worry about to reduce One more layer to worry about to reduce mismatch during Layout : Mandrelmismatch during Layout : Mandrel

Odd # of Fins in a single RXPolygon:

Identical Mandrel placement necessaryNon-Identical Mandrel placement couldcause for variation

Even # of Fins in a single RXPolygon: Placement of Mandrel not an

issue

AB

MANDREL

FIN

FIN

Page 23

FN Shape A: 3 finsFN Shape B: 2 fins

B

Upfront Design Solution – Make sure that Diff pairs are designed such that they have even # of Fins. For centroid type layout, for example, designed # of Fins should be mod(#of Fins, 4)=0

A

MANDREL

RX

RX

Passives Limitations in a FINFET Passives Limitations in a FINFET ProcessProcess

Compared to Planar:

• Gate Density Requirements are stringent.

• Length is quantized due to Dummy PC

• Height is quantized due to Fin Pitch

• Cut Mask mask for all the PC – (Good layout

Page 24

• Cut Mask mask for all the PC – (Good layout practice in general).

14XM vs. 20LPM : Analog Benchmark Circuit : 14XM vs. 20LPM : Analog Benchmark Circuit : Performance and Power:Performance and Power:

• Power: The TX pre-driver in 14nm takes about 40% less power than the 20nm design.

• Performance: The 14nm design edge rate for most of the stages is almost double as compared to the 20nm design

Page 25

20nm design

Devices in 14XM that are important for Analog/RFDevices in 14XM that are important for Analog/RF

Page 26

Other devices of Analog Interest (experimental @ this stage): ZVT, ULVTAll the devices supported in a Planar process supported in 14XM

Broad Range of Process PlatformsBroad Range of Process Platforms

20nm PlanarCost-optimized,

UnifiedLEADING

14XM FinFETeXtremeMobility

Analog, Power &

Mixed-Signal

Page 27

27

Volume production-proven In development

180 – 40nmMixed-technology

Solutions

28nmPerf/power/cost

Optimized

UnifiedLEADING

EDGE

ADVANCED

MAINSTREAM

Center of Excellence Center of Excellence –– Analog & Mixed Signal Technologies Analog & Mixed Signal Technologies

0.18um modular platform (Digital/ Analog/ Power/ eNVM)

0.13um modular platform (Digital/ Analog/ Power/ RF/ eNVM)

65/55nm modular platform (Digital/ Analog/ Power/ DDI/ eNVM)

40nm modular platform (Digital/ Analog/ RF)

Platforms & Technologies

Offerings

Page 28

28CONFIDENTIAL

RF Module

BCD Module

eNVMModule

Baseline Process

CollaborativeDevice

Manufacture

Thanks to the many authors whose work was reproduced in this talk.

Thanks to Andy Wei, Paul Schroder and other members of Advanced Technology Architecture Group for their contributions to this talk.

AcknowledgementsAcknowledgements

Page 29

contributions to this talk.

SummarySummary

Challenges to Analog/RF Design in Planar Submicron Processes presented.

Advantages of FinFET over Planar for Analog Performance.

Analog Benchmarking using real SOC Analog blocks. Simulations results presented.

Page 30

blocks. Simulations results presented.

Page 3131

THANK YOU!