Table of Contents Introduction.................................................................................................................................................... 3
Theory of Operation ...................................................................................................................................... 4
How to Setup the Hardware for Link Test ..................................................................................................... 8
How to Reconstruct and Running the Reference Design ............................................................................. 8
Revision History .......................................................................................................................................... 19
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Introduction
The objective of this design example is to demonstrate how to perform a SDI link loopback test in a Triple-rate SDI link using the SDI Console in Arria 10 SoC Development Kit. This design comes with a SDI pattern generator up to 3G video mode which allow the loopback test from SDI TX to RX for TRS and Frame locks monitoring. The SDI Console provides a GUI to assist user in the link test by allowing real time control on the SDI link ie changing the SDI TX video pattern and enabling transceiver toolkit tuning. The SDI Console also allows link status monitoring ie TRS lock, Frame lock and RX video pattern detection. The SDI Console works together with transceiver toolkit to perform PMA analog settings tuning for the SDI link.
Requirements The reference design requires the following hardware and software to run the test:
• Quartus® Prime Software Version: 17.0 Standard Edition
• Arria 10 SoC Development Kit https://www.altera.com/products/boards_and_kits/dev-kits/altera/arria-10-soc-development-kit.html
• FPGA Mezzanine Card (FMC) to High Speed Mezzanine Card (HSMC) adapter board http://www.kayainstruments.com/fmc2hsmc/
Figure 2. Block diagram of modules in the reference design
Figure 2 shows the high-level modules in the reference design as well as the interfaces among the
modules. The A10 transceiver Native PHY is used to configure and implement the hard transceiver
channels. The SDI II Triple-rate IP would perform the SDI protocol operation. The transceiver
reconfiguration management module will perform the dynamic rate change to support different video
modes for triple-rate SDI. The SDI II Triple-rate IP will perform auto rate switch to lock to the incoming
video mode from SD-SDI up to 3G SDI. This SDI pattern generator support video pattern up to 3G SDI
video mode which allow the loopback test from SDI TX to SDI RX for TRS and Frame lock monitoring. The
SDI Console provides a GUI to assist user in the link test by allowing real time control on the SDI link ie
changing the SDI TX video pattern and enabling Transceiver Toolkit tuning. The SDI Console also allows
link status monitoring ie TRS lock, Frame lock and RX video pattern detection. The Transceiver Toolkit
interface with the Native PHY which allow dynamic PMA analog tuning and BER test.
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Figure 3. GUI of the SDI Console
Figure 3 shows the GUI interface of the SDI Console. The following provide further details on each of the
section in the SDI Console:
1. TTK Tuning – Turning this mode ON would allow Transceiver Toolkit to take full control of the
transceiver and avoid the RX being reset and reconfigured by SDI II IP. Note that you should
enable this before you launch the transceiver toolkit and perform PMA analog tuning. After you
have done with transceiver toolkit, disable this mode to allow the SDI link to resume normal
functionality.
2. Refresh Link Status Button – This is the refresh button to re-populate the status in the SDI Link
Status section.
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3. PAL/NTSC Selection – Select between PAL or NTSC mode for the TX video
4. TX Video Pattern Select – Shows the TX video pattern selected by user
5. TX Video Pattern Buttons – Allows user to dynamically select and change the TX video pattern.
All the supported video patterns are listed by different buttons for easy access
6. TX Video Standard – Transmitter video standard. You may refer to SDI II IP Core User Guide ->
"Table 4-5: Transmitter Protocol Signals" for further details on the decoding.
7. TX Video Format - Transmit video format. You may refer to SDI II IP Core User Guide -> "Table 3-
5: Video Pattern Generator Top Level Signals" for further details on the decoding.
8. RX Video Standard – Receiver video standard. You may refer to SDI II IP Core User Guide ->
"Table 4-6: Receiver Protocol Signals" for further details on the decoding
9. RX Video Format - Receiver video format. You may refer to SDI II IP Core User Guide -> "Table 4-
7: Video Format Values" for further details on the decoding
10. RX Video Pattern – Shows the video pattern received by the SDI RX
11. TRS and Frame Lock LEDs - Show the lock status signals for rx_trs_locked and rx_frame_locked
Transceiver toolkit is generally used to find the optimal PMA analog settings of the transceiver for a
board setup. Transceiver toolkit comes with user interface to allow user to real time interface through
with the transceiver as well as dynamically change the PMA analog settings on-the-fly by just clicking
buttons. User will just need to select a specific PMA analog value from the drop-down list and the toolkit
will help to perform the background dynamic reconfiguration steps. With the help of transceiver toolkit,
user will be able to perform Auto-sweep to find the optimal settings for a link. Figure 4 shows an
example of the transceiver toolkit GUI and the VOD settings drop-down list.
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Figure 4. Transceiver Toolkit UI And VOD Settings Drop-down List Since there is no HSMC connector available on the Arria 10 SoC Development Kit, the FPGA Mezzanine Card (FMC) to High Speed Mezzanine Card (HSMC) adapter board is used to allow connection with the SDI HSMC Board. The BNC cable is then used to form a loopback link from the SDI TX to SDI RX to perform the loopback test. Figure 5 shows an example of the connection of the boards and BNC cable.
Figure 5. Board Setup for SDI Link Loopback Test
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How to Setup the Hardware for Link Test Follow these steps to setup the hardware to run the reference design:
1. Connect the FPGA Mezzanine Card (FMC) to High Speed Mezzanine Card (HSMC) adapter board
to FMC B daughtercard port of the Arria 10 SoC Development Kit
2. Connect the SDI HSMC Board to the HSMC connector of the FMC to HSMC adapter board
3. Connect one BNC cable from SDI OUT2 to SDI IN2 on the SDI HSMC Board
4. Use the default switching settings. For more details about default switching settings, please
refer to Arria 10 SoC Development Kit user guide
5. Connect the USB cable to the USB Blaster connector on the development kit
6. Connect the power adapter shipped with the development board to power supply jack
7. Turn On the power for the Arria 10 SoC Development Kit. The hardware system is now ready for
programming
How to Reconstruct and Running the Reference Design Follow these steps to reconstruct, compile and run the design:
1. Follow the instruction in the Design Store to prepare the design template and load the design
into your Quartus software
2. Perform full compilation with the design
3. Program the SOF file generated into the Arria 10 SoC Development Kit
4. After the programming is completed, open the System console and load the top.sof to establish
connection to the device as shown in Figure 6
5. At the System Console -> TCL Console, type “source a10_sdi_console_1p3.tcl” to launch the SDI
Console as shown in Figure 7.
6. The SDI Console will be launched as shown in Figure 3
7. Select your target TX video pattern by clicking the TX Video Pattern button. Figure 8 shows the
SDI Console GUI with SD PAL TX video pattern selected.
8. You can then check the TX and RX link status in the SDI Link Status section of the SDI Console. As
shown in Figure 8, the standards, formats and lock status will be populated. The received video
pattern will be shown to ease the user to cross check with the TX video pattern sent.
9. You can click on the Refresh Link Status button to update the link status in the SDI Console.
10. Figure 9 shows another example of the SDI Console GUI with 3Ga 1080p60 TX video pattern
selected.
11. To perform the transceiver PMA analog settings tuning with Transceiver Toolkit, send a 3G TX
video pattern to the RX so that the RX is reconfigured to 3G mode. Then enable the TTK Tuning
mode in the SDI Console as shown in Figure 10
12. Launch the transceiver toolkit at System Console -> Tools -> Transceiver Toolkit as shown in
Figure 11
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13. Click on the Transceiver Toolkit -> Transceiver Links -> Control Transceiver Link to establish
control over the TX and RX as shown in Figure 12
14. You can now perform the PMA analog settings tuning and BER test in the Transceiver Toolkit as
shown in Figure 13. You may also refer to the Arria 10 SX Triple-rate SDI with Transceiver Toolkit
Reference Design User Guide for further detail on running PMA analog tuning and BER test in
the Transceiver Toolkit with the SDI link.
15. Note that when the BER test is running in the Transceiver Toolkit, you will observe the SDI RX
lose the TRS and Frame lock as shown in Figure 14. This is expected because the SDI RX is now
receiving PRBS pattern sent by the Transceiver Toolkit.
16. After the tuning is completed, stop the BER test in Transceiver Toolkit and disable the TTK
Tuning mode in System Console. You can now see the SDI RX resume locking to the video
pattern as shown in Figure 15.
Figure 6. Loading the SOF in System Console to establish connection to the device
Conclusion The design example provides a reference on how to perform a SDI link loopback test in a Triple-rate SDI link using the SDI Console in Arria 10 SoC Development Kit.
