Asdesach Zena Markos

Efficiency Enhancement of Linear GaN RF power Amplifiers Using the Doherty Technique

This work has been accepted by the faculty of electrical engineering / computer science of the University of Kassel as a thesis for acquiring the academic degree of Doktor der Ingenieurwissenschaften (Dr.-Ing.). Supervisor: Prof. Dr.-Ing. G. Kompa Co-Supervisor: Prof. Dr.-Ing. A. Bangert Defense day: 06th November 2008 Bibliographic information published by Deutsche Nationalbibliothek The Deutsche Nationalbibliothek lists this publication in the Deutsche Nationalbibliografie; detailed bibliographic data is available in the Internet at http://dnb.d-nb.de. Zugl.: Kassel, Univ., Diss. 2008 ISBN print: 978-3-89958-622-0 ISBN online: 978-3-89958-623-7 URN: urn:nbn:de:0002-6235 © 2009, kassel university press GmbH, Kassel www.upress.uni-kassel.de Printed by: Unidruckerei, University of Kassel Printed in Germany

http://dnb.ddb.de/

Dedicated to my parents for their love, devotion and prayers.

Acknowledgments

I wish to express my sincere gratitude to Prof. Dr. -Ing. G. Kompa, for giving me the opportunity to carry out this research work at the Department of High Frequency Engineering (HFT), University of Kassel. His intellectual supervision during the course of this work has been inspiring.

Special thanks goes to TARGET (Top Amplifier Research Group in a European Team) for funding part of this research work. Particularly, I would like to thank Prof. P. Colantonio, Prof. F. Giannini and Dr. R. Giofrè of the Department of Electronic Engineering, University of Rome, “Tor Vergata”, Italy. Their cooperation and supervision during my stay at their department was tremendous.

I am indebted to Prof. Dr. -Ing. A. Bangert, for accepting to be a second examiner and also to the members of the disputation committee Prof. Dr. rer. nat. K. - J. Langenberg and PD Dr. -Ing. R. Marklein.

My gratefulness is directed to Mr. S. Dahmani, Mr. S. Embar, Mr. R. Ma, Dr. -Ing. E. S. Mengistu, Mr. S. Monsi, Mrs. H. Nauditt, Dipl. -Ing. J. Weide, Dipl. -Ing. B. Wittwer, Mr. A. Zamudio, and all other members of the HFT who are not mentioned by name. Their kind help at the office and in the laboratories is highly appreciated.

I am thankful to Mr. Beyene Aleme, Dr. Kassahun A. Belay, Dipl. -Ing. Dawit Negash, Dr. Eva Rau, family members and friends for their unreserved encouragement and support over the past several years.

Asdesach Zena Markos

Kassel, November 2008

Contents

Chapter 1: Introduction 1

1.1 Challenges in Power Amplifier Design..……….……………………………...2 1.2 Average Efficiency…………………….……………………………………....3 1.3 Thesis Organization………………….………………………………………...6

Chapter 2: AlGaN/GaN HEMT Modeling 8

2.1 GaN Material Properties……….………………………………………………8 2.1.1 AlGaN/GaN HEMT…………………………………………………….11 2.1.2 Performance Limiting Factors………………………………………….13

2.2 Device Modeling Approaches.....…………………………………………….14 2.3 Small-Signal Modeling………….…………………………………………....17

2.3.1 Extrinsic Parameter Extraction…………………………………………18 2.3.2 Intrinsic Parameter Extraction………………………………………….21

2.4 Large-Signal Modeling……………………………………………………….26 2.4.1 Gate Current and Charge Models……………………………………….28 2.4.2 Drain Current Model……………………………………………………29 2.4.3 Model Verification……………………………………………………...34

2.4.3.1 Pulsed I(V) Characteristics…………………………………….35 2.4.3.2 Output Power and Efficiency………………………………….35 2.4.3.3 Intermodulation Distortion Prediction…………………………36

Chapter 3: Linearity and Efficiency in Power Amplifiers 38

3.1 Class of Operation..…………………………………………………………..39 3.1.1 Conventional Amplifiers.………….……………..………………….…39 3.1.2 Harmonic Tuning Techniques.….………..…………………………….44

3.2 Nonlinearity and Memory Effect …………………………………………..49 3.2.1 Harmonics, AM/AM and AM/PM………………..………………….…49 3.2.2 Intermodulation Distortion....……………..…………………………….50 3.2.3 Adjacent Channel Power Ratio………..……………………………..…52 3.2.4 Memory-Effects...………………..……………………………………..53

3.3 Efficiency Enhancement Techniques…..…………………………………….55

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Chapter 4: Single-Stage GaN Power Amplifier Design 59

4.1 2W Class-AB GaN Power Amplifier Design……..…………………………...60 4.1.1 Matching Network Design………….…………………………………..61

4.1.1.1 Output Matching …….…………..……………………… ….61 4.1.1.2 Input Matching………....………………………………...……67

4.1.2 Bias Network Design…………………………………………………..69 4.1.3 Performance Evaluation..……..………………………………………..72

4.1.3.1 Single-Tone Power Sweep…………………………………….74 4.1.3.2 Two-Tone Test.….………...…..………...….………………...76 4.1.3.3 W-CDMA Characterization.……..……………………………79

4.2 3W Class-F GaN Power Amplifier Design ...…..……………………………80 4.2.1 Output Matching Network……….....…...…….……………...……...…82 4.2.2 Input Matching Network………..………….……………………………83 4.2.3 Waveform Simulations ....…....….……………………………………...85 4.2.4 Performance Evaluation .………….…………………………………….86

4.2.4.1 Output Power and Efficiency……………………………….…87 4.2.4.2 Linearity Characterization……………………………………..89

Chapter 5: Doherty Amplifier Design 92

5.1 Doherty Operation………..…………………………………………………...92 5.1.1 RF Characteristics…...……………………………………………….…100 5.1.2 Implementation Technique…………………...………………………...104

5.1.2.1 Uneven Doherty Technique………………………………….106 5.1.2.2 Practical Considerations……………………………………..110

5.1.3 Linearity of Doherty Amplifier…………………...……………………112 5.2 4W GaN Doherty Amplifier Design…….…………………………………..115

5.2.1 Main Amplifier……….…………...……….……..….………………….117 5.2.2 Peaking Amplifier……….…………….…..……………………...……120 5.2.3 Power Divider and Combiner……….….….…………………………...122

5.2.3.1 Uneven Power Divider………………………………………122 5.2.3.2 Combiner…………………………………………………….124

5.2.4 Load Modulation…………………...…………………………………..125 5.2.5 Performance Evaluation…………...…………………………………...126

5.2.5.1 Output Power and Efficiency ……………………………...128 5.2.5.2 Linearity Characterization...…………………………………131

5.3 7W GaN Doherty Power Amplifier Design…….…………………………..133

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5.3.1 Design and Simulation……….…………………………………………134 5.3.2 Performance Evaluation……...………………………………………...138

5.3.2.1 Output Power and Efficiency… ………………………...139 5.3.2.2 Linearity Characterization …………………………………142

Chapter 6: Conclusion and Further Work 145

Appendices 150

A. Measurement Setups……………………………………………………....150 A.1 Time Domain Measurement Setup.....………………………………150 A.2 Frequency Domain Measurement Setup..…………...………………151

B. Switch Mode Amplifier....……………………..………………………….153 B.1 Class-D Amplifier..…………………………………………………153 B.2 Class-E Amplifier..…………………………………………………154

C. Lumped Element Characterization .………………………………………156 D. Schematics Circuits of Designed Power Amplifiers…..………….……….158

References 163

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List of Figures Figure 1.1 Power loss in a 10W amplifier as function of its efficiency……….....…….4 Figure 1.2 Efficiency of an ideal class-B amplifier as a function of output power back-off……………………...……………………………….…..….4 Figure 1.3 Illustration of average efficiency in a single-stage amplifier driven with variable envelope signal with 8.5 dB PAR …………….…..….5 Figure 2.1 Basic AlGaN/GaN HEMT structure………………….………………..….11 Figure 2.2 AlGaN/GaN HEMT on Si…..……………………………………………..12 Figure 2.3 Large-signal table based model derivation process ………………………16 Figure 2.4 Photo of the investigated 2-mm (10 x 200 µm) AlGaN/GaN on Si HEMT. ………………..….…………………..…....….17 Figure 2.5 A 22-element distributed model for a GaN HEMT.………………..….….17 Figure 2.6 Pinch-off S-parameter fitting …………….... …………………….......…..21 Figure 2.7 Extracted Cgs, Gm, Cgd and Cds ………………...…..…………………....…22 Figure 2.8 Extracted Gds, Ri, τ, Ggdf, Ggsf and Rgd………………………………..…....24 Figure 2.9 Extracted Cgs as a function of the intrinsic voltages…………………..…..25 Figure 2.10 Comparison of measured and simulated S-parameters.…………………..25 Figure 2.11 Large-signal model topology for AlGaN/GaN HEMT..…..….………..…26 Figure 2.12 Extracted gate current sources...…………………………….……….…...29 Figure 2.13 Extracted charge sources………………….. …………………….….…...29 Figure 2.14 Pulsed I(V) measurements to characterize surface trapping………….…..30 Figure 2.15 Pulsed I(V) measurements to characterize buffer trapping………….. …..31 Figure 2.16 Pulsed I(V) measurements with a 10Ω serious stabilization resistor ….…32 Figure 2.17 Pulsed I(V) measurements to characterize self heating effect ……….…..32 Figure 2.18 Extracted bias-dependent fitting parameters to model the drain current…33 Figure 2.19 Comparison of measured (lines) and simulated (symbols) S-parameters...34 Figure 2.20 Pulsed I(V) simulations (lines) and measurements (symbols) …….….….35 Figure 2.21 Single-tone power sweep simulations and measurements (class-AB )..... .36 Figure 2.22 Single-tone power sweep simulations and measurements (class-C)….......36 Figure 2.23 Two-tone measurement and simulation (f0 = 2.14 GHz, ∆f = 200 kHz).....37 Figure 3.1 Load-lines of various class of operations...……………..……...…..…...…39

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Figure 3.2 Tuned-load analysis………...…………....…………….…………...……..40 Figure 3.3 Output current and efficiency of reduced conduction angle mode………..41 Figure 3.4 Single-stage amplifier under single-tone excitation ………………...…….44 Figure 3.5 Maximally flat third harmonic peaking class-F amplifier…………...…….46 Figure 3.6 Intrinsic gate source capacitance (Cgs)…………………………………….48 Figure 3.7 In-band amplifier output spectrum (two-tone excitation)…………………51 Figure 3.8 Higher order derivatives of Gm for a 2-mm GaN HEMT………….....…....52 Figure 3.9 Definition of offset and bandwidths of a single carrier W-CDMA spectrum for ACPR calculation..…………………………………….…....53 Figure 3.10 Vector summation of IMD3 products.………………………………...….55 Figure 3.11 Doherty amplifier technique: block diagram and ideal efficiencies …...…57 Figure 4.1 Single-stage amplifier design procedure through nonlinear analysis approach …………………………………………….…...……….60 Figure 4.2 Block diagram of a single-stage amplifier circuit…...………………..…...61 Figure 4.3 Extrinsic load impedance determination technique...………..……………63 Figure 4.4 Load-pull measurements of a 2-mm GaN device ...………………..……..64 Figure 4.5 Simulated load-pull contours of a 2-mm GaN device……………..………64 Figure 4.6 Output matching network: (a) topology and (b) Smith chart illustration… 66 Figure 4.7 Output matching network: (a) schematic and (b) simulated transmission and return losses...…….………………...……..….67 Figure 4.8 Simulated S21 and MAG with conjugate matching (at 2 GHz)……………68 Figure 4.9 Input matching network………………………………...………….…..….69 Figure 4.10 A short circuited λ/4-line drain bias network……………….…...……….71 Figure 4.11 Simulated envelope impedance of the bias network……………….……..71 Figure 4.12 Radial stub drain bias network…………………………..………….…….71 Figure 4.13 Gate bias network: (a) topology and (b) simulated transmission and return losses .…………………………….…………………………...72 Figure 4.14 2W GaN class-AB amplifier circuit schematic...…………………………72 Figure 4.15 Simulated intrinsic waveforms of class-AB amplifier...………..….…..…74 Figure 4.16 2W GaN class-AB amplifier photo and small-signal response ……...…...74 Figure 4.17 Single-tone power sweep harmonic measurements at a class-AB

bias point….……………………………………………………………...75 Figure 4.18 Single-tone power sweep measurements at a class-AB bias point …....75 Figure 4.19 Single-tone power sweep measurements at a class-C bias point …......….75 Figure 4.20 Two-tone power sweep simulation and measurements………...….……...77 Figure 4.21 Two-tone measurements (∆f = 5 MHz and f = 200 kHz)...…………..….78 Figure 4.22 Measured output powers and lower IMDs at ∆f = 5 MHz …….…………78

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Figure 4.23 Single-carrier W-CDMA (Test Model 1, 32 DPCH) measurement…..…..79 Figure 4.24 Measured output powers and upper ACP at three different bias points.….80 Figure 4.25 Power gain cut-off frequency (fmax) of a 2-mm GaN device……...……....82 Figure 4.26 Output matching: (a) network topology and (b) simulated load impedances at fundamental, second and third harmonic frequencies...…..83 Figure 4.27 Input matching: (a) network topology and (b) simulated input impedances at fundamental, second and third harmonic frequencies…....84 Figure 4.28 3W class-F amplifier schematic circuit……………...……..………...…...85 Figure 4.29 Single-tone simulations (at 1 dB compression point) ……………...….…85 Figure 4.30 3W class-F amplifier measured and simulated S-parameter s………....…87 Figure 4.31 Single-tone power sweep simulation and measurement………………….88 Figure 4.32 Single-tone power sweep harmonic measurement…………...……….…..88 Figure 4.33 Single-tone measurements at three different bias point….……..……......88 Figure 4.34 Measured fundamental output power, upper and lower IMD3s.….……...89 Figure 4.35 Measured lower IMD3s at VGS0 = -1.25V, -1.3V, and -1.65V..……..…...90 Figure 4.36 Single-carrier W-CDMA (Test Model 1, 32 DPCH) measurement.….….90 Figure 5.1 Doherty amplifier: (a) schematic and (b) equivalent circuit………...…....94 Figure 5.2 Doherty amplifier load-lines: (a) main and (b) peaking amplifiers….........99 Figure 5.3 Output signals of main (lines) and peaking (symbols) amplifier………...102 Figure 5.4 Theoretical efficiency of Doherty amplifier (6 dB back-off)………..…...102 Figure 5.5 Doherty amplifier: (a) impedances of main and peaking amplifiers

and (b) output powers of main , peaking and Doherty amplifiers...….....103 Figure 5.6 Efficiency of a Doherty amplifier (for ψ = 0.33, 0.25 and 0.2)...………..104 Figure 5.7 Ratio of IP to IM (for θΜ = 1.1π).................................................................105 Figure 5.8 Simplified device characteristics for Doherty operation: (a) main amplifier and (b) peaking amplifier …......…….……………………..….106 Figure 5.9 Doherty amplifier output currents: main, peaking (uneven and even) …..109 Figure 5.10 Doherty amplifier characteristics.……...……………..…………………109 Figure 5.11 Simulated optimum efficiency vs. phase delay of a 2.6W AlGaN/GaN Doherty amplifier.……………………………………………...…..…...111 Figure 5.12 Active device I(V) characteristics….………….………………..……….117 Figure 5.13 Output matching network of the main amplifier……………………...…119 Figure 5.14 Single-tone measurement (symbols) and simulation (lines)……….…....119 Figure 5.15 Output matching network of the peaking amplifier…………...……...…121 Figure 5.16 Single-tone measurement (symbols) and simulations (lines) …….…......121 Figure 5.17 Uneven Wilkinson power diver: (a) schematic and (b) simulated and measured (o) transmission coefficients....…………………….…….123

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Figure 5.18 Doherty combiner: (a) schematic and (b) simulated transmission and return losses...…...….….………….…………….……124 Figure 5.19 Simulated behaviors of the Doherty amplifier..…...………...….…....….126 Figure 5.20 Simulated load modulation of the main and peaking amplifiers….....…..126 Figure 5.21 4W GaN Doherty amplifier: (a) schematic circuit and (b) photo of the realized amplifier on a Teflon substrate.…….………..………….127 Figure 5.22 Simulated (lines) and measured (symbols) small-signal characteristics of the 4W GaN Doherty amplifier...………….………....128 Figure 5.23 Single-tone power sweep measurement (symbols) and simulation (lines) at 2.14 GHz……..…………………………….………129 Figure 5.24 Comparison of PAEs of class-AB and Doherty amplifier…...……...…..130 Figure 5.25 Measured AM/AM and AM/PM of the Doherty amplifier…...…...…….130 Figure 5.26 Measured IMD3 of the 4W Doherty amplifier.……………..……….….131 Figure 5.27 Single-carrier W-CDMA (Test Model 1, 32 DPCH) measurements …...132 Figure 5.28 1-mm GaN HEMT die photo........…………..………….….……………133 Figure 5.29 1-mm GaN device I(V) characteristics………….……….….….……….134 Figure 5.30 Output matching network of the main amplifier……...……...…..……...135 Figure 5.31 Output matching network of the peaking amplifier...….…….…………136 Figure 5.32 Simulated load-lines of 7W Doherty amplifier ..………….……….……137 Figure 5.33 Photo of realized 7W Doherty amplifier ……...………………………..138 Figure 5.34 Small-signal gain and input return loss of 7W Doherty…………………139 Figure 5.35 Single-tone measured and simulated performance of 7W Doherty ..…...140 Figure 5.36 Single-tone measured performance for three peaking

amplifier bias points………………………..…………………………...141 Figure 5.37 Measured IMD3 with main amplifier bias point fixed and peaking amplifier bias point varying……………….……………….………...…..142 Figure 5.38 Single-carrier W-CDMA (Test Model 1, 32 DPCH) measurements…....143 Figure A.1 Schematic diagram of time domain measurement setup…………….…..151 Figure A.2 Schematic diagram of frequency domain measurement setup………….151 Figure B.1 Class-D amplifier theoretical voltage and currents……………………...153 Figure B.2 Class-E amplifier theoretical voltage and currents………………………154 Figure C.1 Equivalent circuit of a chip capacitor ………………………………..…156 Figure C.2 Measured (lines) and simulated (symbols) of a 22 pF chip capacitor...…157 Figure C.3 Equivalent circuit of an AVX chip capacitor.………………..………….157 Figure D.1 Circuit schematic of a 2W GaN class-AB amplifier: ……...……………158 Figure D.2 Circuit schematic of a 3W GaN class-F amplifier: …………...……..….159 Figure D.3 Circuit schematic of a 4W GaN Doherty amplifier…………….……….162

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List of Tables Table 2.1 Semiconductor material properties and features ………….………………....9 Table 2.1 Material properties of common semiconductor ………………………...……9 Table 2.3 Architectural benefits of GaN device.…………….…………………...……10 Table 2.4 Starting value pinch-off device parameters of a 2-mm AlGaN/GaN HEMT with a 10 x 200 µm gate width………….……...…..…20 Table 2.5 Optimized pinch-off device parameters of a 2-mm AlGaN/GaN HEMT with a 10 x 200 µm gate width…………..…………....20 Table 3.1 Summarized properties of reduced conduction angle modes amplifier …... 43 Table 4.1 Optimum output impedances (for maximum output power)……………......83 Table 4.2 Optimum input impedances (taken at maximum PAE) .……………...…….84 Table 4.3 Summary of performances of the 4W and 7W Doherty amplifiers .………..91 Table 5.1 Power amplifiers requirements for a 3G basestation………………………115 Table 5.2 Summary of performances of the 4W and 7W Doherty amplifiers……......144 Table 5.3 Comparison of published Doherty amplifier data .…………………....144

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List of Symbols Cgs, Cds, Cgd Intrinsic gate-source, drain-source and gate-drain capacitance F Cpdi, Cpgi, Cgdi Inter-electrode capacitances F Cpga, Cpda, Cgda Parasitic pad capacitances F Cth Thermal capacitance s·W/K CGT, CDT Part of an RC network to model trapping time constants F c0 Velocity of light (= 30 x 108) cm/sec ft Current gain cutoff frequency Hz fmax Power gain cutoff frequency Hz Ggsf, Ggdf gate-source and gate-drain diode conductances S Gm Channel transconductance S Gds Drain-to-source conductance S Igs, Ids Intrinsic gate-source and drain-source current A IGS, IDS Extrinsic gate-source and drain-source current A IM, even Drain current of main amplifier of even Doherty A

IP, even Drain current of peaking amplifier of even Doherty A IM, unevn Drain current of main amplifier of uneven Doherty A IP, unevn Drain current of main amplifier of uneven Doherty A Imax Maximum drain-source current (gate-forward bias) A IDSS Saturated drain-source current (zero gate bias voltage) A

ISODSI Isothermal drain source DC current A

G Power gain dB k Power division ratio Lg , Ld , Ls Gate, drain, and source inductance Η l Electrical length of microstrip line mm m Voltage transformation ratio n Number of harmonics ns Sheet charge concentration cm-2

p Power back-off W PAE, PAE_total

Power added efficiency, total power added efficiency %

Pdiss Instantaneous dissipated power W PDC Dissipated DC power W Pin, Pin, avg RF input power, average input power W Pin, M, Pin, P RF input powers to main and peaking amplifiers W Pout, Pout,avg Output power, average output power W q Electron charge C Qgs Gate-source charge C Qgd Gate-drain charge C

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Rth Thermal resistance K/W Ropt Optimum output impedance Ω Rg, Rd, Rs Gate, drain, and source resistance Ω Ri Gate-source charging resistance Ω Rgd Gate-drain charging resistance Ω RGT, RDT Part of an RC network to model trapping time constants Ω Sij Two-port scattering parameters (i, j = 1,2) VB Drain-Source voltage of main amplifier at breaking point V Vbr Breakdown voltage V VDS0, M, VDS0, P Bias drain-source voltages of main and peaking amplifier V VGS0, VDS0 Bias gate-source and drain-source voltage V VGS, VDS Extrinsic gate-source and drain-source voltage V Vgs, Vds Intrinsic gate-source and drain-source voltage V VGS0, M, VGS0, P Bias gate-source voltages of main and peaking amplifier V Vin,Vin ,M, Vin,P RF input voltage (total, main, and peaking amplifiers) V Vk Knee voltage V VM Main PA output voltage V VP Pinch-off gate-source voltage V VPK Peaking amplifier output voltage V Vpk, M, Vpk, P Peak RF output voltage of the main and peaking amplifier V vs Saturation velocity cm/s x Maximally flat third harmonic component ratio Yij Two-port small-signal admittance parameters (i, j = 1,2) S Zf0 Intrinsic load impedance Ω ZP, ZM Impedance of main and peaking amplifier Ω ZL Load impedance Ω Z0 Characteristic impedance Ω Zout, Zin Output and input impedances Ω α Conduction angle rad αD Model for traps associated with deep-level A/V αG Model for traps associated with surface state A/V αT Model for thermal effects A/K

T∆ Change in channel temperature K εr, εff(f0) Relative dielectric permittivity, effective dielectric constant η, ηavg Drain efficiency, average drain efficiency % κ Thermal conductivity W/cm·K λ Wavelength cm ψ Doherty peaking point ξ Current ratio of peaking to main amplifier τ Transit delay time S µ Electron mobility cm2/V·s ω Angular frequency Rad

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List of Abbreviations and Acronyms 2-DEG Two-Dimensional Electron Gas 3G Third Generation 3GGP Third Generation Partnership ACLR Adjacent Leakage Power Ratio ACP, ACPR Adjacent Channel Power, Adjacent Channel Power Ratio ADS Advanced Design System AM Amplitude Modulation BTS Base Transceiver Station CAD Computer Aided Design CAPEX Capital Expenditure CCDF Complementary Cumulative Distribution Function CW Continuous Wave DC Direct Current DiVA Dynamic I(V) Analyzer DPD Digital Predistortion EER Envelope Elimination and Restoration FET Field Effect Transistor HEMT High Electron Mobility Transistor GaN Gallium Nitride IMD, IMR Intermodulation Distortion, Intermodulation Distortion Ratio IMD3 Third Order Intermodulation Distortion, LDMOS Laterally Diffused Metal-Oxide-Semiconductor MAG Maximum Available Gain MESFET Metal-Semiconductor FET MOCVD Metal-Organic Chemical Vapor Deposition MTA Microwave Transition Analyzer MWO Microwave Office OPEX Operational Expense OFDM Orthogonal Frequency Division Multiplex PA Power Amplifier PAE Power Added Efficiency PAR Peak-to-Average Ratio PEP Peak Envelope Power PM Phase Modulation PSD Power Spectral Density PSK Phase Shift Keying QAM Quadrature Amplitude Modulation SDD Symbolically Defined Device UMTS LTE Universal Mobile Telecommunications System, Long Term Evolution VNA,VSA Vector Network Analyzer, Vector Signal Analyzer W-CDMA Wideband Code Division Multiple Access WiMAX Worldwide Interoperability for Microwave Access

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Abstract Contemporary wireless communication systems including the 3rd generation (3G) universal mobile telecommunication system (UMTS) and the worldwide interoperability for microwave access (WiMAX) utilizes spectrum efficient modulation techniques. Such techniques, however, result in signals with broad modulation bandwidth and also high peak-to-average power ratio (PAR). To avoid signal clipping and spectral spreading such signals require linear amplification. This needs power amplifiers used in the RF front end to operate at large back-off power level. At this back-off level, however, the standard amplifier operates at low power efficiency. Hence, spectral efficiency could be achieved at the expense of power efficiency, which results in an elevated linearity-efficiency trade-off in the amplifier. Consequently, analysis, design and realization of highly linear amplifiers with sufficiently high efficiency at large power back-off level becomes more critical. This in particular is essential in the present 3G and future standards [for instance the long term evolution (LTE) of UMTS and 4th generation (4G)].

Although, there have been methods to improve the average efficiency of the amplifiers full utilization of these techniques has not yet been attained. This is due to the difficulty in implementation, availability of suitable power devices and lack of robust design methods. However, advances made in developing new power devices using wide bandgap semiconductor materials has resulted in devices with high power density, efficiency, and linearity at high frequencies. These devices are suitable for most efficiency enhancement techniques. Among these, the AlGaN/GaN HEMT is a suitable candidate for Doherty amplifier design.

Along with the availability of fast and vigorous computer aided design (CAD) tools, amplifier design activity could become increasingly faster and cost effective. This thesis deals with the linearity-efficiency trade-off through design and analysis of highly linear and efficient amplifiers (both at peak and back-off power levels) using AlGaN/GaN HEMTs. On the course of the amplifier design activity, a large-signal model will be derived

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in order to acquire a CAD tool. It is essential to develop an accurate large-signal model for a highly linear and efficient amplifier design process. Moreover, amplifier architectures such as the Doherty technique need operating conditions in the pinch-off and saturation region of the device I(V) characteristics. Hence, the large-signal model should predict all expected behavior of the device. Among others, modeling of GaN devices should include problems of current collapse.

Prior to design of high efficiency amplifiers, contemporary and essential aspects in the design of single stage amplifier will be investigated. Among others, methods to acquire optimum linearity of an amplifier through out-of-band distortion minimization at the circuit design level will be demonstrated. Single stage amplifier design techniques through harmonic tuning will also be explored as a possible solution to achieve high efficiency.

To tackle the critical problem of achieving high average efficiency at large-back-off, a concise analysis on the Doherty technique will be given. A practical design method through the use of uneven power splitting will be emphasized. Illustrative design of Doherty amplifiers will be provided with their performance in terms of output power, efficiency and linearity. Most importantly, tests include the use of complex dynamic communication signals to determine the performance in terms of adjacent channel power ratio and average efficiency.

It will be shown that in a first implementation, a 4W Doherty amplifier with 38.5% power added efficiency (PAE) with -37.5 dBc of adjacent channel power ratio (ACPR) at 8.5 dB back-off under a single-carrier W-CDMA signal has been designed. In a further implementation, a 7W Doherty amplifier with 47% PAE with -27 dBc of ACPR at 8.5 dB back-off has also been realized.

The achieved performance will indicate that the efficiency requirements of the basestation amplifier can be fulfilled utilizing the design guide lines provided in this thesis.

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Zusammenfassung Gegenwärtige drahtlose Kommunikationssysteme, insbesondere der dritten Generation (3G), wie das Universal Mobile Telecommunication System (UMTS) und das Worldwide Interoperability for Microwave Access (WiMAX), nutzen Modulationstechniken die zugewiesene Spektren effizient ausnutzen. Daraus resultieren große Modulationsbandbreiten und hohe Leistungsspitzen, sogenannte Peak-to-Average (PAR) Werte. Um Signalübersteuerung und damit spektrale Ausbreitung in Nachbarkanäle zu vermeiden, werden Verstärker in ihrer linearen Regionen betrieben. Um dies zu erreichen, müssen Leistungsverstärker in Basisstationen bei großem Back-off betrieben werden. Dies bedeutet jedoch, dass Standardverstärker bei geringer Leistungseffizienz betrieben werden müssen. Eine Ausnutzung der spektralen Bandbreite wird also durch Einbußen bei der Leistungseffizienz erkauft. Konsequenterweise wird bei Analyse, Design und Herstellung von Leistungsverstärkern besonderes Augenmerk auf ausreichend hohe Leistungseffizienz bei großem Back-off Betrieb gelegt. Dies gilt besonders für gegenwärtige Systeme der 3. Generation und kommende, zukünftige Standards [beispielsweise die Long Term Evolution (LTE) des UMTS Standards und Systeme der 4. Generation].

Obgleich Methoden existieren, die durchschnittliche Leistungseffizienz der Verstärker zu erhöhen, hat eine vollständige Ausnutzung dieser Methoden bisher nicht stattgefunden. Zu begründen ist das durch Schwierigkeiten bei der Implementierung, Verfügbarkeit geeigneter Leistungstransistoren sowie ein Mangel an etablierten Designverfahren. Erzielte Fortschritte bei der Entwicklung neuer Transistoren durch Verwendung von Materialien mit großen Bandabständen. brachten Transistoren mit hohen Leistungsdichten sowie hoher Effizienz und Linearität bei hohen Frequenzen hervor. Diese Bauteile eignen sich gut für die Entwicklung von Schaltungen mit gesteigerter Effizienz. Zu den beschriebenen Materialien zählt unter anderem der AlGaN/GaN HEMT, der sich besonders für die Integration in das Design eines Doherty Verstärkers eignet. Einhergehend mit der Verfügbarkeit von computergestützten Designwerkzeugen (CAD) konnte der Designprozess von Verstärkern extrem verkürzt und kosteneffizient gemacht werden. Unter Verwendung von AlGaN/GaN HEMTs untersucht

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die vorliegende Arbeit Möglichkeiten, Linearität und Effizienz von Verstärkern während des Designs und der Analyse sowohl bei Peak als auch bei Back-off Leistungswerten zu maximieren. Im Zuge der Designaktivitäten wurde ein Transistorgroßsignalmodell erstellt, das zum Einsatz in einem CAD Werkzeug kommt. Die Verfügbarkeit eines akkuraten Großsignalmodells ist für einen erfolgreichen Designprozess eines hochlinearen und hocheffizienten Verstärkers von entscheidender Bedeutung. Zudem benötigen fortschrittliche Verstärkerarchitekturen, wie die Doherty-Technik, Modelle, die auch in der Abschnür- und Sättigungsregion der Strom-Spannungs-Ausgangskennlinien (I(V) Charakteristiken) gültige Simulationswerte liefern. Somit sollten die im Designprozess verwendeten Modelle zuverlässige Vorhersagen aller Betriebseigenschaften treffen. Unter anderem sollte besonders das Problem der Stromverluste im Modell für GaN Bauteile berücksichtigt werden.

Zur Entwicklung hocheffizienter Verstärker werden übliche und wichtige Aspekte im Design einstufiger Verstärker herangezogen und genauer Untersucht. Um optimale Linearität zu erzielen, kommen Methoden zur Anwendung, die die Nebenbandverzerrung bereits auf der Entwurfsebene minimieren. Dabei werden Techniken zum Entwurf einstufiger Verstärker, wie das harmonische Abstimmen (harmonic tuning), als mögliche Lösungen zur Erlangung hoher Effizienz identifiziert.

Um das Problem hoher Durchschnittseffizienz bei großem Back-off angehen und identifizieren zu können, wird die Doherty Technik einer präzisen Untersuchung unterzogen. Ein Schwerpunkt des praktischen Entwurfs wurde auf die Verwendung ungleicher Leistungsteiler gelegt. Der Entwurfsprozess wird durch Tests des realen Verhaltens der Verstärker hinsichtlich Ausgangsleistung, Effizienz und Linearität gestützt. Die durchgeführten Tests beinhalten auch die Verwendung industrienaher, komplex modulierter Kommunikationssignale, um das Verhalten der Verstärker bezüglich Adjacent Channel Power Ratio (ACPR) und Durchschnittseffizienz unter realitätsnaher Umgebung zu untersuchen.

In einer ersten Ausführung konnte ein 4W Doherty Verstärker entwickelt werden, der unter Anregung eines Single-Carrier WCDMA Signals und bei 8.5% Back-off betrieben, 38.5% Power Added Efficiency (PAE) und -37.5 dBc ACPR liefert. In einer Implementierung konnte ein 7W Doherty Verstärker entwickelt werden, der im Betrieb 47% PAE und -27 dBc ACPR liefert.

xix

Die erzielten Ergebnisse belegen, dass bei Verfolgung der in dieser Arbeit vorgestellten Design Richtlinien die Effizienzanforderungen an Verstärker, die in Basisstationen zum Einsatz kommen, erfüllt werden können.

xx

Chapter 1

Introduction

In order to satisfy the increasing demand of mobile users, modern wireless communication systems are required to operate at high data rate. High data rate transmission requires a broadband modulation bandwidth, which in turn demands the use of spectrum efficient modulation techniques. Spectrum efficient modulation techniques including the phase shift keying (PSK) and quadrature amplitude modulations (QAM) are main techniques used in division access like wide-band code division multiple access (W-CDMA) and orthogonal frequency division multiple access (OFDMA) [1], [2]. Such techniques are broadband and at the same time have very high dynamic range (in terms of peak power to average ratio (PAR)) [3], [4].

Hence, transmitters in the basestations are required to manage these signals. This in particular requires power amplifiers (amplifiers) with high output power, high linearity, sufficiently high average efficiency and broad instantaneous bandwidth [5]. These multiple demands impose several challenges on the amplifier designer. Although tackling each demand independently, could overcome the challenges. The requirements are interrelated, which makes the design difficult to deal independently. This is specifically to mean that the design of a linear amplifier may not be achieved without compromising efficiency.

Among other requirements, the demand presented on the power amplifier to assure the highest average efficiency is critical. This is to maintain low DC power consumption within the signal dynamic range accounting for PAR characteristics of the signal to be amplified. Hence, design solutions are under intensive investigation to improve the average efficiency of the amplifier involved in the transmitter units [4]. A synopsis of identifying challenges in amplifier design will be provided in the next section.

1

1.1 Challenges in Power Amplifier Design

To fulfill system requirements of current mobile communications, power amplifiers with high output power, high linearity, broad (RF and envelope) bandwidth with higher average efficiency are required. For instance, the BTS in the UMTS standard requires W-CDMA modulation with 5 MHz bandwidth and adjacent channel power ratio of -45 dBc at the 5 MHz offset [6]. Moreover, the signal produces a PAR of 7 to 10 dB [3]. Moreover, higher PAR values are expected for future standards like LTE and 4G [2]. Hence, the basestation amplifier should be able to satisfy these stringent requirements.

The primary requirement in the basestation amplifier is to fulfill the linearity specification. To satisfy the linearity, the class-A or class-AB amplifiers are operated at a large back-off from the peak output power (due to the high PAR of the signal), which leads to operate at low average power and efficiency. Together with this, the linearity of the amplifier may have to be improved through additional linearization, since a single-stage amplifier may not satisfy the linearity requirement [3]. For the linearization method to be effective, the amplifier is also expected to have bandwidth independent linearity (i.e. minimum memory-effect [7]).

Consequently, the basestation amplifier should be designed to have high linearity, high output power, high average efficiency and broad bandwidth (both RF and envelope). To tackle the multiple challenges in the design, the following possible solutions could be proposed:

a) Basestation amplifiers with high output power (>100W) can be realized using new wide bandgap device technologies such as AlGaN/GaN HEMTs and SiC MESFETs. The AlGaN/GaN HEMT devices provide architectural benefits and unique features to produce high output power [8], [9]. Recent progress in the AlGaN/GaN HEMT fabrication has made it possible to reach power densities up to 30W/mm [10] with output power exceeding 300W [11], [12].

b) The linearity of the power amplifier could be improved through device and circuit level optimization as well as system level linearization. At the device level, the linearity can be optimized through improved device processes. For instance, through the use of field-plated HEMT structures in AlGaN/GaN [13], [14]. In this regard, the use of two-tone test signals to analyze the device properties in terms of minimizing intermodulation distortion (IMD) is a further possibility [15]. Circuit

2

level linearization can be implemented using techniques like derivative superposition [16]. At the system level, the already designed amplifier can be linearized using linearization techniques including feedback, feedforward and predistortion [17]. For this linearization techniques to be effective the amplifier should have bandwidth independent nonlinearity [17]. Hence, the instantaneous bandwidth of the amplifier should be increased through improved circuit design methods including the matching and bias circuits in the amplifier [18], [19].

c) High peak efficiency could be achieved using a single-stage design (for instance class-B), harmonic tuning and switched mode amplifiers [18]. However, these power amplifiers have either low average efficiency (if operated at large power back-off level) or high nonlinearity (if operated near the compression). Hence, the efficiency of these amplifiers should further be enhanced at back-off using enhancement techniques. In this regard, original techniques including the Doherty [20], the outphasing [21], envelope elimination and restoration (EER) [22], envelope tracking (ET) [23] and the class-S amplifier with ∆-Σ modulator [24], [25] are under reinvention and intensive investigation.

Hence, power amplifier design activity should consider all these aspects in order to satisfy requirements. Among the challenges, achieving sufficiently high PAE (>35%) at the 8.5 dB back-off will be tackled in this thesis. The next section provides a closer insight on the need for high average efficiency in basestation amplifiers.

1.2 Average Efficiency

High efficiency in the basestation power amplifier is required to reduce power consumption. Furthermore, inefficient amplifiers require extra cooling, which leads to the deterioration of the active semiconductor device reliability. This makes the amplifiers the most critical component in the transmitter’s final stage.

In the basestation the amplifiers consume a large portion of energy and, hence, every percentage increase in PAE translates into a percentage in power saving and into reducing cooling costs [26]. Thus, the amplifier should have efficiency as high as possible.

3

⎟⎟⎠

⎞⎜⎜⎝

⎛−=−= out

outoutDCloss P

PPPPη

(1.1)

where η is the efficiency in percent, is the dissipated DC power, is the output power and is the power loss in Watts.

DCP outP

lossP

0 20 40 60 80 1000

50

100

150

200

Efficiency (%)

Pow

er lo

ss (W

)

Figure 1.1 Power loss in a 10W amplifier as function of its efficiency.

Figure 1.1 shows the power loss calculated from (1.1) for a hypothetical 10W amplifier as a function of its efficiency. It can be noted that if the amplifier has a 20% efficiency it has a power loss of 40W, which is four times its output power. Hence, increasing the efficiency is an inevitable option in order to minimize the overall power loss and to save both operational expense (OPEX) and capital expenditure (CAPEX) [26].

Pow

er b

ack-

off (

dB)

0 20 40 60 80-40

-30

-20

-10

0

10

Efficiency (%) Figure 1.2 Efficiency of a class-B amplifier as a function of output power back-off.

The need for high efficiency is further determined by the PAR of the signal used in the system. A variable envelope signal with high PAR imposes the

4

amplifier to operate at back-off and hence lower efficiency. As illustrated in Figure 1.3, a single-stage amplifier driven under a variable envelope signal with a significant PAR requires a back-off operation. However, at this power level the amplifier operates at a reduced efficiency.

P (dBm)in

Pout

Pout, avg

η

Pin, avg

P(d

Bm

), PA

E (%

)ou

t

P1dB8.5 dB back-off

ηavg

Figure 1.3 Illustration of average efficiency in a single-stage amplifier driven with a variable envelope signal with 8.5 dB PAR [note that the 8.5 dB back-off is required from the 1 dB compression point (P1dB)].

This can be evidenced further from the efficiency of a single-stage class-B amplifier. The efficiency of a class-B amplifier only at its maximum output power and can be given as a function back-off as

p4100πη = (1.2)

where p is power back-off in Watts. The efficiency drops down as the input drive reduces as shown in Figure 1.2 for an ideal class-B amplifier as a function of power back-off [determined according to (1.2)] [18].

It can be seen that an ideal class-B amplifier with 78.6% efficiency at its maximum output power delivers only 25% at 10 dB back-off. A useful measure of performance is the average efficiency, which is defined as the ratio of the average output power to the average DC input power [3]:

5

DCavg

outavgavg P

P

,

,=η (1.3)

For an amplitude modulated (AM) signal, the average efficiency defined in (1.3) should be high and kept constant in the whole signal dynamic range. Methods to improve the efficiency at the back-off have been developed over the years to amplify AM signals. Along with other techniques, the Doherty amplifier design technique proposed in [20], has recently been reconsidered as front contender in the roadmap [26-28]. This is due to its relatively simple implementation and its advantages of resulting in efficiency improvement at back-off [29]. Consequently, several research efforts have recently focused on the Doherty amplifier solution, based on different power device technologies including GaAs MESFETs [30], Si LDMOS [31] and using emerging AlGaN/GaN HEMTs [32], [33]. Despite its relatively simple concept, the Doherty amplifier has not yet been commercially available [18]. This might have been due to problems in availability of proper device and also design repeatability. Hence, in order to utilize its simplicity and associated advantages, various implementation issues should be investigated. This thesis deals with efficiency enhancement of linear RF power amplifiers based on GaN technology and the Doherty principle.

1.3 Thesis Organization

The main objective of this thesis is to enhance the efficiency of linear AlGaN/GaN amplifiers for 3G mobile communication applications. Hence, various problems in high efficiency amplifier design will be addressed and attempted to be solved. In this regard, particular emphasis on the design of linear AlGaN/GaN amplifiers based on the Doherty technique will be provided. To accommodate the various aspects of the design procedure, the thesis is sectioned into six chapters. In Chapter 1, the objective of the thesis and the motivation to this research work has been described. The need for high efficiency not only at the peak power but also at high power back-off level has also been addressed.

In Chapter 2, brief explanation of the material properties of AlGaN/GaN HEMT for amplifier design will be given. This provides an insight into the advantages of AlGaN/GaN HEMTs and its fundamental characteristics for high power and linear amplifier design. Modern power amplifier design activity requires the use of CAD tools for cost effective design and

6

optimization. For this purpose, a non-linear model of GaN will be developed. The description of a large-signal table-based model of an AlGaN/GaN device will be incorporated in this chapter. The device modeling has been based on the work developed at the Department of High Frequency Engineering (HFT) [34]. The description includes the extraction of small- and large-signal model parameter and also validity assessment.

Fundamental concepts in the linearity and efficiency of single-stage amplifiers will be provided in Chapter 3. Basic amplifier class of operation including conventional (class-A, class-AB, class-B and class-C) and high efficiency (class-F) techniques will be reviewed. Contemporary problems in amplifier design, most importantly, memory-effects in amplifiers will be discussed. The need for efficiency enhancement techniques will also be highlighted in this chapter.

In Chapter 4, single-stage amplifier designs will be presented. Primarily, an amplifier design approach to attain optimum linearity of the amplifier through the design of input and output matching and bias network will be provided. The design aspects are illustrated through simulation, analysis and characterization of a 2W class-AB amplifier. In order to investigate the possibility of using class-F amplifier for a Doherty application, practical design consideration of harmonic tuned amplifiers will be investigated. A 3W class-F amplifier design with experimental performances will be provided.

In Chapter 5, the Doherty technique will be provided with the aim to achieve high average efficiency. A concise analysis together with practical implementation technique and practical issues will be given. In this regard, an uneven Doherty amplifier design technique will be emphasized as a feasible method of implementing the Doherty technique. Subsequently, a 4W uneven Doherty amplifier using GaN on Si has been realized and characterized. It will be shown that the amplifier achieves a PAE of 38.5% and an ACPR value of -37.5 dBc at 8.5 dB back-off under a single carrier W-CDMA excitation signal. In addition, a 7W uneven Doherty amplifier using GaN on SiC will be presented. A PAE value of 47% and -26 dBc ACPR has been measured at 8.5 dB back-off. At 10 dB back-off the PAE and ACPR reduced to 42% and -28 dBc, respectively.

Finally, summary of the research results and further works will be provided in Chapter 6.

7

Chapter 2

AlGaN/GaN HEMT Modeling

Highly linear and efficient RF power amplifiers are demanded in modern wireless communication basestations. The design of such high performance amplifiers in turn requires power devices with very high output power and thermal stability [35]. These requirements have already put tremendous constraints on currently available power devices such as Si LDMOS FET and GaAs MESFET [35]. Hence, new device technologies like the SiC MESFET and AlGaN/GaN HEMT are under rapid development as a current and future solution [35], [36]. Among these, AlGaN/GaN device produces the highest performance in terms of output power, gain and power efficiency. This device technology has emerged as a new contender in the market due to recent progress in research on material processing technologies [35].

A brief insight into the GaN material system, HEMT structure and its system level advantages will be given in the first section of this chapter. The subsequent goal is to use the AlGaN/GaN HEMT for amplifier design, which in turn requires characterization and modeling. Starting with a general overview on modeling techniques in Section 2.2 the derivation of small- and large-signal model of AlGaN/GaN HEMT will be provided in Section 2.3 and Section 2.4, respectively.

2.1 GaN Material Properties

The properties of the material system imposes a direct impact on the DC, small- and large-signal performance of the device. The most influencing properties of semiconductor are the energy bandgap, breakdown field, thermal conductivity, electron and hole transport properties, saturated

8

electron velocity and also the substrate conductivity [37]. The relation between material properties, device operation and figure of merit from the amplifier system performance point of view is given in Table 2.1.

Table 2.1 Semiconductor material property and features [37].

Material property Device property

Improved performance System advantages

High voltage

High breakdown field High doping

Power density, gain, efficiency and output impedance

Larger bandwidth, smaller number of dies and less energy usage

High thermal conductivity Wideband gap

High temperature

Small die size and more output power/die

Easier system cooling

High ftHigh electron velocity

High frequency High fmax

High system frequency

As given in Table 2.1, focusing on high power amplifier applications, desirable material properties for the active device includes a large energy gap, a high thermal conductivity and high breakdown field. At the same time high electron mobility is desired for high frequency operation. Hence, the primary objective in amplifier design is to select the proper device technology. A summary of the most important properties of common semiconductor materials for high power device applications is given in Table 2.2.

Table 2.2 Material properties of common semiconductors [37] - [39].

Property Si GaAs GaN 4H-SiC Bandgap (eV) 1.1 1.43 3.4 3.2 Breakdown field (V/cm) 7x105 7x105 35x105 35x105

Saturation velocity (cm/s) 1x107 1x107 1.5x107 2 x107

Saturation field (V/cm) 8x103 3x103 15x103 25x103

Thermal conductivity (W/cm-k) 1.5 0.46 1.7 4.9 Electron mobility (cm2/V-s) 1350 6000 1000 800 Hole mobility (cm2/V-s) 450 330 300 120 Dielectric constant 11.9 12.5 9.5 10

It can be seen in Table 2.2 that the material properties of SiC and GaN have favorable features for high power application. Specifically, GaN material has the required electronic properties that make it an ideal candidate for high power microwave devices [38-41]. The GaN material has an energy gap of 3.4 eV at room temperature, and also very high electric breakdown

9

field. This enables it to support peak internal electric fields. High electric field strength results in higher breakdown voltages. This is an essential attribute, which provides the high power density and high power handling capability. As a result, a GaN device can be biased at very high drain voltage (Vbr > 70V). Moreover, it can also operate at higher channel temperatures up to 300 oC. The GaN material system has also a high saturation electron velocity (2 x 107 cm/s), which contributes to higher current density [38]. The current density arises since the maximum current in a device is directly proportional to the product of the electron charge ( ), the sheet carrier density ( ) and the electron saturation velocity ( ). q sn sv

As a result of its high breakdown voltage and high power density, GaN devices have high input and high output impedance levels and low output capacitance [35]. High impedance levels and low output capacitance are essential for a highly linear and efficient amplifier since it provides a frequency independent broadband matching. A summary of the system level advantages of AlGaN/GaN HEMTs are mapped in Table 2.3.

Table 2.3 Architectural benefits of GaN device [42]. Amplifier architectures Device design GaN attribute Digital pre-distortion with class-AB amplifier

Reduced current High impedance low Q matching

High Voltage

EER with class-E/F amplifier

High ft, fmax High frequency

Low parasitic capacitance

High voltage High power density

Doherty architecture with class-F main amplifier

High ft, fmax High frequency Low parasitic capacitance

High voltage High power density

∆-Σ modulator architectures class-S amplifier High ft, fmax High frequency

High impedance low Q matching

High Voltage Multi-band amplifier with fixed matching

Low parasitic capacitance

High power density

Intensive research work on high efficiency AlGaN/GaN amplifier design based on various architectures has been performed recently. Thus, a class-F with 80% [43], Doherty with 76% [33] and envelope tracking with 50% efficiencies [44] have been realized.

GaN device can also operate at high frequencies, since the cutoff frequency is directly proportional to the saturation velocity. The electron velocity increases linearly with the electric field in the low field environments. As

10

the electric field increases, the electron velocity overshoots and then settles to a steady value. This is due to the presence of doping impurities and lattice vibrations, which scatter the electrons while traveling in the device channel [38]. This problem can partially be solved using a HEMT structure [38].

2.1.1 AlGaN/GaN HEMT

A general AlGaN/GaN HEMT structure is shown in Figure 2.1. The main advantage in the HEMT structure is that the scattering impurities are separated from the channel physically.

GateSource Drain

Substrate: SiC, Si or Sapphire

Nucleation layer GaN, AlGaN or AlN2DEG

AlGaN

Figure 2.1 Basic AlGaN/GaN HEMT structure (adopted from [38]).

In this configuration, Si doped AlGaN is grown on top of the GaN material. The AlGaN has an even higher energy gap than GaN. The Si impurities donate electrons to the crystal that tends to accumulate in the region of lowest potential (quantum well) beneath the AlGaN/GaN interface [38]. This forms a sheet of electrons, which constitutes the two dimensional electron gas (2-DEG). At the 2-DEG, the electrons have higher mobility since they are physically separated from the ionized Si donor atoms residing in the AlGaN. One of the unique properties of nitride based semiconductors is the existence of a strong polarization field within the crystal, which has profound impact on the electronic properties of GaN based heterostructures [45].

The formation of 2-DEG in AlGaN/GaN heterostructure is different from that in the AlGaAs/GaAs system due to the existence of a polarization field across the AlGaN/GaN heterojunction. A 2-DEG with the density up to 1013

cm-2

can be achieved in the AlGaN/GaN heterostructure without any

doping [45]. The modulation doping in AlGaN barrier layer contributes to the formation of 2-DEG.

11

Theoretical and experimental studies of the formation of the 2-DEG in an AlGaN/GaN heterostructure revealed that surface states act as source of the electrons in the 2-DEG [46]. The built-in static electric field in the AlGaN layer induced by spontaneous and piezoelectric polarization alters the band diagram and the electron distribution of the AlGaN/GaN heterostructure. Thus, considerable amount of electrons transfer from the surface states to the AlGaN/GaN heterointerface, leading to a 2-DEG with a density up to 1013

cm-2

[45].

In addition to this property, the substrate used in a HEMT structure is an important factor regarding RF performance and cost of fabrication. Currently, AlGaN/GaN HEMT can be grown on SiC, sapphire or Si substrates. The foremost choice is SiC due to its superior thermal conductivity. The SiC substrate is expensive, which makes it difficult to grow in large wafer size for mass production [47].

The use of Si as a substrate has become cost effective and suitable for mass production as reported recently in [47]. The advantages of Si substrate as compared to SiC or sapphire include lower wafer cost, availability in larger wafer size and better thermal conductivity than sapphire. However, it has less resistivity and could introduce large lattice and thermal expansion mismatch to the GaN [47].

AlGaN

GaN

Si

Transition layer

GaN

Source Gate Drain

High resisitvity substrate(10,000 )Ω

Stress mitigating transition layer

Semi insulating GaN layer (0.8 m)µ

(n = 0.8x10 /cms 13 2)2DEG ( = 1,500 cmµs 2/V-s)

Barrier of composition -x (26% Al)and thickness - d (180A)

Cap layer (15A)

Figure 2.2 AlGaN/GaN HEMT on Si (adopted from [48]).

The significant thermal expansion and crystalline structural mismatches between Si and GaN induce substantial levels of tension in the GaN-Si interface. The key challenge to manufacture AlGaN/GaN HEMTs on Si, to

12

grow an interface material between the GaN and Si. The interface material must be capable of absorbing and dissipating this tension [47]. Figure 2.2 shows an AlGaN/GaN HEMT structure on Si. The recent advancement in process technology has, for instance, resulted in a 36 mm AlGaN/GaN HEMT on Si substrate, producing pulsed RF output power of 368W (at drain bias of 60V), maximum drain efficiency of 70% and 17.5 dB small-signal gain [49]. This high RF performance AlGaN/GaN HEMTs on Si started to become available commercially. In this thesis, AlGaN/GaN devices on Si will be used for the design of single-stage (class-AB and class-F) and Doherty amplifiers.

2.1.2 Performance Limiting Factors

Despite its excellent material properties, the AlGaN/GaN HEMT posses some imperfections, which usually limit its performance. This includes trapping effect, self heating and current collapse in the HEMT device. The trap states refer to the deep level states in the bandgap, resulting in a delay of frequency response. The traps also induce power loss. These traps may appear on the AlGaN surface, in the AlGaN barrier layer, at the AlGaN/GaN heterointerface, or in the GaN buffer layer [50].

The presence of the trap states in AlGaN/GaN HEMTs causes voltage delay in the device operation through the trapping and de-trapping process. This can further degrade the power handling capability [50]. The surface of the crystal interrupts the perfect periodicity of the crystal lattice. These states exist at the crystal surface and can be of two types, the intrinsic surface states and the extrinsic surface states. The term intrinsic refers that such states could also exist in an ideally perfect surface [50].

The extrinsic surface states are caused by defects or impurities at the surface formed during crystal growth or in subsequent device fabrication process. Similar to the surface states, interruption of the periodicity of the crystal lattice at the hetero-interface forms interface states. Interface states, can also be induced by interface roughness and compositional non-uniformities.

Due to the lack of a suitable GaN substrate, GaN is usually grown on sapphire or SiC with large lattice mismatch. Consequently, AlGaN/GaN layers grown on this substrates are imperfect crystals with dislocations, impurities, and defects in the material [50]. These defects may cause the

13

formation of deep level trap states within the GaN and AlGaN layer. These trap states are usually deep below the conduction band edge and have time constants as large as milliseconds [51].

The main consequence of these trapping effects is the current collapse in AlGaN/GaN HEMT. The current collapse phenomena occurs at large-signal operation, where the operating point of the device is swept across the I(V) characteristic [51]. Enormous research effort is going in order to fully identify the causes and possible remedies of current collapse. Current collapses can be reduced by surface passivation using Si3N4, employing a recess gate structure and by the use of a field plate [52], [53]. From amplifier circuit design point of view, these performance limiting factors should be predicted in the large-signal model of the device.

2.2 Device Modeling Approaches

Power amplifier design and optimization activities are mainly based either on load-pull measurements or through nonlinear simulation. The latter approach requires an accurate large-signal model and is the preferred method due to its convenience and cost effectiveness [54]. Hence, a large-signal model should be derived for an AlGaN/GaN HEMT device prior to amplifier design activity.

There are mainly two device modeling approaches, which are termed physical and empirical modeling. The physical modeling approach relies on physics-based parameters and technology of device, while the empirical modeling approach is based on measured characteristics that describe the behavior of the device. In the physical modeling approach, the device performance is predicted from physical data describing the device [55]. This data include carrier transport properties, material characteristics and device geometry. The main advantage of this approach is that it describes the device operation in terms of the device physics. Therefore, it is more applicable for device designers.

Empirical (measurement based) models use characterization techniques such as S-parameters and pulsed I(V) data. These techniques are the most common one for amplifier design activity. These techniques provide large-signal simulation accuracy since the model elements are constructed from measurements that emulate actual device application. Empirical models can be of two types, the analytical or table based one. Analytical models use

14

equations for the description of measured data [56], [57]. Table-based models use lookup tables developed from the measured data [58-63].

The model implementation using analytical functions are fast. However, it can also be difficult to find functions that fit globally the nonlinear device model parameters over large voltage ranges. This is the case, for example, for GaN HEMTs with operating drain voltages of 50V or more [63]. The technique might also be technology dependent and the fitting parameters might not have physical meaning [62]. The main advantages of the analytical models include computational efficiency, automatic data smoothing, simplicity, and ability to deliver simulation results outside the measurement range [62].

In table-based models, instead of using mathematical expressions, multidimensional spline functions are used to fit the measured data. This procedure needs only fitting coefficients to be stored. Therefore, they are more accurate than the analytical models and are suitable for applications, where the functional form of the behavior is unknown. The physical reliability of the models can be improved using an equivalent circuit that can fit the device physics. Data smoothing can be improved in these models by using spline functions that can maintain the continuity of the measured data. Based on this approach, differentiable current and charge sources can be modeled. This in turn enables to predict harmonics and linearity accurately. Early research works have also shown the accuracy of this technique for linearity prediction [61]. Moreover, dispersive drain current models based on pulsed I(V) measurements are best implemented using lookup tables as described in [61]. Table-based models can be implemented in different commercial CAD tools. For instance, with Agilent’s Advanced Design System (ADS) using symbolically defined devices (SDD) and with AWR’s Microwave Office (MWO) using model wizard in the form of dynamically linked models. Consequently, model implementation issues are not fundamental problems of a table-based modeling approach.

Therefore, this approach adopted from the long experience of the department of high frequency engineering (HFT) [34], [62] will be used for this research work. The general procedure of deriving the table based large-signal modeling approach to GaN devices described in [34] can be outlined as shown in Figure 2.3.

15

Cold pinch- off and forward

V and V sweep

GS DS

CW S-Parameter Pulsed I(V) Large-SignalCold, cold pinch-off

and P pointsdiss CW, two-tone,

W-CDMA and load-pull

Extrinsic parameter(linear data fitting and optimization)

Intrinsic parameter(linear data fitting)

Large-signalmodel verification

Large-signalmodel implementation

Small-signal model verification

Dispersive drain current model

Charge-source model

Figure 2.3 Large-signal table based model derivation process.

The first step in the large-signal modeling procedure is the accurate measurement of the GaN HEMT. To extract reliable and physically meaningful extrinsic and intrinsic elements of the small-signal equivalent circuit model, very accurate multi-bias S-parameter measurements are required.

The large-signal model is mainly composed of five nonlinear elements, two gate currents (Igd and Igs), two charge sources (Qgs and Qgd) and the drain current (Ids). The charge sources can be generated from the intrinsic capacitance surfaces through integration. The drain current model is derived from a set of pulsed I(V) measurements. The complete large-signal model will then be implemented in commercial CAD tool mainly in ADS to be used for amplifier design. The model will be experimentally verified under single-tone and two-tone excitations in a 50Ω environment. Following this procedure, a large-signal model will be developed for a 2-mm (10 x 200 µm) AlGaN/GaN HEMT chip on Si obtained from Nitronex Inc (its die photo shown in Figure 2.4). The next section deal with small-signal modeling followed by large-signal modeling in Section 2.4.

16

Gate Drain

Source

Gate fingers Figure 2.4 Photo of the investigated 2-mm (10 x 200 µm) AlGaN/GaN on Si HEMT [the device is fabricated by Nitronex Inc. (photo adopted from [64])].

2.3 Small-Signal Modeling

The primary step in small-signal modeling of a device is to define an adequate equivalent circuit. This equivalent circuit should reflect the physical properties of the device technology. A 22-element distributed model topology shown in Figure 2.5 has been adopted to model the AlGaN/GaN HEMT on Si device. This model topology was proposed in [34] to model AlGaN/GaN devices on SiC. It takes into account all expected parasitic elements of the device. Moreover, this model is scalable and the topology is convenient for large-signal model derivation [34].

Intrinsic FET

Cgda

Cgdi

GgdfRgd

CgdCgs

Ri

Vi

Ggsf

Rg RdLg Ld

Rs

Ls

CpgaCpgi

CpdaCpdi

Cds

GdsIds

SS

G D

I = V G eds i m-jωτ

Vds

VDS

dg

s

VGS

Vgs

Figure 2.5 A 22-element distributed model for a GaN HEMT(adopted from [34]).

The equivalent circuit depicted in Figure 2.5 consists of 12 extrinsic parameters and 10 intrinsic parameters. Inter-electrode and crossover

17

capacitances (due to air-bridge source connections) between gate, source, and drain are taken into account with Cpgi, Cpdi, and Cgdi. Parasitic elements due to the pad connections, measurement equipment probes, and probe tip-to-device contact transitions are represented with Cpga, Cpda, and Cgda. The parasitic resistances (Rg, Rd, and Rs) and inductances (Lg, Ls and Ld) at the gate, source and drain contacts have also been incorporated.

To model the lossy Si-substrate, in some cases, a transversal RC network instead of pure capacitances have been proposed [65], [66]. However, these RC networks are not required if the conductivity of the Si is higher than 10 kΩ-cm [67]. The substrate for the device shown in Figure 2.2 posses this conductivity and, hence, the equivalent circuit without RC networks has been adopted.

2.3.1 Extrinsic Parameter Extraction

Extrinsic parameter extraction is a vital step in the small-signal modeling process. Extrinsic parameters are generally extracted from a set of S-parameter measurements performed under cold FET condition. The parameters can be extracted analytically [68] or through optimization [69-71]. The analytical method is fast but the sequentially derived solutions of circuit parameters may have less accuracy [62]. In the optimization method an error function is minimized by fitting the calculated S-parameters to measured ones. The starting value for the optimization is obtained from both gate-forward and cold pinch-off S-parameters. In order to exclude the local minimum problem during optimization, multi-plane data fitting and bi-directional search technique have been used [71]. This technique has been proved to be a reliable method of extraction [63].

The starting parameters for optimization are generated from two sets of S-parameter measurements. The S-parameter must be measured for an optimal frequency range. An optimal upper frequency of 15 GHz is determined (using the graph provided in Chapter 4 of [34]) to be sufficient to extract the parameters for a 2-mm GaN device. Hence, S-parameters have been measured up to 18 GHz (to cover an even wider frequency range).

Two sets of measurement are taken at two cold FET (VDS0 = 0) bias conditions. First one, taken at a reverse gate bias voltage below pinch-off (VDS0 = 0, VGS0 < Vp), is used to extract the parasitic capacitances and

18

inductances. Second one, with gate forward (VDS0 = 0, VGS0 > 0), is used to extract the parasitic series resistances. The extraction procedure is described in [71]. It can be summarized as follows:

1. The S-parameter measurements at cold pinch-off will first be converted to Y-parameters. The total branch capacitances (gate-source, gate-drain and drain-source) can be estimated from the imaginary parts of these Y-parameters in the low-frequency range (from 100 MHz to 3 GHz for the investigated 2-mm device).

2. Three different capacitances are considered in each branch, the best partitions of the total branch capacitances are searched by scanning different distributions. For each iteration:

a) Capacitances are distributed for the iteration. The extrinsic capacitances are removed from measurements and converted to Z-parameters.

b) The parasitic inductances can be estimated from the Z- parameters at higher frequencies (> 3 GHz). Estimated values of the extrinsic inductances are used to remove all the reactive extrinsic elements from the cold pinch-off measurements. The results are then converted to Z-parameters.

c) Extrinsic resistances are estimated from these Z-parameters (without parasitic reactances). At this point, all extrinsic elements are estimated and can be de-embedded from the measured S-parameter. This leads to the intrinsic transistor Y-parameters, and, thus, the intrinsic elements of the model can be determined.

d) After all elements of the cold pinch-off model have been estimated, the corresponding S-parameters can be reconstructed to evaluate the error function.

3. Now, the best capacitance distribution, which corresponds to the lowest error of all iterations, and the best initial values for the extrinsic capacitances and inductances can be determined.

4. All extrinsic reactive elements are then detached from the measurement on cold-forward. The result is then converted to Z-parameters to extract the best initial values for the extrinsic resistances.

5. At this point, the best initial values for all the extrinsic elements of the model have been estimated. These are delivered to the optimization routine, which produces the final values.

19

The starting parameter values for the 22-element model using pinch-off S-parameter measurements for the capacitance and cold-forward measurements for the resistance are given in Table 2.4.

Table 2.4 Starting parameter values of a 2-mm AlGaN/GaN HEMT with a 10 x 200 µm gate width derived from measurement (pinch-off and forward).

Extrinsic Parameters Intrinsic Parameters

Cpga = 154 fF Cpda = 154 fF Cgda = 0.0 fF Cpdi = 462 fF Cpgi = 469 fF Cgdi = 0 fF

Lg = 42.4 pH Ld = 89.25 pH Ls = 10.4 pH Rg = 1.61 Ω Rd = 1.35 Ω Rs = 0.88 Ω

Cgs = 887.85 fF Cds = 73.0 fF Cgd = 968.29 fF Ri = 0.0 Ω Rgd = 0.0 Ω τ = 0.0 ps

Gm = 0.0 mS Gds = 3.20 mS Ggsf = 0.3 mS Ggdf = 0.00 mS

The optimized parameter values for 22-element model using cold pinch-off and cold-forward (for the extraction of the parasitic resistances) S-parameter measurements are given in Table 2.5.

Table 2.5 Optimized parameter values of a 2-mm AlGaN/GaN HEMT with a 10 x 200 µm gate width.

Extrinsic Parameters Intrinsic Parameters

Cpga = 161.9 fF Cpda = 169.77 fF Cgda = 0.0 fF Cpdi = 522.052 fF Cpgi = 435.088 fF Cgdi = 0 fF

Lg = 41.3 pH Ld = 97 pH Ls = 10.4 pH Rg = 1.52 Ω Rd = 1.97 Ω Rs = 0.94 Ω

Cgs = 1891.85 fF Cds = 37.0 fF Cgd = 849.29 fF Ri = 0.0 Ω Rgd = 0.0 Ω τ = 0.0 ps

Gm = 0.0 mS Gds = 3.28 mS Ggsf = 0.33 mS Ggdf = 0.0142 mS

Extracted source inductance Ls is smaller than Lg and Ld. Moreover, no negative values have been delivered by the algorithm, which verifies that sufficient measurement frequency range has been considered. Regarding the resistances, it can be observed that the optimized values are not far from the starting values (obtained from cold forward S-parameter data). This emphasizes the reliability of the approach on cold forward measurement to obtain starting values for the parasitic series resistances. Figure 2.6 shows the comparison of simulated and measured S-parameters taken below pinch-off (used for the extraction of the capacitances and inductances). Good agreement between simulation and measurement can be observed. However, regarding the magnitude of S22 at very low frequencies, the model does not follow the measurement properly. It is due

20

to the external bias-T, used at the drain side (instead of the internal one within the VNA). The external bias tee used during S-parameter measurement has minimum frequency range of 0.5 GHz. Although the bias tee is included in the system calibration, it can still present an impedance different from 50Ω outside its specified frequency range. Hence, the first few measurement points are unreliable.

2 4 6 8 10 12 14 160 18

0.20.40.60.8

0.0

1.0

Frequency (GHz)

Mag

nitu

de S11

S21

2 4 6 8 10 12 14 160 18

0.20.40.60.8

0.0

1.0

Frequency (GHz)M

agni

tude S22

S12

(a) (b)

2 4 6 8 10 12 14 160 18 2 4 6 8 10 12 14 160 18

-150-100-50

0

-200

50

Frequency (GHz)

S12

S22-150-100-50

0

-200

50

Frequency (GHz)

Phas

e (d

egre

e) S21

S11

(c) (d)

Figure 2.6 Pinch-off S-parameter fitting with optimized element values of the 22-element equivalent circuit model for a 2-mm AlGaN/GaN HEMT obtain from Nitronex Inc. with a 10 x 200 µm gate width [measurement (symbols) and simulation (lines)].

2.3.2 Intrinsic Parameter Extraction

After the extrinsic parameters have been de-embedded from the small-signal equivalent circuit, the bias dependent intrinsic FET parameters can be extracted. These parameters can also be extracted either from a closed form analytical equation or from a linear data fitting [71]. The linear data fitting technique is used to determine the intrinsic element values, if the elements are frequency dependent [34]. The intrinsic parameters can be determined from the intrinsic Y-parameters given in (2.1a) - (2.1d) through linear data fitting techniques following the procedure in [34]. The extracted bias dependent parameters as function of intrinsic drain and gate voltages are shown in Figure 2.7. 21

gsigsfi

gsgsfiigs CRjGR

CjGYYY

1

12,11, ω

ω

++

+=+= (2.1a)

gdgdgdfgd

gdgdfigd CRjGR

CjGYY

1

12, ω

ω

++

+=−= (2.1b)

gsgsfi

jm

iigm CjGReG

YYYω

ωτ

++=−=

−

112,21, (2.1c)

dsdsiids CjGYYY 12,22, ω+=+= (2.1d)

The gate source capacitance Cgs [shown in Figure 2.7(a)] is formed by the gate metal and the 2-DEG channel charge. With the gate voltage Vgs = 0V, Cgs decreases in the pinch-off region (Vgs ≤ -1.5V) and gradually increases with increasing drain voltage. This is due to the lateral electric field established by the drain voltage, which accelerates charge carriers in the channel to scatter into the barrier layer.

010

2030

40

-4

-2

0

202468

Vds (V)Vgs (V)

Cgs

(pF)

0

1020

3040

-4-2

020

0.5

1

1.5

2

Vds (V) Vgs (V)

Cgd

(pF)

(a) (b)

010

2030

40

-4

-2

0

20

200

400

600

Gm

(mS)

Vgs (V)Vds (V)

0

1020

3040

-4-2

020

2

4

6

Vds (V)Vgs (V)

Cds

(pF)

(c) (d)

Figure 2.7 Extracted Cgs, Gm, Cgd and Cds as a function of the intrinsic voltages for a 2- mm AlGaN/GaN HEMT on Si.

22

The drain gate capacitance Cgd [shown in Figure 2.7(b)] is formed due to the extension of the depletion region into the gate-drain space. Smaller values of Cgd are observed with increasing drain voltage since the extension of depletion increases with increasing drain voltage. The transconductance Gm is controlled by both the drain and gate voltage, and it is physically related to the channel charge density and electron velocity. Hence, an increase in Gm can be seen in Figure 2.7(c) with increasing gate voltage. It also increases linearly with increasing drain voltage in the ohmic region (Vds < 3V) as the electron velocity varies linearly with electric field strength at lower intensity. In the saturation region (Vds > 3V), Gm becomes constant as the electron velocity saturates at higher channel electric field.

The drain source capacitance is shown Figure 2.7(d). The physical origin of Cds can be attributed to the high-field part of the depletion layer, which separates the source and drain electrodes in an electrostatic sense. Hence, higher values for Cds will be obtained in the ohmic region due to the reduction of the high-field part, as can be seen in Figure 2.7(d). The remaining bias dependent parameters are also shown in Figure 2.8. The variation of the drain current with the drain voltage is modeled by the output conductance Gds. Hence, as shown in Figure 2.8(a), negligible value of Gds in the saturation region can be seen, where the drain current is nearly constant. The channel resistance or the charging resistance Ri [shown in Figure 2.8(b)] models the low field region of the channel under the gate where the gate source capacitance Cgs is charged.

The transit time of electrons in the channel under the depletion region is modeled by τ. Therefore, τ is expected to increase with increasing drain voltage or decreasing gate voltage. This is not, however, visible in Figure 2.8(c) since the value in the ohmic region is larger than the saturation region. The conduction current through the gate-source and gate-drain Schottky diodes are modeled by the conductances Ggsf and Ggdf, as shown in Figure 2.8(d) and Figure 2.8(e), respectively. As can be seen from Figure 2.8(d) Ggsf shows a jump from the saturation region to gate forward region, which is attributed to turn on of the diode. Hence, their value should increase with Vgs beyond the diodes turn on voltage (Vgs ≈ 1.1V). The charging resistance Rgd has been used to model the symmetrical distribution of the depletion region under the gate in the ohmic-forward region (Vds < 3V and Vgs > 0V). Rgd is expected to have similar behavior as Ri in this region, as shown in Figure 2.8(f).

23

010

2030

40

-4-2

020

500

1000

1500

2000

Vds (V)Vgs (V)

Gds

(mS)

0

1020

3040

-4-2

020

5

10

15

Vds (V) Vgs (V)

Ri (

Ω)

(a) (b)

010

2030

40

-4-2

020

100

200

300

400

Vds (V)Vgs(V)

τ (ps

)

0

1020

3040

-4-2

020

0.2

0.4

0.6

0.8

Vds (V)Vgs (V)

Ggd

f (m

S)

(c) (d)

010

2030

40

-4-2

020

0.2

0.4

0.6

0.8

Vds (V) Vgs (V)

Ggs

f (m

S)

0

1020

3040

-4-2

020

50

100

150

Vds (V)Vgs (V)

Rgd

(Ω)

(e) (f)

Figure 2.8 Extracted Gds, Ri, τ, Ggdf, Ggsf and Rgd as a function of the intrinsic voltages for a 2-mm AlGaN/GaN HEMT on Si with a 10 x 200 µm gate width.

During the extraction procedure, the surfaces have been extrapolated to higher Vgs and Vds areas outside the measured data range. The extrapolation may lead to a larger value. This can be seen, for instance, in case of Ri where a high value is observed. The extrapolated data is within the high power dissipation (outside the normal operating region of the device).

24

However, it can be removed to observe the normal shapes of the surfaces (for instance shown in Figure 2.9 for Cgs).

010

2030

40

-4

-2

0

20

5

10

Vds (V) Vgs (V)

Cgs

(pF)

Figure 2.9 Extracted Cgs as a function of the intrinsic voltages for a 2-mm AlGaN/GaN HEMT on Si.

0 5 10 15 200.2

0.4

0.6