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Eric RUTTEN , INRIA Grenoble, Ctrl-A team Autonomic Management of Reconfigurations in DPR FPGA, and towards integration in Data-Centers
Eric RUTTEN , INRIA Grenoble, Ctrl-A team
Autonomic Management of Reconfigurations in DPR FPGA, and towards integration in Data-Centers
Outline
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Autonomic Computing : self-reconfiguration
controlled by feedback loops
this work : Dynamically Partially Reconfigurable
Embedded FPGA : automata-based control
this workshop : Integrating HPC and FPGAs :
exploit DPR ?
Decision
Representation
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Automated administration & regulation in reaction to variations in load, resources,… in large (Big Data) or embedded (IoT) systems
self-*: deploy, mgmt, healing, protection promising, but challenge in developing systems need for automation & separation of concerns
Understand and design control for
problems in efficiency (e.g; energy) & assurances (e.g.crash avoidance)
Ctrl-A : for Autonomic Computing
Strategy/Policy
Eolas, Grenoble
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Feedback loops are the object of Control Theory research
sensors, actuators, objective, decision, pace
Application to Self-adaptive, flexible, reconfigurable, …
Computing systems (HW, SW) still relatively recent
perception (sensors)
action (actuators)
decision (control)
system (process)
Control for Autonomic Computing
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HPC on Dynamically Partially Reconfigurable FPGA
Controlling choices in combinatorial space [ICAC13, ACM TECS16]
Application graph ANR FAmous
par., cond. & seq. branches
Tasks versions Size, WCET, power, QoS
Architecture sleep modes, DVFS, …
Policies power peak, QoS, surface
e.g., Autonomic Computing on FPGA
ctrlr
ctrlr
Soguy GUEYE & Eric RUTTEN , INRIA Grenoble, Ctrl-A team & Jean-Philippe DIGUET, LabSticc, Lorient
Autonomic Management of Reconfigurations in DPR FPGA-based Embedded System
Drone-embedded FPGA
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typical application : video stream processing
DPR FPGA motivation : more HW implementations on same HW
Réalisation d’un système électronique embarquémulti-capteurs sur drone pour l’évitement
d’obstacle
Lieu : Laboratoire Lab-STICC (Lorient)
Contexte
Les drones sont de plus en plus utilisés dans des domaines diverses tel que l’agriculture, lesmédias, la cartographie, l’inspection d’ouvrage, la sécurité, etc… Actuellement, les drones sontsurtout pilotés à distance, mais le but du projet est de réaliser un drone autonome. Pour ce faire, ledrone a besoin de connaître son environnement et cela nécessite l’installation de nombreuxcapteurs. Les informations des capteurs sont récupérées par une plateforme composée d’une carted’auto-pilotage Pixhawk (partie reptilien du cerveau du drone: asservissement en vitesse/position,etc), d’une carte à base de cyclone 5 d’Altera composé de deux processeurs ARM-9 et d’une partielogique programmable (partie neo-cortex du cerveau du drone : prise de décision en fonction desdifférents capteurs).
Objectif
Dans un premier temps, l’objectif de ce projet vise à établir la communication entre lescapteurs (12 capteurs infra-rouge et 6 capteurs à ultra-son) et la plateforme Linux embarquéeutilisant ROS. Les cartes des capteurs sont données ainsi qu’une carte de développement SoC(System-On-Chip) dont le Linux est configuré dessus.
Une fois la prise en main de ce matériel terminée, l’objectif principal du projet consistera àaméliorer la vitesse d’acquisition des données de capteurs fonctionnant en I2C via l’utilisation desinterruptions de l’ADC (Analog-Digital Converter).
D’autres objectifs seront proposés selon la progression du projet.
Illustration 1: prototype du drone HPeC
Introduction Control Architecture Designing Reconfiguration Layer Design Methodology Case Study Conclusion
Layered Control Architecture
We propose a control architecture structured in three layers
S. M.K GUEYE INRIA
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Case Study Managing Search landing area task
Control
DE1-Soc FPGA system
HPS : Dual-core ARM(ROS/Linux OS)
Self-adaptation managerSoftware version of the task
FPGA : one tileHardware version of the task
The control objective consists in maintaining the execution time of the taskbetween a minimum threshold and a maximum threshold.
S. M.K GUEYE (INRIA)25/34
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Context-aware DPR control
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DPR FPGA
DPR ctrlr
end metrics
what : tasks/ops
how: QoS reqs
notifications metrics
reconfiguration management & control : insuring : for task/operation, choice of good enough bitsream version,
w.r.t. given requirements, following measured metrics
notifying : metrics, … in case of impossibility,
to be managed at upper level by tasks or reqs change
bitstreams ids on/off
(DPR) FPGA in Data Centers
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motivations : performance for new workloads AI, Data analytics, machine learning, security, SDN Cloud µservices (e.g. Nokia/Bell labs) , …
acceleration , energy consumption FPGA in server nodes, as parallel shared resource
6 Pictures from Maxeler
thru D. Koch (FPT’18)
(DPR) FPGA in Data Centers
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problems : programming support to produce bitstreams security (e.g.leakage) isolation of communication
approaches: networks of FPGAs
multiple FPGAs, multiple applications virtualization, « resource elastic » [Koch]
set of bitstreams : fixed : standard operations dynamic : user/application defined/compiled
FPGA Control in Data Centers
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reconfiguration management & control : integrated in
global scheduling and mapping
but large and complex sheduling problem
autonomic management
Picture from K. Yoshii (FPT’18)
FPGA Control in Data Centers
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reconfiguration management & control : hierarchical : e.g. reusing our proposal
local DPR control(s) on FPGA card
coordinated with global application-level
manager(s)
DPR FPGA
DPR ctrlr
end metrics
what : tasks/ops
how: QoS reqs
notifications metrics
bitstreams ids on/off
application(s) application(s)
DPR FPGA server + CPU
higher-level mgr
DPR FPGA
DPR ctrlr
end metrics
what : tasks/ops
how: QoS reqs
notifications metrics
bitstreams ids on/off
DPR FPGA
DPR ctrlr
end metrics
what : tasks/ops
how: QoS reqs
notifications metrics
bitstreams ids on/off
. . .
. . .
e.g., control of parallelism
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reconfiguration management & control : hierarchical :
e.g. reusing our proposal
local DPR control on FPGA card
coordinated with global application-level manager(s)
DPR FPGA
DPR ctrlr
end metrics
what : tasks/ops
how: QoS reqs
notifications metrics
bitstreams ids on/off
DPR FPGA server
higher-level mgr :degree of
parallelism
req measures of perf.
. . .
. . . . . .
e.g., control of parallelism
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reconfiguration management & control : hierarchical :
e.g. reusing our proposal
local DPR control on FPGA card
coordinated with global application-level manager(s)
DPR FPGA
DPR ctrlr
end metrics
what : tasks/ops
how: QoS reqs
notifications metrics
bitstreams ids on/off
DPR FPGA server
higher-level mgr :degree of
parallelism
req measures of perf.
. . .
. . . . . .
