1

BASIC VHDL LANGUAGE ELEMENTS

Digital Design for Instrumentation with

VHDL

2

BASIC VHDL LANGUAGE ELEMENTS

1. Comments2. Identifiers3. Data Objects4. Data Types5. VHDL Operators6. VDHL Design Entity

3

BASIC VHDL LANGUAGE ELEMENTS

1. Comments2. Identifiers3. Data Objects4. Data Types5. VHDL Operators6. VDHL Design Entity

4

1. Comments

Comments are preceded by two consecutive hyphens (--) and are terminated at the end of the line.

Example:

-- This is a comment

5

BASIC VHDL LANGUAGE ELEMENTS

1. Comments2. Identifiers3. Data Objects4. Data Types5. VHDL Operators6. VDHL Design Entity

6

2.Identifiers

VHDL identifier syntax: A sequence of one or more uppercase letters,

lowercase letters, digits, and the underscore. Upper and lowercase letters are treated the

same (i.e., case insensitive). The first character must be a letter. The last character cannot be the underscore Two underscores cannot be together. Identifier values and numbers:

1. Individual logic signals ‘0’, ‘1’2. Multiple logic signal “01110”

7

BASIC VHDL LANGUAGE ELEMENTS

1. Comments2. Identifiers3. Data Objects4. Data Types5. VHDL Operators6. VDHL Design Entity

8

3. Data Objects

There are three kinds of data objects: SIGNALs, VARIABLEs, and CONSTANTs.

3.1 SIGNAL Data Objects3.2 VARIABLE Data Objects3.3 CONSTANT Data Objects

9

3.1 SIGNAL Data Objects

SIGNAL data objects represent logic signals on a wire in the circuit.

SIGNALs are used for communication between components.

A signal does not have memory; thus, if the source of the signal is removed, the signal will not have a value.

There are three places in which SIGNALs can be declared in VHDL code:

1. ENTITY declaration.2. Declarative part of ARCHITECTURE.3. Declarative part of PACKAGE.

CONT………..

10

3.1 SIGNAL Data Objects

General form of SIGNAL declaration:

SIGNAL signal_name, signal_name, .…….. : type name;

11

3.2 VARIABLE Data Objects

A VARIABLE; unlike SIGNAL; does not represent a signal on a wire in the circuit.

VARIABLE data objects are sometimes used to hold results of computation and for index variables in the loops.

VARIABLES can be declared only inside the declarative part of PROCESS.

General form of VARIABLE declaration:

VARIABLE variable_name, variable_name, ……. : type_name;

12

3.3 CONSTANT Data Objects

The CONSTANT data objects must be initialized with a value when declared and this value cannot be changed.

CONSTANT can be declared only inside the declarative part of ARCHITECTURE.

General form of CONSTANT declaration:

CONSTANT constant_name: type_name:=constant value;

13

Example of Data Objects

SIGNAL x: BIT;

VARIABLE y: INTEGER;

CONSTANT one: STD_LOGIC_VECTOR (3 DOWNTO 0):= "0001";

14

BASIC VHDL LANGUAGE ELEMENTS

1. Comments2. Identifiers3. Data Objects4. Data Types5. VHDL Operators6. VDHL Design Entity

15

4. Data Types

The VHDL data types are:1. BIT and BIT_VECTOR Data Type2. STD_LOGIC and STD_LOGIC_VECTOR Data

Type3. SIGNED and UNSIGNED Data Type4. INTEGER Data Type5. BOOLEAN Data Type6. Enumeration Data Type7. ARRAY Data Type

16

4.1 BIT and BIT_VECTOR Data Type

The BIT and BIT_VECTOR types are predefined in VHDL standards IEEE1076 and IEEE1164, hence no need for LIBRARY statement.

Objects of these types can only have the values ‘0’ or ‘1’.

The BIT_VECTOR type is simply a vector of type BIT.

CONT…………

17

4.1 BIT and BIT_VECTOR Data Type

Example:SIGNAL x: BIT;SIGNAL Y: BIT_VECTOR (5 DOWNTO 0);SIGNAL z: BIT_VECTOR (0 TO 4);...x <= '1';y <= "000010";z <= (OTHERS => '0'); -- same as "00000"

z(4) Z(3) Z(z) z(1) z(0)Y(5) Y(4) Y(3) Y(2) Y(1) Y(0)Y z

CONT…………

18

Notes:1. The syntax “lower_index TO higher index” is

useful for a multi bit signal that is simply an array of bits.

2. The syntax “higher_index DOWNTO lower_index” is useful if the signal represents a binary number.

4.1 BIT and BIT_VECTOR Data Type

194.2 STD_LOGIC and STD_LOGIC_VECTOR Data Type

The STD_LOGIC and STD_LOGIC_VECTOR types are not predefined.

Therefore, the following two library statements must be included in order to use these types:

LIBRARY IEEE;

USE IEEE.STD_LOGIC_1164.ALL;

CONT…………

20

If objects of type STD_LOGIC_VECTOR are to be used as binary numbers in arithmetic manipulations, then either one of the following two USE statements must also be included:

For signed number arithmetic

For unsigned number arithmetic

4.2 STD_LOGIC and STD_LOGIC_VECTOR Data Type

CONT…………

USE IEEE.STD_LOGIC_SIGNED.ALL;

USE IEEE.STD_LOGIC_UNSIGNED.ALL;

21

The STD_LOGIC and STD_LOGIC_VECTOR types provide more values than the BIT type for modelling a real circuit more accurately.

Objects of these types can have the following values:

'0' = normal 0 Useful ‘L’ =weak 0'1' = normal 1 for 'H' =weak 1'Z' =high impedance Logic 'U' =uninitialized'_' = don’t-care Circuits ‘X’ = unknown

'W'=weak unknown

4.2 STD_LOGIC and STD_LOGIC_VECTOR Data Type

CONT…………

22

Example:

4.2 STD_LOGIC and STD_LOGIC_VECTOR Data Type

LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;SIGNAL x: STD_LOGIC;SIGNAL y: STD_LOGIC_VECTOR (7 DOWNTO 0);x <= 'Z';y <= "0000001Z";y <= (OTHERS => '0'); -- same as "00000000"

23

4.3 SIGNED and UNSIGNED Data Type

These types are used for arithmetic operation; they represent an array of STD_LOGIC signals.

The purpose of SIGNED and UNSIGNED data types is to allow the user to indicate in the VHDL code what kind of number representation is being used.

CONT…………

24

To use these types, the code must include the following statement:

The SIGNED is used with 2’s complement representation.

4.3 SIGNED and UNSIGNED Data Type

CONT…………

LIBRARY IEEE;

USE IEEE.STD_LOGIC_ARITH.ALL;

25

4.4 INTEGER Data Type

The predefined INTEGER type defines binary number objects for use with arithmetic operators.

By default, an INTEGER signal uses 32 bits to represent a signed number.

Integers using fewer bits can also be declared with the RANGE keyword.

CONT…………

26

Example:

This defines y as 7-bit binary number.

4.4 INTEGER Data Type

SIGNAL x: INTEGER;

SIGNAL y: INTEGER RANGE –64 to 63;

27

4.5 BOOLEAN Data Type

The predefined BOOLEAN type defines objects having the two values TRUE and FALSE.

Example:SIGNAL x: BOOLEAN;

28

BASIC VHDL LANGUAGE ELEMENTS

1. Comments2. Identifiers3. Data Objects4. Data Types5. VHDL Operators6. VDHL Design Entity

29

5. VHDL Operators

1. Logical Operator2. Arithmetic Operators3. Assignment Operators4. Relational Operators5. Shift and Rotate Operators

30

5.1 Logical Operators

31

5.2 Arithmetic Operators

32

5.2 Arithmetic Operators

Used with STD_LOGIC_VECTOR, SIGNED, UNSIGNED, INTEGER

c <= -a; (c equals to the 2’s complement of a).

There are no synthesis restrictions regarding (Addition, Subtraction, and Multiplication).

For Division, only power of two dividers is allowed.

CONT…….

33

5.2 Arithmetic Operators

For Exponentiation, only static values of base and exponent are accepted.

(y MOD x) returns the reminder of y/x. with the signal of x.

(y REM x) returns the reminder of y/x with the signal y.

(MOD, REM, ABS) operators are generally little or no synthesis support.

CONT…….

34

5.3 Assignment Operators

<= Used to assign a value to a SIGNAL

:=Used to assign Value to VARIABLES, CONSTANTS, or GENERIC

=>Used to assign values to individual vector elements, or with OTHERS

35

5.3 Assignment Operators cont….

36

5.4 Relational Operators

Used to compare expressions

Result of comparison TRUE or FALSE

Compared expressions must be of the same type

37

5.4 Relational Operators cont…..

38

5.5 Shift and Rotate Operators

39

5.5 Shift and Rotate Operators - Example