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Smart Dust Mote Core Architecture

Smart Dust Mote Core Architecture

Brett Warneke, Sunil Bhave

CS252Spring 2000

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Smart Dust Mote Core Architecture

Smart Dust Overview

Autonomous sensing andcommunications in 1 mm3

Multiple sensors:

temperature, light,

vibration, etc.

Batteries: 1 J/mm3

Downlink:broadcast only

Uplink: CCR draws

6.4pJ/bit1-2 mm

Thick-Film Battery

Solar Cell

Power Capacitor

Analog I/O, DSP, Control

Passive Transmitter withCorner-Cube Retroreflector

Sensors

Receiver with Photodetector

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Smart Dust Mote Core Architecture

System Diagram

Core

Transceiver back end

Sensor Signal Processing

Computation

Memory

Sensors

Power

Supply

Receiver

Front End

ADC

Real TimeClock

CCR

Driver

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Smart Dust Mote Core Architecture

Design Goals

Minimize energythrough architecture Minimum energyASIC implementation

Dynamic reconfigurability

How much is necessary

tradeoff with ASIC mapping Energy driven operation modes

Military base monitoring

Typical application scenario to guide design

Detect heat and vibration of vehicles

Real time sensor readings

Logged sensor readings

ASIC Microprocessor

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Smart Dust Mote Core Architecture

One Approach: Golden Processor

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Smart Dust Mote Core Architecture

Golden Processor: Features

Laser Reprogrammable

Gated clocks everywhere

Processor stall mode

Eight execution phases

1 cpi including fetch

No pipelining to reduce overhead

Forced sequencing

Minimize glitching Prevent bus conflicts and thus short circuit current

Robust to delay variations from process spreads, voltage

swings (will test from 0.3V to 1.4V), and temperature

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Smart Dust Mote Core Architecture

New Approach: Top-Level Diagram

Sensors

Power

Supply

Receiver

Front End

ADC

Real TimeClock

CCR

Driver

Timer

Bank

Setup

Memroy

Reconfigurable

Datapath

Components

SRAM

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Smart Dust Mote Core Architecture

All activity initiated by timers When timer expires, Setup Memory 1

configures the datapath

Additional setup memories can be invoked to

perform more steps Two rates available for each timer

Two sensor sampling rates for normal polling

and interesting events

Delay receiver for a long period beforereturning to normal rate

Multiple setup memory banks for energy-

driven operationmodes

Timers and Setup Memory

Timer value 1

Timer value 2

Timer

Setup Mem 1

Setup Mem 2

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Smart Dust Mote Core Architecture

Reconfigurable Datapath Components

Adder

Timing Recovery

Mote ID Mem

Data Addr Reg

Sensor Reg n

Comparator

Threshold Mem n

Packet Decoder

Config Mem

FFT

Config Mem

FIR Filter

Data Recovery

Packet Encoder

CRCFIFO

Immediate Mode Setup Reg

Immediate mode packets load Immediate Mode Setup Registerto configure the datapath

Data-driven components

Wiring options

many point-to-point control and data wires

wire mesh with switches for routing

Global Setup Reg

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Smart Dust Mote Core Architecture

Example Configuration: Sensor Logging

Timer value 1

Timer value 2

Timer

Setup Mem 1

Setup Mem 2

Adder

Data Addr Reg

SensorReg

C

omparator

Threshold Mem

Sensor ADC

SRAM

PWR PWR

PWR

PWR

PWR

Done

Data

Done

Data

PWR

PWR

Addr

Data

Zero

WE

True

False Done

Open control signals are

driven by the setup memory

543210

Zero

Setup Mem 1

Open control signals are

driven by the setup memory

SensorReg

Sensor ADC

PWR PWR

PWR

PWR

PWR

Done

Data

PWR

PWR

Done

Data

Adder

Threshold Mem

Done

Data

PWRDone

Data

PWR

C

omparator

False

TrueTrue

Data Addr Reg

SRAM

PWR

Addr

Data

WEDone

Setup Mem 1

Setup Mem 2

Adder

Data Addr Reg

SensorReg

C

omparator

Threshold Mem

Sensor ADC

SRAM

PWR PWR

PWR

PWR

PWR

Done

Data

Done

Data

PWR

PWR

Addr

Data

WE

True

False Done

Open control signals are

driven by the setup memory

Setup Mem 2

Open control signals are

driven by the setup memory

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Smart Dust Mote Core Architecture

Comparison of Three Architectures

ARM8 estimations from Peggy Laramie, M.S. thesis 1998

energy is for a set of instructions equivalent to the configuration

on the previous slide Vdd=1V (scaled from the reported numbers)

Energy estimations for other approaches were to be from

Powermill

ARM8 GoldenProcessor

NewArchitecture

Data

logging w/threshold1.44nJ

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Smart Dust Mote Core Architecture

Conclusions

Smart Dust needs minimum energy controller New non-microprocessor architecture designed

Timer controlled

Reconfigurable datapath

Should be much lower energy than a microprocessor

architecture, but unconfirmed