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4/14/12

Bus Organization

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4/14/12Clock Circuits

The 8085 has an on-chip clock generator

It requires tuned circuit like LC, RC or Crystal orExternal Clock source as input to generate the clock

The T-flip flop divides the frequency by 2

The operating frequency is always half the oscillatorfrequency

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4/14/12Clock Circuits

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4/14/12Clock Circuits

RC Tuned Circuit:

the output frequency isnot exactly stable

Less cost forcomponents

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4/14/12Clock Circuits

Cystal Oscillator Circuit:

the most stable circuit

The 20 pF capacitorassures an accuratestart-up frequency

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4/14/12Clock Circuits

External Clock:

the figure showshow to use an

external clock

The external clockis applied at X1 inputand X2 input is keptopen

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4/14/12Demultiplexing AD7 AD0

AD0-AD7 lines aremultiplexed

Lower-half address

A0-A7

The lower-halfaddress bus must belatched in T1 of the

machine cycle tomake it availablethrough the rest ofthe machine cycle.This is done by

using an external

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4/14/12Reset Circuit

On reset, the PC sets to0000H which causes the 8085to execute the first instruction

in the 0000H address. The reset signal must be held

at LOW for 3 clock cycles for aproper reset.

The power-on reset circuitensures the activation of thefirst instruction from 000H

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4/14/12Reset Circuit

Upon power-up, RESET IN must remain LOW for 10 ms afterthe minimum Vcc is reached. Upon power-up or key press,the RESET IN goes low and slowly rises to +5V providing

sufficient time to reset. The diode is connected to discharge the capacitor when

power supply is cut off

After RESET, 8085 loads 0000H in PC register and clears the

INTE flag. INTE flip-flop is cleared to disable interrupts. It can be

enabled by EI instruction after initial settings.

EPROM consisting of monitor program must be located at

0000H to be executed after RESET or Power-up

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4/14/12Generation of Control Signals

The 8085 provides RD and WR to initiate read or write cycle

Read and write signals are separately generated for I/Odevices and memory

8085 provides IO/M signal to indicate whether the signal isfor I/O or memory

Using the IO/M, along with RD and WR it is possible togenerate 4 control signals.

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4/14/12Generation of Control Signals

MEMR (Memory Read) : To read data from memory

MEMW (Memory Write) : To write data in memory

IOR (I/O Read) : Read data from I/O device

IOW (I/O Write) : write data from I/O device

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4/14/12Generation of Control Signals

The circuit usesOR gates

When the outputis low only when

BOTH inputsare low

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4/14/12Bus Drivers

Typically, the 8085 buses can source 400 uA and sink 2mAof current

8085 can drive only one TTL load

Bus drivers and buffers increase the driving capacity of 8085

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4/14/12Bus Drivers

UNIDIRECTIONAL BUFFERS

8-bit unidirectional buffer74LS244 is used to bufferhigher address bus.

Consists of 8 non-invertingbuffers with tri-state outputs

Each can sink 24 mA andsource 15 mA of current

It is Divided into 2 groups

1G and 2G lines control theenabling and disabling of thegroups

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4/14/12Bus Drivers

BI-DIRECTIONAL BUFFER

Increases capacity of data bus

74LS245 is a bi-directional buffer also called Octal BusTransceiver

Consist of 16 non-inverting buffers, 8 for each direction withtri-state output

Data flow direction is controlled by pin DIR

When DIR is high, the flow of data is from A bus to B bus andB to A when low

Can sink 24 mA and source 15 mA of current

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4/14/12Typical Configuration