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Brandon Wang Group Director, Strategic Program April 2015 Cadence Thermal Solution
Brandon Wang Group Director, Strategic Program April 2015
Cadence Thermal Solution
2 © 2015 Cadence Design Systems, Inc. All rights reserved..
• Growing thermal issues – Technology scaling => higher power density – 3DICs => greater thermal issues
• Temperature impacts
– Power consumption – Peak performance – Aging – Package costs
• MP SoC architectures – Dynamic applications, variable execution time – Power management solutions (DVFS), can even worsen thermal
properties! Thermal mitigation schemes must be proposed at design time
Thermal issues in modern SoCs
3 © 2015 Cadence Design Systems, Inc. All rights reserved..
Impact of increased temperature during operation Increased design complexity and cost, higher operating cost
Data center
Source : Ponemon Institute Report (9/30/2010) on National Survey of Data Center Outages
Mobile market
Source : Broadcom talk on power and thermal challenges in mobile devices at Mobilicom 2013
Cooling is up to 50% of total cost Outage costs $5600/min.
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Nasty effects of increased temperature Mean time to failure decreases by 2X for each 10o increase
Electromigration
Increased resistance (higher IR drop) or failure
Source : NXP CDNLive! 2009 Bangalore
Faster failures
Source : Freescale/UCIrvine talk at daiict – August 2009
5 © 2015 Cadence Design Systems, Inc. All rights reserved..
Vicious cycle of thermal runaway Result of positive, accelerating feedback loop
Junction Temperature increase
Exponential increase in
leakage
Large increase in temperature Exceeds fixed capacity of package to dissipate heat
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• Temperature gradient may be as much as 40-500 across a chip
• Thermal diffusion causes heat to affect neighboring blocks
• Area with no transistors (very low power density) may be hotter than areas with active blocks
Thermal effects are not localized
7 © 2015 Cadence Design Systems, Inc. All rights reserved..
Thermal Challenges in Mobile Application
Source: ST-Ericson
8 © 2015 Cadence Design Systems, Inc. All rights reserved..
• Power-analysis must take temperature into consideration
• But power affects temperature
• Temperature calculation must take power into consideration
• Iteration required until analysis results in small changes to power and temperature
Need for closed-loop analysis
Power Analysis
Thermal Analysis
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Multi-Dies-package-board thermal co-simulation
Voltus Sigrity PowerDC
• Sigrity PowerDC computes Temperature map including multiple dies, package and board • Voltus computes temperature dependent Power map of each die ( leakage, dynamic) • Iterate co-simulation until results converge ( equilibrium, transit)
Power Map Temperature Map
Temperature Map Package Model
Power Map Die Model
Model Connection Protocol (MCP) – Connectivity map
from die to package to board
10 © 2015 Cadence Design Systems, Inc. All rights reserved..
• Support for flip-chip and 3DIC • Thermal analysis over multiple packages and boards • Tiled temperature map
System-centric thermal analysis Leakage-power dependent and including die information
2D plots of temperature and heat flux
3D visualization of thermal hotspots
Package DB (.spd)
Chip Design DB (LEF, DEF, Tech. Libs., Verilog, etc.)
Voltus
Sigrity PowerDC (Thermal
Only Mode)
Die Model w/o Package
(Spice RC model plus current signature)
i(t), I
Die Model
Power Map
11 © 2015 Cadence Design Systems, Inc. All rights reserved..
• Support for flip-chip and 3DIC • Analysis over multiple packages and boards
System-centric DC-thermal co-simulation Temperature-driven IR drop analysis including die information
Package DB (.spd)
Chip Design DB (LEF, DEF, Tech. Libs., Verilog, etc.)
Voltus
Sigrity PowerDC (Electrical-Thermal
co-sim. mode)
Die Model w/o Package
(Spice RC model plus current signature)
i(t), I
Die Model
Power Map
12 © 2015 Cadence Design Systems, Inc. All rights reserved..
Package Model Extraction with Sigrity XtractIM • Support for single and multi-chip die, flip-chip, wirebond and leadframe • User-controlled extraction precision (RLGC) • Extraction with Sigrity hybrid solver and 3DEM engines
Chip-centric power analysis and signoff Temperature-dependent and including package/PCB info.
Chip Design DB (LEF, DEF, Tech. Libs., Verilog, etc.)
Package DB (.spd)
Sigrity XtractIM
Voltus Package Model (Spice .sp)
PKG Model
PCB Model
Total Power
Switching Power (computed only for on domains)
Leakage Power
Temperature dependent power analysis
Tiled power maps
Sigrity PowerDC
Thermal Map
13 © 2015 Cadence Design Systems, Inc. All rights reserved..
• ~25% increase in current density for FinFETs
• Poor heat escape paths for FinFET devices – Wider temperature variations vs. planar
CMOS
• Self Heating Effect
– In devices (FEOL) – Function of number of fins, fingers etc.
– From thermal coupling with interconnect (BEOL) – Function of interconnect layer, metal width and
IRMS through the wires
Thermal sign-off in the era of FinFET devices
Source : Swann and Hassoun, Tufts Univ.
14 © 2015 Cadence Design Systems, Inc. All rights reserved..
• FEOL ∆T by instance and by tile – Based on power calculation
and thermal resistance file
• BEOL ∆T by instance per layer – Based on IRMS computation for
PG and signal nets
• Worst ∆T reported per tile
Voltus solution for SHE Analysis Temperature-aware signoff for FinFET designs
Chip Design DB (LEF, DEF, Tech. Libs., Verilog, etc.)
Voltus Self Heating Analysis (FEOL and BEOL)
Thermal
Resistance File
Switching Activity (TCF/VCD)
Thermal Maps
Reports
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Temperature-dependent chip signoff with Voltus IR drop and EM analysis
Chip Design DB (DEF, Verilog, etc.)
Temperature-based IR drop and EM analysis with Voltus
Library 1 (Temperature 1)
Library 2 (Temperature 2)
Library n (Temperature n)
Leakage currents
Switching Activity (TCF, VCD)
EM Rules File (Max. current
densities)
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• Global clock-gating with shutdown fail-safe
• Dynamic Voltage Scaling
• Temperature-tracking frequency scaling
• Feedback-controlled fetch-gating
• Fetch-decode throttling
• Speculation control
• Dual pipeline
• Migrating computation
• Register-file remapping
Dynamic thermal management (DTM) Design techniques to avoid thermal runaway
Slide 16 16
Source : Freescale/UCIrvine talk at daiict – August 2009
17 © 2015 Cadence Design Systems, Inc. All rights reserved..
• Allows monitoring of up to 8 sensor inputs
• SAR ADCs for high performance and low power – 50KS/s temperature conversion rate and 0.2mW power
• Low latency (10 cycles)
• Operational from -400C to 1250C
• Accuracy of +/- 50C untrimmed and +/-1.50C trimmed
On-chip temperature monitoring IP from Cadence Used for dynamic thermal management
Temperature monitoring IP
Temp. sensors PMU
DVS example
