EE1411

Microelettronica

Coping with Coping with InterconnectInterconnect

EE1412

Microelettronica

Impact of Interconnect Impact of Interconnect ParasiticsParasitics

• Reduce Robustness• Affect Performance

• Increase delay• Increase power dissipation

Classes of Parasitics

• Capacitive

• Resistive

• Inductive

EE1413

Microelettronica

Capacitive Cross TalkCapacitive Cross Talk

X

YVX

CXY

CY

EE1414

Microelettronica

Capacitive Cross TalkCapacitive Cross TalkDynamic NodeDynamic Node

3 x 1 μm2 overlap: 0.19 V disturbance

CY

CXY

VDD

PDN

CLK

CLK

In1In2In3

Y

X

2.5 V

0 V

EE1415

Microelettronica

Capacitive Cross TalkCapacitive Cross TalkDriven NodeDriven Node

Keep time-constant smaller than rise time

V ( V o l t )

X

YVX

RYCXY

CY

τXY = RY(CXY+CY)

0

0.50.450.4

0.350.3

0.250.2

0.150.1

0.050 10.80.6

t (nsec)0.40.2

tr↑ (5-500 ps)

Vy

(vol

t)

EE1416

Microelettronica

Dealing with CapacitiveDealing with CapacitiveCross TalkCross Talk

Avoid floating nodesProtect sensitive nodesMake rise and fall times as large as possibleDifferential signalingDo not run wires together for a long distanceUse shielding wiresUse shielding layers

EE1417

Microelettronica

ShieldingShielding

GND

GND

Shieldingwire

Substrate (GND )

Shieldinglayer

VDD

EE1418

Microelettronica

Cross Talk and PerformanceCross Talk and Performance

Cc

- When neighboring lines switch in opposite direction of victim line, delay increases

DELAY DEPENDENT UPON ACTIVITY IN NEIGHBORING WIRES

Miller EffectMiller Effect

- Both terminals of capacitor are switched in opposite directions (0 → Vdd, Vdd → 0)

- Effective voltage is doubled and additional charge is needed

X

Y

Z

Cc

EE1419

Microelettronica

Impact of Cross Talk on Delay Impact of Cross Talk on Delay

r is ratio between capacitance to GND and to neighbor

EE14110

Microelettronica

Design Design TechniquesTechniques

Evaluate and improveConstructive layout generationPredictable structuresAvoid worst case patterns

EE14111

Microelettronica

Structured Predictable InterconnectStructured Predictable Interconnect

S

S SV V S

G

SSV

G

VS

S SV V S

G

SSV

G

V

Example: Dense Wire Fabric ([Sunil Kathri])Trade-off:• Cross-coupling capacitance 40x lower, 2% delay variation• Increase in area and overall capacitance

EE14112

Microelettronica

Encoding Data Avoids WorstEncoding Data Avoids Worst--CaseCaseConditionsConditions

Encoder

Decoder

Bus

In

Out

EE14113

Microelettronica

Driving Large CapacitancesDriving Large Capacitances

• Transistor Sizing• Cascaded Buffers

EE14114

Microelettronica

2 4 6 8 10 12 142

2.2

2.4

2.6

2.8

3

3.2

3.4

3.6

3.8x 10

-11

S

t p(s

ec)

Device SizingDevice Sizing

(for fixed load)

Self-loading effect:Intrinsic capacitancesdominate

EE14115

Microelettronica

Inverter ChainInverter Chain

CL

If CL is given:- How many stages are needed to minimize the delay?- How to size the inverters?

May need some additional constraints.

In Out

EE14116

Microelettronica

tp = tp1 + tp2 + …+ tpN

⎟⎟⎠

⎞⎜⎜⎝

⎛+ +

jgin

jginunitunitpj C

CCRt

,

1,1~γ

LNgin

N

i jgin

jginp

N

jjpp CC

CC

ttt =⎟⎟⎠

⎞⎜⎜⎝

⎛+== +

=

+

=∑∑ 1,

1 ,

1,0

1, ,1

γ

Chain of N InvertersChain of N Inverters

EE14117

Microelettronica

Delay equation has N - 1 unknowns, Cgin,2 ….. Cgin,N

Minimize the delay, find N - 1 partial derivatives

Result: Cgin,j+1/Cgin,j = Cgin,j/Cgin,j-1

Size of each stage is the geometric mean of two neighbors

- each stage has the same effective fanout (Cout/Cin)- each stage has the same delay

1,1,, +−= jginjginjgin CCC

Optimal Tapering for Given NOptimal Tapering for Given N

EE14118

Microelettronica

ExampleExample

CL= 8 C1

In Out

C11 f f2

283 ==f

CL/C1 has to be evenly distributed across N = 3 stages:

EE14119

Microelettronica

Optimum Delay and Number of Optimum Delay and Number of StagesStages

1,/ ginLN CCFf ==

When each stage is sized by f and has same eff. fanout f:

N Ff =

( )γ/10N

pp FNtt +=

Minimum path delay

Effective fanout of each stage:

EE14120

Microelettronica

Optimum Number of StagesOptimum Number of Stages

For a given load, CL and given input capacitance CinFind optimal sizing f

( ) ⎟⎟⎠

⎞⎜⎜⎝

⎛+=+=

fffFt

FNtt pNpp lnln

ln1/ 0/1

0γ

γγ

0ln

1lnln2

0 =−−

⋅=∂

∂

fffFt

ft pp γ

γ

fFNCfCFC in

NinL ln

ln with ==⋅=

( )ff γ+= 1exp

EE14121

Microelettronica

Optimum Effective FanOptimum Effective Fan--out fout fOptimum f for given process defined by γ

( )ff γ+= 1exp

fopt = 3.6for γ=1

EE14122

Microelettronica

Impact of SelfImpact of Self--Loading on Loading on ttpp

With Self-Loading γ=1

EE14123

Microelettronica

Normalized delay function of FNormalized delay function of F

( )γ/10N

pp FNtt +=

EE14124

Microelettronica

Buffer DesignBuffer Design

1

1

1

1

8

64

64

64

64

4

2.8 8

16

22.6

N f tp

1 64 65

2 8 18

3 4 15

4 2.8 15.3

EE14125

Microelettronica

Using Cascaded BuffersUsing Cascaded Buffers

CL = 20 pF

In Out

1 2 N0.25 μm processCin ≅ 2.5 fFtp0 ≅ 30 ps

F = CL/Cin = 8000fopt = 3.6 N = 7tp ≅ 0.97 ns

Transistor sizes for optimally sized cascaded buffers

EE14126

Microelettronica

Delay as a Function of F and NDelay as a Function of F and N

101 3 5 7

Number of buffer stages N

9 11

10,000

1000

100

t

p

/

t

p

0

F = 100F = 1000

F = 10,000t p

/t p0

EE14127

Microelettronica

Output Driver Design (1)Output Driver Design (1)

Trade off Performance for Area and EnergyGiven tpmax find N and f

Area

Energy

( ) minminmin12

11

11...1 A

fFA

ffAfffA

NN

driver −−

=−−

=++++= −

( ) 22212

111...1 DD

LDDiDDi

Ndriver V

fCVC

fFVCfffE

−≈

−−

=++++= −

EE14128

Microelettronica

Output Driver Design (2)Output Driver Design (2)

Transistor Sizes for optimally-sized cascaded buffer tp = 0.97 ns

Transistor Sizes of redesigned cascaded buffer tp = 1.89 ns

0.25 μm process, CL = 20 pF, Cin ≅ 2.5 fF

EE14129

Microelettronica

1 1.5 2 2.5 3 3.5 4 4.5 53

3.5

4

4.5

5x 10

-11

β

t p(s

ec)

NMOS/PMOS ratioNMOS/PMOS ratio

tpLH tpHL

tp β = Wp/Wn

EE14130

Microelettronica

How to Design Large TransistorsHow to Design Large Transistors

G(ate)

S(ource)

D(rain)

Multiple

Contacts

small transistors in parallel

Reduces diffusion capacitanceReduces gate resistance

EE14131

Microelettronica

Bonding Pad DesignBonding Pad DesignBonding Pad

Out

InVDD GND

100 μm

GND

Out

In

guard ring

EE14132

Microelettronica

ESD ProtectionESD Protection

Diode

PAD

VDD

R D1

D2X

C

PAD

BUFFER

RESISTOR

EE14133

Microelettronica

Pad FramePad FrameLayout Die Photo

EE14134

Microelettronica

Tristate BuffersTristate Buffers

InEn

En

VDD

Out

VDD

In

En

EnOut

EE14135

Microelettronica

Impact of ResistanceImpact of Resistance

We have already learned how to drive RC interconnectImpact of resistance is commonly seen in power supply distribution:

IR dropVoltage variations

Power supply is distributed to minimize the IR drop and the change in current due to switching of gates

EE14136

Microelettronica

RI Introduced NoiseRI Introduced Noise

M1

X

I

R ‘

RΔV

φ pre

ΔV

VDD

VDD - ΔV ‘

I

EE14137

Microelettronica

Power DistributionPower Distribution

Low-level distribution is in Metal 1Power has to be ‘strapped’ in higher layers of metal.The spacing is set by IR drop, electromigration, inductive effectsAlways use multiple contacts on straps

EE14138

Microelettronica

Power and Ground DistributionPower and Ground Distribution

GND

VDD

Logic

GND

VDD

Logic

GND

VDD

(a) Finger-shaped network (b) Network with multiple supply pins

EE14139

Microelettronica

3 Metal Layer Approach (EV4)3 Metal Layer Approach (EV4)3rd “coarse and thick” metal layer added to the

technology for EV4 designPower supplied from two sides of the die via 3rd metal layer

2nd metal layer used to form power grid90% of 3rd metal layer used for power/clock routing

Metal 3

Metal 2Metal 1

Courtesy Compaq

EE14140

Microelettronica

4 Metal Layers Approach (EV5)4 Metal Layers Approach (EV5)4th “coarse and thick” metal layer added to the

technology for EV5 designPower supplied from four sides of the dieGrid strapping done all in coarse metal

90% of 3rd and 4th metals used for power/clock routing

Metal 3

Metal 2Metal 1

Metal 4

Courtesy Compaq

EE14141

Microelettronica

2 reference plane metal layers added to thetechnology for EV6 designSolid planes dedicated to Vdd/Vss

Significantly lowers resistance of gridLowers on-chip inductance

6 Metal Layer Approach 6 Metal Layer Approach –– EV6EV6

Metal 4

Metal 2Metal 1

RP2/Vdd

RP1/Vss

Metal 3

Courtesy Compaq

EE14142

Microelettronica19

ASP DAC 2000

Power Dissipation TrendsPower Dissipation Trends

Power consumption is increasingPower consumption is increasingBetter cooling technology neededBetter cooling technology needed

Supply current is increasing faster!Supply current is increasing faster!OnOn--chip signal integrity will be a major chip signal integrity will be a major issueissuePower and current distribution are criticalPower and current distribution are criticalOpportunities to slow power growthOpportunities to slow power growth

Accelerate Accelerate VddVdd scalingscalingLow κ dielectrics & thinner (Cu) Low κ dielectrics & thinner (Cu) interconnectinterconnectSOI circuit innovations SOI circuit innovations Clock system designClock system designmicromicro--architecturearchitecture

Power Dissipation

020406080

100120140160

EV4 EV5 EV6 EV7 EV8

Pow

er (W

)

00.511.522.533.5

Vol

tage

(V)

Supply Current

020406080

100120140

EV4 EV5 EV6 EV7 EV8

Cur

rent

(A)

00.511.522.533.5

Volta

ge (V

)

EE14143

Microelettronica

Power Distribution ProblemPower Distribution ProblemSource: Cadence

•• Requires fast and accurate peak current predictionRequires fast and accurate peak current prediction•• Heavily influenced by packaging technologyHeavily influenced by packaging technology

BeforeBefore AfterAfter

Highest voltage drop

EE14144

Microelettronica

ElectromigrationElectromigration (1)(1)

Limits dc-current to 1 mA/μm

EE14145

Microelettronica

ElectromigrationElectromigration (2)(2)

EE14146

Microelettronica

Resistivity and PerformanceResistivity and Performance

0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 50

0.5

1

1.5

2

2.5

time (nsec)

vo

ltag

e (

V)

x= L/10

x = L /4

x = L /2

x= L

0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 50

0.5

1

1.5

2

2.5

time (nsec)

vo

ltag

e (

V)

x= L/10

x = L /4

x = L /2

x= L

Diffused signal Diffused signal propagationpropagation

Delay ~ LDelay ~ L22

CN-1 CNC2

R1 R2

C1

Tr

Vin

RN-1 RN

The distributed The distributed rcrc--lineline

EE14147

Microelettronica

Using BypassesUsing BypassesDriver

Polysilicon word line

Polysilicon word line

Metal word line

Metal bypass

Driving a word line from both sides

Using a metal bypass

WL

WL K cells

EE14148

Microelettronica

Diagonal WiringDiagonal Wiring

y

x

destination

Manhattan

source

diagonal

•20+% Interconnect length reduction• Clock speedSignal integrityPower integrity

• 15+% Smaller chips plus 30+% via reduction Example of layout using 45° lines

EE14149

Microelettronica

Interconnect Projections: CopperInterconnect Projections: Copper

Copper is planned in full sub-0.25 μm process flows and large-scale designs (IBM, Motorola, IEDM97)With cladding and other effects, Cu ~ 2.2 μΩ-cm vs. 3.5 for Al(Cu) ⇒40% reduction in resistanceElectromigration improvement; 100X longer lifetime (IBM, IEDM97)

Electromigration is a limiting factor beyond 0.18 μm if Al is used (HP, IEDM95)

Vias

EE14150

Microelettronica

Interconnect hierarchy of 0.25 Interconnect hierarchy of 0.25 μμmmCMOS processCMOS process

# of metal layers is steadily increasing due to:

• Increasing die size and device count: we need more wires and longer wires to connect everything

• Rising need for a hierarchical wiring network; local wires with high density and global wires with low RC

0.25 μm wiring stacksubstrate

poly

M1

M2

M3

M4

M5

M6

Tins

H

WS

ρ = 2.2μΩ -cm

EE14151

Microelettronica

Minimum Widths (Relative)

0.0

0.5

1.0

1.5

2.0

2.5

3.0

3.5

1.0μ 0.8μ 0.6μ 0.35μ 0.25μ

M5M4M3M2M1Poly

Minimum Spacing (Relative)

0.0

0.5

1.0

1.5

2.0

2.5

3.0

3.5

4.0

1.0μ 0.8μ 0.6μ 0.35μ 0.25μ

M5M4M3M2M1Poly

Wiring Layers Wiring Layers

EE14152

Microelettronica

DelayDelay in the in the PresencePresence of Long of Long InterconnectInterconnect WiresWires

EE14153

Microelettronica

Reducing RCReducing RC--delaydelay

Repeater

EE14154

Microelettronica

Repeater InsertionRepeater InsertionTaking the repeater loading into account

EE14155

Microelettronica

For a given technology and a given interconnect layer, there exiFor a given technology and a given interconnect layer, there exists sts an optimal length of the wire segments between repeaters. The an optimal length of the wire segments between repeaters. The delay of these wire segments is delay of these wire segments is independent of the routing layer!independent of the routing layer!

Repeater InsertionRepeater Insertion

EE14156

Microelettronica

OptimizingOptimizing the the InterconnectInterconnectArchitectureArchitecture

Wire pipelining improves the throughput of a wire

EE14157

Microelettronica

Ldi/dtLdi/dt voltage dropvoltage drop

Impact of inductance on supply voltages:• Change in current induces a change in voltage• Longer supply lines have larger L

CL

V ’DD

V DD

L i(t)

V outV in

GND ’

L

EE14158

Microelettronica

Ldi/dtLdi/dt: Simulation: Simulation

0 0.5 1 1.5 2

x 10-9

0

0.5

1

1.5

2

2.5

V out(V

)

0 0.5 1 1.5 2

x 10-9

0

0.02

0.04

i L(A

)

0 0.5 1 1.5 2

x 10-9

0

0.5

1

VL

(V)

time (nsec)

0 0.5 1 1.5 2

x 10-9

0

0.5

1

1.5

2

2.5

0 0.5 1 1.5 2

x 10-9

0

0.02

0.04

0 0.5 1 1.5 2

x 10-9

0

0.5

1

time (nsec)

Input rise/fall time: 50 psec Input rise/fall time: 800 psec

decoupled

Without inductors

With inductors

Without

With inductors

With inductors

decoupled

EE14159

Microelettronica

Dealing with Dealing with Ldi/dtLdi/dt

Separate power pins for I/O pads and chip core.Multiple power and ground pins. Careful selection of the positions of the power and ground pins on the package.Increase the rise and fall times of the off-chip signals to the maximum extent allowable.Schedule current-consuming transitions. Use advanced packaging technologies.Add decoupling capacitances on the board.Add decoupling capacitances on the chip.

EE14160

Microelettronica

Choosing the Right PinChoosing the Right Pin

ChipL

L ´

Bonding wire

Mountingcavity

Leadframe

Pin

EE14161

Microelettronica

Decoupling CapacitorsDecoupling Capacitors

SUPPLY

Boardwiring

Bondingwire

Decouplingcapacitor

CHIPCd

1

2

Decoupling capacitors are added: • on the board (right under the supply pins)• on the chip (under the supply straps, near large buffers)

EE14162

Microelettronica

OnOn--chip Decoupling Capacitances chip Decoupling Capacitances in Alpha Processor Familyin Alpha Processor Family

Source: B. Herrick (Compaq)