Cascading CMOS gates

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Goal

Designing for minimum propagation delay:

•Fixed number of stages•Optimum number of stages

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Example 1:Two cascaded inverters

S=W/L

CL/Ci=

Ip: Cp= Cin(Inv2)

Inv2Inv1

Cp= u Ci

S uS

uSCp

CLVi Vp Vo

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Transistor sizing

•two cascading stages:

• minimize propagation delay:

u

tutttt po

po2p1pp

u

po2p1p ttt

i puC Ci LC C

CiClt2t2t popop

Vi Vp(u)

Vo

Ci Cp CL

I B

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Example

Two stages are faster than one if:

CiClt2t popo

CiClt2t pop

4CiCl

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Sizing Logic Paths for Speed

Frequently, input capacitance of a logic path is constrained Logic also has to drive some capacitance Example: ALU load in an Intel’s microprocessor is 0.5pF How do we size the ALU datapath to achieve maximum speed? We have already solved this for the inverter chain – can we

generalize it for any type of logic?

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Delay in a Logic Gate

Gate delay:

d = h + p

effort delay intrinsic delay

Effort delay:

h = g f

logical effort

effective fanout = Cout/Cin

Logical effort is a function of topology, independent of sizingEffective fanout (electrical effort) is a function of load/gate size

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Optimum number of stages: buffer

Why a buffer

- long interconnection wires

- chip interfaces

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Chip interface: an example

Pentium (7 buffer)L = (10.2-19.9) nH

Cp = (2.6 - 9.7) pF

Co = (4.8 -17.1) pF

PAD PIN

Co Cp

L

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Long interconnection wires

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Single interconnection capacitance

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Total interconnection capacitance

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Example: 2 inverter stages

fCi 20 F pFCC iL 201000

ns26tns4.0t

t641000t2t

ppo

popop

Too large !

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Multiple stage Buffer

in2

2

in1

CuC

CuC

N

i

L

in1N

1N

uC

C

CuC

u

tututtt po

2

po2p1pp

pop tuNt

VG

C1 C2 CN-1 CL

Vi V1 V2 Vo1 2 3 N

u u2 uN-1

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Cascading CMOS inverters

iN

L

pop

CuC

tuNt

Minimizing tp:

)C

Cln(ett

72.2eu

)C

Cln(N

i

Lpop

opt

i

Lopt

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Propagation delay vs sizing factor u

X Inv 2 Inv N Inv

10 10 6.3 6.3

100 100 20 12.5

1000 1000 63 18.8

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Example

CMOS 1m; Ci=10fF; tp 0.2ns

CL=20pF X=2000

7 stages tp 4ns

Stage 1 2 3 4 5 6 7 Wn(m) 1.8 5.3 15.8 47.7 138.2 409.9 1210.7Wp(m) 2.8 8.4 24.9 73.8 218.3 646.21912.8

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Tri-State CMOS Buffer