Catapult C Synthesis Shines a Light on STMicroelectronics Imaging ChallengesThe STMicroelectronics Imaging Division, within the company’s HomeEntertainment and Displays Group, creates high image quality productstargeted at the consumer market. To achieve higher design productivity tocompete more effectively in this demanding space, STMicroelectronicsdecided to investigate high-level synthesis solutions. Within just a fewyears, the division has gone from evaluating this methodology to relying onCalypto’s high-level synthesis tool, Catapult®C Synthesis, to create some ofits most critical designs. In fact, more that 70 million phones equipped withSTMicroelectronics Imaging chips containing IP designed with Catapult Chave been already sold.

STMicroelectronics ImagingDivision develops a wide-range

of sensors, camera modules, andimage processors, building on 12years of experience and expertise inthe complete imaging chain(sensors, optics, processing).STMicroelectronics’ image subsys-tems produce high image quality incompact form factors at a low costand are mainly targeted at consumerproducts such as camera phones,PDAs, digital still cameras andoptical mices. The division alsocreates sensors for dedicated opticsin industrial and security applica-tions along with imaging signalprocessors that implement advancedcolor processing and imageenhancement algorithms.

STMicroelectronics was lookingfor a way to achieve higher designproductivity when creating thesehigh-quality, low-cost products.According to Arnaud Laflaquiere,

Sensors Business Unit Manager inSTMicroelectronics’ ImagingDivision, “The imaging market is aconstant ‘race to pixels’ and sensorsize, all of which is strongly domi-nated by time to market pressures.”

“The image quality mustconstantly be improved throughdedicated enhancement algorithmsto differentiate image processorproducts,” adds Massimo Mancuso,Image Processors Business UnitManager withinSTMicroelectronics.

Power consumptionmust be kept to aminimum, since mostof the imaging prod-ucts end up in handhelddevices that have strictpower budgets toensure competitivebattery performance.However, sensor resolu-tion directly impacts power:

Alexandre Cellier, Massimo Mancuso, and Giuseppe Bonanno of STMicroelectronics.

“We believe that CatapultC and high-level

synthesis give us animportant competitiveedge. It is one of manyfactors in helping us

maintain our leadershipin the highly competitive

imaging market.”

MASSIMO MANCUSO

IMAGE PROCESSORS

BUSINESS UNIT MANAGER

STMICROELECTRONICS

the more pixels, the more powerconsumed. In addition, there is theconstant tradeoff between using rela-tively power-hungry enhancementalgorithms and optimizing for power.

Due to all these factors, multi-constraint optimizations arerequired in the imaging division’sdesign environment. Flexibility,reactivity and the ability to quicklyspin derivatives are absolutelyessential to stay ahead in business.

Saving Time on First Designs

With all this in mind, AlexandreCellier, Senior Design Engineer,and the ST Imaging design teamdecided a few years ago to investi-gate high-level synthesis. His teamworks in a C model-based flowwhere all the models for the designsare originally created in C/C++. Themodels are mostly bit accurate fromthe start. STMicroelectronicsImaging Division went through anextensive time-to-market improve-ment initiative, looking for ways toimprove productivity. Their expec-tation was that high-level synthesisdirected from the C models wouldenable the design team to achievecorrect RTL quicker whileimproving the overall quality of thearchitectures. For example, it isfaster to write a FIR filter in Cwithout any timing or technologyconstraints than writing the samefunction in RTL. The RTL designrequires the description of each ofthe different stages of pipelineneeded to meet a given speed or

technology target, making it a time-consuming task when designing atthe RTL.

Cellier evaluated the Catapult CSynthesis solution from Calyptobecause it offered a mature andcomprehensive environment forhigh-level synthesis. The assessmentof Catapult C was to take placewithin the context of real-worlddesign projects on three differentdesign blocks.

The first IP block was a new algorithmic-based design that existedonly as a higher-level description inC/C++. The second and third algo-rithm blocks were ones they hadalready created in RTL using thetraditional hand coding approach.They decided to recreate these twofrom the original C specification inCatapult C. That would give them a

direct comparison between the twomethodologies with respect to designtime and the quality of the RTL.

The results of all three evalua-tions surpassed the design team’sexpectations. The first IP wasconsidered impossible to create inless than a year. Yet with Catapult C,the design team was able to deliverfully verified RTL in only 50 percentof the time. The second IP originallytook six months to hand design, butit took only 10 weeks to createsimilar RTL results with Catapult C:a 60 percent time savings. The expe-rience with the third IP was similar:it took five months to hand code theRTL compared to just three monthswith Catapult C, for a 40 percentreduction.

In all three test cases, the qualityof the RTL—particularly withrespect to area and timing—provedto meet or exceed the hand codedversions. These impressive resultsconvinced the design team thathigh-level synthesis usingCatapult C was a viable approachfor the Imaging Division. In fact,they were so enthusiastic aboutCatapult C that by the end of thatfirst year they had already taped-outtheir first IP block generated withCatapult C.

High Level Synthesis Expanding

Since that time, theSTMicroelectronics ImagingDivision has successfully taped outover 11 designs using high-levelsynthesis over the past four years.

“With the Catapult C flow,RTL debug literally

disappears. The C model isvalidated in its environment,and from there correct-by-

construction RTL is created.This reduces the verification

effort dramatically.”

GIUSEPPE BONANNO

DESIGN TOOLS AND

METHODOLOGIES MANAGER

STMICROELECTRONICS

this makes it complicated to port anIP to a new, faster technology.

In contrast, because the coding isdone at the C level, with Catapult Cthe IP is easier to review and under-stand. The designers essentiallyfocus on the functional intent,leaving most of the implementationdetails for the tool to automate,greatly facilitating later reuse andmodifications. Verification is alsogreatly improved because the reuseof the IP is automated, eliminatingerrors that can creep in when handcoding RTL. Cellier offers acautionary note, “While C/C++ ismuch more abstract than RTL, it isstill easy to complicate it. Goodguidelines and education are impor-tant for ease of readability andreusability, but once this learninginvestment is made, tremendousproductivity gains can be obtainedand sustained.”

Moving Catapult C intoMainstream Design

Another welcomed advantage inadopting Catapult C was how easilyit integrated into the team’s designflow. As the Design Tools andMethodologies manager for theImaging Division, GiuseppeBonanno supports many EDA toolsin the STMicroelectronics Imagingflows. He was pleased at howsmoothly Catapult C was to adopt.“Catapult C proved to integratequite seamlessly into our designflow. Initial glitches were resolved

The team has kept pace with anearly 5X increase in designcomplexity in their imaging algo-rithmic IP during that time. Theyfind it much easier to adapt and porttheir IP in C compared to RTL.

According to Cellier, “Ourdesign team now routinely usesCatapult C to create complex, multi-block IP due to its maturity and itsincreasing capacity. Additionally,we face an on-going need toimprove productivity to meet theincreasing demands of the market.”With more of the algorithmic designbeing automatically created by thehigh-level synthesis environment,less needs to be manually integratedin the later stages of the design.

Initially, the natural tendency wasto design smaller, single blocks sothe results could be easily under-stood as a check on whetherCatapult C was creating acceptable,if not optimal results. Over time, theconsistent quality achieved byCatapult C convinced them to movemore of their algorithmic design tohigh-level synthesis. “As Catapult Cearned our trust through predictablefunctional accuracy and high qualityof result,” says Cellier, “we gainedthe needed confidence to assignbigger designs to the tool, resultingin even larger productivity gains.”

An Unexpected, Welcome Benefit

STMicroelectronics’ imagingdesigners discovered thatCatapult C considerably improvedthe reusability of their IP by

moving the abstraction level fromRTL to the C level.

Reuse at the RTL is far fromstraightforward and often a frus-trating, time-consuming process. Inmany cases, RTL models are leftpoorly documented and the originalIP authors are often busy with a newproject or may not be with thecompany anymore. Despite strict

coding guidelines, different IPusually looks different, based on theauthor’s coding preferences. So italways takes time to get familiarwith the coding and mindset of theauthor to understand the intent of theIP. Moreover, with complex algo-rithms, clever implementation tricksare often employed at the implemen-tation level, making it even moredifficult to understand the under-lying algorithmic specification. All

“As Catapult C earned ourtrust through predictable

functional accuracy and highquality of result, we gainedthe needed confidence to

assign bigger designs to thetool, resulting in even larger

productivity gains.”

ALEXANDRE CELLIER

SENIOR DESIGN ENGINEER

STMICROELECTRONICS

expeditiously and Calypto’s supportwas there every time we needed it.”

Part of what smoothed the transi-tion was the fact that the designteam was already modeling theiralgorithmic IP in C/C++, so it was anatural progression to move to high-level synthesis. With Catapult C, theimaging designers can now createand refine the algorithms in C andthen automatically create the RTLon the implementation side. Prior toCatapult C, making changes to thealgorithms was a tedious anddisconnected process. The modifi-cations had to be hand coded in theRTL, creating a potential source oferrors and requiring extensive, time-consuming debug cycles.

“With the Catapult C flow, RTLdebug literally disappears. The Cmodel is validated in its environ-ment, and from there correct-by-construction RTL is created. Thisreduces the verification effortdramatically,” Bonanno observes.

Visit our web site at www.calypto.com for the latest product news.

“In our product roadmaps, wherethe target frequencies are alwaysincreasing, we often have to reworkexisting IP to have it running at ahigher frequency. Thanks toCatapult C we have drasticallyreduced the time required forretiming since all the modificationscan be done at the C level,” statesCellier.

An Ever-Expanding Horizon

Bonanno, Cellier, and theimaging design team are extremelysatisfied with Catapult C for thecreation of their algorithmic-baseddesign IP. They plan to continueexpanding its use in future designs.“We believe that Catapult C andhigh-level synthesis give us animportant competitive edge,”declares Mancuso. “It is one ofmany factors in helping us maintainour leadership in the highly compet-itive imaging market.”

“In our product roadmaps,where the target

frequencies are alwaysincreasing, we often haveto rework existing IP to

have it running at a higherfrequency. Thanks toCatapult C we have

drastically reduced the timerequired for retiming sinceall the modifications can be

done at the C level.”

ALEXANDRE CELLIER

SENIOR DESIGN ENGINEER

STMICROELECTRONICS