ELEC 522 Catapult C Synthesis Work Flow Tutorial ECE Department, Rice University Page 1 Catapult C Synthesis Work Flow Tutorial ELEC 522 Advanced VLSI Design, Rice University Version 1.3 10/14/2010, Guohui Wang Introduction In this tutorial, you will go through the complete work flow of Catapult C Synthesis, including bit accurate C program simulation, HDL generation, ModelSim/ISE Simulator simulation/verification, and integration with System Generator. You will build a simple sum of square computation block using Catapult C tool. Objectives After this tutorial lab, you will be able to: Write C/C++ code in Catapult C. Compile and simulate the C/C++ code using GCC; Use Catapult C to generate HDL code; Simulate/Verify the generated HDL model in ModelSim/ISE built-in Simulator; Integrate the HDL model into System Generator design by using the Black-box block. Then simulate a complete system in System Generator. Design Description Use Catapult C Synthesis to implement a “sum of square” computation: Computation equation: c = a*a + b*b; Data type: a and b are both 16bit fixed-point numbers; c is 34bit number. Tools Used in This Lab In this lab, we will use the following tools: Mentor Graphics Catapult C Synthesis 2009a.85 GCC 4.2.2 Xilinx ISE 10.1.3 ModelSim SE6.5c Xilinx System Generator 10.1 MATLAB 2008a
Transcript
ELEC 522 Catapult C Synthesis Work Flow Tutorial ECE Department, Rice University Page 1
Catapult C Synthesis Work Flow Tutorial
ELEC 522 Advanced VLSI Design, Rice University
Version 1.3 10/14/2010, Guohui Wang
Introduction In this tutorial, you will go through the complete work flow of Catapult C Synthesis, including bit accurate C program simulation, HDL generation, ModelSim/ISE Simulator simulation/verification, and integration with System Generator. You will build a simple sum of square computation block using Catapult C tool.
Objectives After this tutorial lab, you will be able to:
Write C/C++ code in Catapult C. Compile and simulate the C/C++ code using GCC;
Use Catapult C to generate HDL code;
Simulate/Verify the generated HDL model in ModelSim/ISE built-in Simulator;
Integrate the HDL model into System Generator design by using the Black-box block. Then simulate a complete system in System Generator.
Design Description Use Catapult C Synthesis to implement a “sum of square” computation:
Computation equation: c = a*a + b*b;
Data type: a and b are both 16bit fixed-point numbers; c is 34bit number.
Tools Used in This Lab In this lab, we will use the following tools:
Mentor Graphics Catapult C Synthesis 2009a.85
GCC 4.2.2
Xilinx ISE 10.1.3
ModelSim SE6.5c
Xilinx System Generator 10.1
MATLAB 2008a
ELEC 522 Catapult C Synthesis Work Flow Tutorial ECE Department, Rice University Page 2
Procedure This tutorial comprises 6 primary steps:
1. Create a new Catapult project. Write C++ code in Catapult C; 2. Simulate C++ code using GCC; 3. Generate Verilog HDL code in Catapult; 4. Simulate/Verify HDL model in ModelSim/ISE-simulator; 5. Synthesize your HDL model using Xilinx ISE; 6. Use black-box to integrate the HDL model into System Generator and simulate the complete system
in System Generator.
Please notice that the goal of this document is only to show the basic tool flow. Therefore, we do not optimize our design. In your project design, you might need to go back and forth for a couple of iterations between step 1 and step 4 to optimize your design. Besides, in this simple tutorial I have not considered the interface optimization. In your project, you need to consider the interface design, for example, pointer VS non-pointer interfaces.
STEP 1: C Programming in Catapult C Synthesis Create a new folder. Start the Catapult tool on the Linux server. Then create a new project in Catapult.
Click “Set Working Directory”, in the popup dialog select the folder you just created.
In the menu, select File->New to create a new file. Type in the code below: Select File->Save as, to save this file as “example.h”.
Data type uint34 has been defined in ac_int.h: typedef ac_int<34, true> uint34;
Then create another new file, type in the following code, then save it as “example.cpp”.
#include "example.h" #pragma hls_design top int34 sumsquare(int16 a, int16 b) { int34 c = 0; c = a * a + b* b; return c; }
//Include Catapult bit accurate types #include "ac_int.h" int34 sumsquare(int16 a, int16 b);
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lab2. Finally, your Makefile will look like this:
Notice that, ${MGC_HOME} is an environment variable that points to the install path of Mentor Graphics Catapult C Synthesis. This environment varialble has been set when you log in the Linux server. In the .tcshrc file under your home directory, you source several setup scripts, and one of them sets the MGC_HOME environment variable.
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Step 6: Integrate HDL Model into System Generator In this step, you will integrate the HDL model into System Generator by using the Black-Box block. Then you could verify your design in a System Generator project.
At first, you need to create a skeleton file, which contains the Verilog HDL module with only module definition and interface declaration. This skeleton will tell System Generator Black Box block the basic information of you HDL model, so that System Generator will generate a configuration file for your HDL Black Box automatically. Once you have the configuration file for your Black Box, you need to replace the skeleton file with your synthesizable Verilog HDL file from Step 5.
Create a new folder for the System Generator project. Create a new skeleton file, and name it as ‘rtl.v’ (*Notice: the name should be the same as your RTL model.). Copy your RTL model definition into this file (Please just copy the module definition; in other words, there is only an empty module with interface definition but doing nothing). In our example, the definition of the RTL model is shown as below:
Add an input ‘ce’ (clock enable signal) in the model, your code should look like this:
Clock and clock enable ports in black box HDL must appear as pairs . Each clock name (respectively, clock enable name) must contain the substring clk, for example my_clk_1 and my_ce_1. (Please refer to System Generator User Guide, Chapter 4: Importing HDL Modules.)
Run MATLAB. Create a new System Generator model in the same folder with your empty module definition file. Add a ‘Black Box’ from the Simulink Library Browser. In the pop-up dialog, select the empty module ‘rtl.v’. System Generator will generate a Black Box block for you.
