CDCI6214EVM
User's Guide
Literature Number: SNAU202BJuly 2017–Revised October 2018
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Contents
Contents
Preface ........................................................................................................................................ 51 Setup Procedure .................................................................................................................. 6
1.1 Quick Start .................................................................................................................... 61.1.1 Default Configuration ............................................................................................... 7
2 Evaluation Module Configuration ........................................................................................... 82.1 Device Under Test ........................................................................................................... 82.2 Control Pins................................................................................................................... 82.3 Reference Input .............................................................................................................. 92.4 Clock Outputs............................................................................................................... 122.5 Power Supplies ............................................................................................................. 13
3 Frequently Asked Questions - FAQ....................................................................................... 173.1 Troubleshooting ............................................................................................................ 17
A References ........................................................................................................................ 19A.1 Software ..................................................................................................................... 19A.2 EVM Schematics ........................................................................................................... 20A.3 EVM Layout ................................................................................................................. 29
Revision History.......................................................................................................................... 36
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List of Figures
List of Figures1-1. CDCI6214EVM ............................................................................................................... 62-1. Evaluation Module Default, Control Pins ................................................................................. 82-2. Evaluation Module Default, Control Pin Level Shifters ................................................................. 92-3. Evaluation Module Default, Reference Connection.................................................................... 112-4. Rework, Input, and Output Termination Options ....................................................................... 132-5. Evaluation Module Default, Power Distribution......................................................................... 152-6. Evaluation Module Default, Device Connection ........................................................................ 16A-1. Schematics, Clock Generator............................................................................................. 20A-2. Schematics, Inputs ......................................................................................................... 21A-3. Schematics, Outputs ....................................................................................................... 22A-4. Schematics, Control Pins.................................................................................................. 23A-5. Schematics, Power Distribution .......................................................................................... 24A-6. Schematics, Power......................................................................................................... 25A-7. Schematic, USB Interface................................................................................................. 26A-8. Schematic, EVM Hardware ............................................................................................... 27A-9. Schematic, Block Guidance............................................................................................... 28A-10. Layout, Assembly Top ..................................................................................................... 30A-11. Layout, Assembly Bottom ................................................................................................. 31A-12. Layout, Top Layer .......................................................................................................... 32A-13. Layout, Middle Layer 1 .................................................................................................... 33A-14. Layout, Middle Layer 2 .................................................................................................... 34A-15. Layout, Bottom Layer ...................................................................................................... 35
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List of Tables
List of Tables2-1. Input Connection Options ................................................................................................. 102-2. Output Connection Options, Example for Y1 Channel Soldered Termination ..................................... 122-3. Power Supply Option Examples.......................................................................................... 142-4. Power Distribution .......................................................................................................... 14A-1. Stack-Up..................................................................................................................... 29
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Introduction
PrefaceSNAU202B–July 2017–Revised October 2018
Introduction
The CDCI6214EVM is an evaluation platform for the CDCI6214 Ultra-Low Power Clock Generator. Thisevaluation module provides an USB-based interface to access the I2C bus to communicate with theCDCI6214 as well as its control pins and the power supply. The edge-launch SMA-connectors enablemeasurements using 50-Ω equipment while the onboard termination allows to use high impedance probes.The flexible re-work options allow to adapt the evaluation module to many application-specificrequirements for rapid prototyping.
Features• CDCI6214
– Single high-performance phase-locked-loop– Ultra-low power operation– Supports mixed power supply operation from 1.8 V to 3.3 V– Four differential outputs with multi-mode output buffers– One LVCMOS bypass output– Crystal oscillator with integrated load capacitance and configurable gain– LVCMOS or AC-coupled differential reference input– Output divider synchronization and digital delays– General-purpose inputs and outputs for individual output enable and status signals– I2C programming interface– Integrated EEPROM with two pages
• Evaluation Module– Power distribution network to choose from
• Low-noise LDO• High-efficiency DC-DC switcher
– Level-shifters to adapt programming interface so selected supply voltage– Onboard input and output termination options– Flexible footprint for four pin SMD crystals
What's Included• CDCI6214EVM• Micro-USB cable
What's Required• Windows-based computer for supplied graphical user interface - TICS Pro• Measurement equipment
– Oscilloscope– Spectrum analyzer or phase noise analyzer– Digital Multi-meter
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Setup Procedure
Chapter 1SNAU202B–July 2017–Revised October 2018
Setup Procedure
1.1 Quick StartThe evaluation module is powered either from the USB port or using an external 5-V supply for moreflexibility. By default the device operates from USB and is supplied with 1.8 V from the onboard LDO. Thecontrol pins of the device can be set using shunts for the respective pullup and pulldown option on the pinheaders in the center of the evaluation module. The control signals are alternatively steered using theTICS Pro graphical user interface which is available free of charge on the TI website.
Figure 1-1. CDCI6214EVM
NOTE: The SMA_XOUT connector drives XIN/FB_N (pin 2) and the SMA_XIN connector drivesXOUT/FB_P (pin 1).
1. Cross-check the default EVM configuration using Figure 2-1. Ensure the correct position of the controlpin signals and the connections to the device and the input reference.
2. Install the newest version of the TICS Pro software from http://www.ti.com/tool/ticspro-sw.3. Load the CDCI6214 device profile in the CDC Devices category using the Select Device menu.4. Connect the USB cable to the EVM and the computer. At the bottom of the screen you will observe a
green status indicator with the protocol set to I2C.5. Press the button Power Off and observe the button change to Power On.6. Press the button Find Device. You are connected to the device and can program its registers.7. At the top of the screen, choose Default Configuration and select EVM Default.
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Setup Procedure
8. Press the button Lock? to poll the lock detector status bit. You can also press the toolbar button ReadAll Registers to obtain more detailed information under User Controls.
9. The clocks outputs can be observed now, providing 100 MHz generated using the onboard 25-MHzcrystal.
1.1.1 Default Configuration
• Input: 25-MHz crystal• Supplies: all 1.8-V LDO• Outputs:
– Soldered on termination: Y2, Y3 AC-coupled LVPECL.– Scope with 50-Ω termination: Y1, Y4 DC-connection.
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Evaluation Module Configuration
Chapter 2SNAU202B–July 2017–Revised October 2018
Evaluation Module Configuration
2.1 Device Under TestThe evaluation module is shipped with a soldered down unit. The position of pin 1 of the 24-pin VQFNpackage is indicated by a silkscreen symbol as well as the reference designator U1.
2.2 Control PinsEach control pin is set by two options:1. MSP430 micro-controller through level shifters controlled by TICS Pro GUI2. Computer-independent control using pin header shunts with onboard pullup and pulldown resistors.
TICS Pro Control:For software-based control, the shunts should be removed. Ensure that, when a device GPIO pin isconfigured as an output, the signal does not collide with the micro-controller signal. The connection tothe level-shifter can, therefore, be disconnected using the solder bridges: R157, R173, R174, R188,and R190.
Independent Control:The connection to the level-shifter should be disconnected using the solder bridges: R157, R173,R174, R188, and R190. Alternatively, the enable pins of the level-shifters can be tied to the disabledstate using: R162, R177, R179, R191, and R193. The shunts of the pin headers are used to tie eachpin to VDDREF or to GND.
The relevant sections of the evaluation module are shown in Figure 2-1 and Figure 2-2.
Figure 2-1. Evaluation Module Default, Control Pins
www.ti.com Reference Input
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Evaluation Module Configuration
Figure 2-2. Evaluation Module Default, Control Pin Level Shifters
2.3 Reference InputThe device offers multiple-input stages:1. Crystal Oscillator2. LVCMOS3. Differential AC-Coupled
The evaluation module supports all of these options. By default the board is assembled for crystaloperation. the crystal is situated on the bottom side of the PCB. It connects to the top layer with R17 andR19. See Table 2-1, Figure 2-3 and Figure 2-4 for more information. Two four-pad SMD footprints areoverlaid on the bottom side of the evaluation module that eases to populate 3.2-mm × 2.5-mm as well as2.0-mm × 1.6-mm crystals.
Reference Input www.ti.com
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Evaluation Module Configuration
(1) Depending on the crystal specifications, it may be required to adapt the series resistance R17 to stay within the power limit of the crystalfor the set drive current, see bit-field ip_xo_gm..
(2) For very strong LVCMOS drivers it is recommended to use C5 population option for a series resistance to adapt to the trace impedanceand reduce reflections at the device input.
Table 2-1. Input Connection Options
INPUT TYPE POPULATE DEPOPULATE
Crystal
R15 = 0 Ω
R13, R14, R21R17 = 10 Ω (1)
R19 = 0 Ω
R22 = 0 Ω
LVCMOS
C5 = 0 Ω (2)
R13, R18, R17, R19
C7 = 0 Ω
R14 = 0 Ω
R15 = 0 Ω
R21 = 0 Ω
R22 = 0 Ω
Differential AC-Coupled
C5 = 100 nF
R13, R17, R19
C7 = 100 nFR14 = 0 Ω
R15 = 0 Ω
R18 = 100 Ω
R21 = 0 Ω
R22 = 0 Ω
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Evaluation Module Configuration
Figure 2-3. Evaluation Module Default, Reference Connection
Clock Outputs www.ti.com
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Evaluation Module Configuration
2.4 Clock OutputsThe evaluation module is flexible for the various output formats the device supports.
Table 2-2. Output Connection Options, Example for Y1 Channel Soldered Termination
INPUT TYPE POPULATE DEPOPULATE
LVDS
R28 = 49.9 Ω
C10, C16, R32, R36R30 = 0 Ω
R34 = 49.9 Ω
R38 = 0 Ω
LVDS, AC-Coupled
R28 = 49.9 Ω
C10, C16, R32, R36R30 = 100 nFR34 = 49.9 Ω
R38 = 100 nF
CML, AC-Coupled
R28 = 49.9 Ω
C10, C16, R32, R36R30 = 100 nFR34 = 49.9 Ω
R38 = 100 nF
LVPECL, AC-Coupled
R28 = 49.9 Ω
C10, C16, R32, R36R30 = 100 nFR34 = 49.9 Ω
R38 = 100 nF
HCSL
R28 = 49.9 Ω
C10, C16, R36R30 = 0 Ω
R34 = 49.9 Ω
R38 = 0 Ω
R32 = 0 Ω
LVCMOS,
R28 = 2 pF
R34, R38, C16R30 = 22 Ω
R32 = 0 Ω
C10 = 499 Ω with SMA short
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Evaluation Module Configuration
Figure 2-4. Rework, Input, and Output Termination Options
NOTE: The SMA_XOUT connector drives XIN/FB_N (pin 2) and the SMA_XIN connector drivesXOUT/FB_P (pin 1).
2.5 Power SuppliesThe EVM is supplied using the USB 5-V rail by default. In this configuration only a single LDO or the DC-DC switcher can be used. For mixed power supplies, TI recommends using the external 5-V option usingJ1 wire connector.
NOTE: The onboard power regulators are alternatively supplied from either USB 5 V or an externallysupplied 5 V. Before an external supply is connected to J1, the connection to the USB supplyhas to be disconnected by removing J23.
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Evaluation Module Configuration
The onboard regulators have enable signals which can be connected to a common micro-controller signalcontrolled through the TICS Pro software. The regulators can be enabled or disabled by default using apin-strap option.
(1) Legend: "blank" = switch set to OFF. "+" = shunt set to EN position. "-" shunt set to disable position.(2) As there is a shared enable signal: all shunts must have the same setting when connected using the switch. Otherwise they
must be disconnected. E.g. only per default enabled signals are connected or only disabled signals.(3) By default set to 1.8 V.
Table 2-3. Power Supply Option Examples (1) (2)
DESCRIPTION
5 V DC-DC,ADJUSTABLE (3) LDO, 1.8 V LDO, 2.5 V LDO, 3.3 V
J1 J23SW EN DIS SW EN DIS SW EN DIS SW EN DIS
S2 J27 J27 S2 J26 J26 S2 J25 J25 S2 J24 J24
USB only, 1.8 V, LDO, Default no connect close 3-6on - + - -
USB only, 1.8 V, DC-DC no connect close 4-5on + - - -
External supply, 1.8 V, DC-DC connect open 4-5on + - - -
External supply, 1.8 V, DC-DC,3.3-V LDO connect open 4-5
on + - - 1-8on +
External supply, 1.8 V, DC-DC,1.8-V to 3.3-V LDO connect open 4-5
on + 3-6on + 2-7
on + 1-8on +
NOTE: For USB-only operation, only a single power regulator is recommended to be enabled at atime. The other regulators, shall be kept disabled using the pin-strap options.
The clock generator offers four separate supply domains for each block of the device. The supplies can bemixed using 1.8 V, 2.5 V, or 3.3 V. Each supply is selected using a resistor solder option on the bottomside of the evaluation module.
NOTE: For each supply only one resistor may be populated at a time.
(1) For mixed configurations, the 5 V is recommended to be supplied externally using J1 connector.
Table 2-4. Power Distribution (1)
SUPPLY
VDDREF VDDVCO VDDO12 VDDO34
DC-DC
LDO,1.8 V
LDO,2.5 V
LDO,3.3 V
DC-DC
LDO,1.8 V
LDO,2.5 V
LDO,3.3 V
DC-DC
LDO,1.8 V
LDO,2.5 V
LDO,3.3 V
DC-DC
LDO,1.8 V
LDO,2.5 V
LDO,3.3 V
R92 R91 R90 R89 R110 R109 R108 R107 R100 R99 R98 R97 R114 R113 R112 R111
1.8 V, LDO, Default x x x x
1.8 V, DC-DC x x x x
Voltage Translation 3.3 V → 1.8V, LDO + DC-DC x x x x
Voltage Translation 1.8 V → 2.5V, LDOs x x x x
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Evaluation Module Configuration
Figure 2-5. Evaluation Module Default, Power Distribution
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Evaluation Module Configuration
Each supply has multiple options for local decoupling and noise reduction using ferrite beads which canbe optimized for custom frequency plans.
Figure 2-6. Evaluation Module Default, Device Connection
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Frequently Asked Questions - FAQ
Chapter 3SNAU202B–July 2017–Revised October 2018
Frequently Asked Questions - FAQ
3.1 Troubleshooting
Question: Suggestion:I want to measure the currentconsumption of the device. Where can Ido that?
For a first-order estimate, the best option is to use anexternal 5-V supply with current measurement option.Remove J23 before you connect to J1.The individual supplies have ferrite beads for better noiseisolation. Next to each ferrite are two full-through VIAs whichcan be used to solder in a current probe with the ferrite beadremoved. Alternatively, a shunt resistor can be populatedhere on resistors like R100.
I programmed the unit and I see thatthe PLL lock detector status bit shows alocked PLL, but I do not get any outputsfrom the device.
Check if you configured one of the GPIOs as a output enablepin. Maybe the signal is set to GND or TICS Pro still driveslow level to the pin.
I click in the software or I set theRESETN/SYNC pin to low, but thedevice keeps active.
GPIO0 might be configured as status output. Thus the onlyway to reset the device is a power-cycle on VDDREF.
I tried different slave addresses andpower cycled the device. Nothingmakes the serial interface work! Is theunit broken?
The EEPROM of the unit may contain a configuration whichdisables the serial interface and instead uses the pins asoutput enable pins. Does the unit start reacting when you setEEPROMSEL to GND or VDDREF, followed by a power-cycle with RESETN at VDDREF level? REFSEL must alwaysbe tied to GND when doing this.When the unit does not react, both EEPROM pages seem tohave disabled the interface. Enter Fallback-Mode to force theserial interface active. Remove any shunts from J19 and J22and configure the pins in TICS Pro to Hi-Z state. When youdo not use the software, disconnect the level shifters byremoving R174 and R190. This leaves EEPROMSEL andREFSEL pin floating. Power-cycle the unit and ensure thatRESETN/SYNC pin (J16) sees a VDDREF level. Either byusing TICS Pro to drive the level or using a shunt on J16-2-3.You should see that the device responds on slave address0x74.
The device does not draw current anycurrent. Also the regulators seem not tobe operating.
Cross-check Table 2-3 for the switch and shunt settings. Theenable signal might be blocked by a wrong setting.
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Frequently Asked Questions - FAQ
I want to test the zero delay mode tominimize the phase delay betweeninput clock and output clocks. Can I dothis on this EVM?
Yes, you can evaluate zero delay mode on this EVM.You are going to need a set of very well flight-time matched50 Ω SMA cables with at least six pieces.• Connect REF inputs to the clock source.• It can be advantageous to buffer in the clock source using
a dedicated buffer part, to generate another clock copy forviewing on a scope.
• Connect Y2P to FB_P and Y2N to FB_N and rework theEVM with AC-coupling on C5, C7 and with R14=R21= 0 Ωand R17, R19 depopulated.
• Connect Y3 to the scope.• Enable the input clock source.• Configure the device for your frequency plan and ensure
the input and output buffers match.• Ensure that the reference divider to the PLL is set to
division "/1".• Ensure that the Y2 output frequency matches the input
frequency at REF.• Set zdm_clocksel = 1 (external feedback), zdm_auto = 1,
ref_mux_src = 1, ref_mux = 1 and then zdm_mode = 1.Re-calibrate the PLL using recal = 1.
• You will see that the device operates in zero delay mode.In zero delay mode the least delay is achieved using eachoutput channels own integer divider.When you test the zero delay mode with internal feedback:this happens using Y2. Any inherent delay from the PLLsetup and input path can be minimized using the digital delayin the output channels. You will have to introduce an offsetbetween feedback output Y2 and the Y1,Y3,Y4 which driveactual receivers.
I tried the divider synchronization andnow all the outputs are muted. What didI do?
Cross-check the following: The input muxes of the integerdividers in each of the output channels must have a valid(=active) pre-scaler clock selected. Moreover thech[4:1]_sync_en bits must be set. Moreover check the actualblock power down bits if the required pre-scaler clock treeand the output channel are active.
I evaluated the CDCI6214 clockgenerator and I am designing my ownapplication board. Until I've finished myproduction program, how do yourecommend to program first samples formy application prototypes?
For few units you could use the EVM and wire it into yourapplication. To wire the serial interface from the EVM to yourapplication board. Replace R176, R197 using 0 Ω. Then youcan wire J17, J21 to your application. Should you need apower supply as well, you can insert J28 to access anadditional output port of the DC/DC-switcher.For larger amounts we recommend to design your applicationboard including an in-system programming option, when yoursystem allows it. This evaluation module can be used asreference for the control pin pin-strap options.When you want to omit any in-system programming and takeadvantage of the factory-pre-programmed devices, pleasecontact your TI representative for options.
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References
Appendix ASNAU202B–July 2017–Revised October 2018
References
A.1 SoftwareTo download the latest newest version of the TICS Pro software, go to http://www.ti.com/tool/ticspro-sw.
The device profile for the EVM is available in the "Clock Generator-Jitter Cleaner (Single Loop)" categoryfor the clock generator "CDCI6214".
EVM Schematics www.ti.com
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References
A.2 EVM Schematics
Figure A-1. Schematics, Clock Generator
www.ti.com EVM Schematics
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References
Figure A-2. Schematics, Inputs
Y0
Y1P
Y1N
Y2P
Y2N
Y3P
Y3N
Y4P
Y4N
1
2345
SMA_Y1P
AGND
12345
SMA_Y1N
AGND
49.9R28
DNP
49.9R34
DNPAGND
0
C16
0
C10
1
2345
SMA_Y2P
DNP
AGND
1
2345
SMA_Y2N
DNP
AGND
49.9R42
49.9R48
0
R46DNP
AGND
0.1µF
C24
DNP
0.1µF
C18
DNP
1
2345
SMA_Y3P
DNP
AGND
1
2345
SMA_Y3N
DNP
AGND
49.9R29
49.9R35
0
R33DNP
AGND
0.1µF
C17
DNP
0.1µF
C11
DNP
1
2345
SMA_Y4P
AGND
1
2345
SMA_Y4N
AGND
49.9R43
DNP
49.9R49
DNP
0
R47DNP
AGND
0
C25
0
C19
AGND
1
2345
SMA_Y0
0
R23
0
R30
0
R38
0.1µF
R44
0.1µF
R52
0.1µF
R31
0.1µF
R39
0
R45
0
R53
5pFC9DNP
0
R24
AGND
Y1_SMA_P
Y1_SMA_N
Y2_SMA_P
Y2_SMA_N
Y3_SMA_P
Y3_SMA_N
Y4_SMA_P
Y4_SMA_N
Text String Text String
0
R32DNP
EVM Default
-------------------------------------------------------
| | |
| Y1 HCSL 50 Ohm scope | Y3 AC-LVPECL Hi-Z Probe |
| | |
-------------------------------------------------------
| | |
| Y2 AC-LVPECL Hi-Z Probe | Y4 HCSL 50 Ohm scope |
| | |
-------------------------------------------------------
0
R36DNPXIN_Y1_P
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EVM Schematics www.ti.com
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References
Figure A-3. Schematics, Outputs
VDD_REF_PLANE
GND
GND
+3.3V
1.00kR160
1.00kR161
GND GND
1.00kR158
DNP 1.00kR159
DNP
GND GND
4.7µF0402
C8922µF0603
C88
2
1
4
53
U14SN74LV1T126DCKR
GND
GPIO1
GND
GND
AGND
2
1
4
53
U16SN74LV1T126DCKR
GND
GPIO4
GND
GND
AGND
GND
GPIO2
GND
AGND
GPIO3
GND
5pFC101
5pFC106DNP
5pFC102DNP
2
1
4
53
U10SN74LV1T126DCKR
VDD_REF_PLANE
GND
RESETN_SYNC
GND
GND
AGND
5pFC91
VDD_REF_PLANE
VDD_REF_PLANE
2
1
4
53
U15SN74LV1T126DCKR
GND
EEPROMSEL
GND
GND
2
1
4
53
U18SN74LV1T126DCKR
GND
REFSEL
GND
GND
VDD_REF_PLANE
VDD_REF_PLANE
123
J19
AGNDVDDREF
123
J22
AGNDVDDREF
123
J21
AGNDVDDREF
123
J17
AGNDVDDREF
123
J20
AGNDVDDREF
123
J18
AGNDVDDREF
0R167
SDA_MSP430
SCL_MSP430
SOMI_MSP430
SCLK_MSP430
EEPROMSEL_LH_MSP430
EEPROMSEL_M_MSP430
REFSEL_LH_MSP430
REFSEL_M_MSP430
SCS_MSP430
SIMO_MSP430
RESETN_SYNC_MSP430
GND
VCCA1
SCLA2
SDAA3
GND4
EN5
SDAB6
SCLB7
VCCB8
U11
TCA9617BDGKR
SCL_DUT
SDA_DUT
+3.3V VDD_REF_PLANE
AGND
+3.3V
GND
123
J16
AGNDVDDREF
1
2345
SMA_FREQCNT
142-0701-806
DNP
SMA_FREQCNT
0.1µF
C96
0.1µF
C97
0.1µF
C90
0.1µF
C99
0.1µF
C103
0.1µF
C105
0.1µF
C100
0.1µF
C87
120pFC92DNP
120pFC93DNP
120pFC94DNP
120pFC95DNP
51kR169
51kR177
DNP
51kR185
51kR191
DNP
51kR192
51kR184
51kR178
51kR168
51kR170
DNP
51kR179
51kR186
51kR193
DNP
4.7kR156
4.7kR154
51kR155
51kR162
DNP
4.99
R157
4.7kR163
4.7kR164
4.7kR182
4.7kR183
4.7kR198
4.7kR199
4.7kR196
4.7kR197
4.7kR194
4.7kR195
4.7kR180
4.7kR181
4.7kR175
4.7kR176
4.99
R188
4.99
R189
4.99
R174
4.99
R190
4.99
R173
4.99
R172
VCCA7
A18
A29
GND3
DIR110
DIR21
B24
B15
OE2
VCCB6
U13
SN74AVC2T245RSWR
GPIOEN_MSP430
----------------------
| !OE | DIR | Signal |
----------------------
| L | H | A-->B |
| L | L | A<--B |
| H | X | Hi-Z |
----------------------
123
J31
+3.3V
123
J32
GND+3.3V
J29
0
R187DNP
0
R8
J30
GPIOEN_MSP430
GPIOEN_MSP430
0R165
0R166
0
R171
0
R7
Copyright © 2017, Texas Instruments Incorporated
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Figure A-4. Schematics, Control Pins
VDDREF
VDDVCO
VDDO1
VDDO3
VDDO2
VDDO4
VDD_LDO_1V8
VDD_LDO_2V5
VDD_LDO_3V3
VDD_ADJ_DCDC
VDD_ADJ_LDO
0.01
R101
0.01
R104DNP
0.01R89
DNP
1 2
3 4
5 6
7 8
J2
DNP
0.01R90
DNP 0.01R91
0.01R92
DNP
VDD_REF_PLANE
VDD_REF_PLANE220 ohm
FB1
0.47µFC44
4.7µFC43
GND AGND
220 ohm
FB4
VDD_LDO_1V8
VDD_LDO_2V5
VDD_LDO_3V3
VDD_ADJ_DCDC
VDD_ADJ_LDO
0.01
R119
0.01
R122DNP
0.01R107
DNP
1 2
3 4
5 6
7 8
J8
DNP
0.01R108
DNP 0.01R109
0.01R110
DNP
VDD_VCO_PLANE
VDD_VCO_PLANE220 ohm
FB8
0.47µFC68
4.7µFC67
GND AGND
220 ohm
FB11
VDD_LDO_1V8
VDD_LDO_2V5
VDD_LDO_3V3
VDD_ADJ_DCDC
VDD_ADJ_LDO
0.01
R120
0.01
R123DNP
0.01R111
DNP
1 2
3 4
5 6
7 8
J9
DNP
0.01R112
DNP 0.01R113
0.01R114
DNP
VDD_O3_PLANE
VDD_O3_PLANE220 ohm
FB9
0.47µFC74
4.7µFC73
GND AGND
220 ohm
FB12
VDD_LDO_1V8
VDD_LDO_2V5
VDD_LDO_3V3
VDD_ADJ_DCDC
VDD_ADJ_LDO
0.01
R121
0.01
R124DNP
0.01R115
DNP
1 2
3 4
5 6
7 8
J10
DNP
0.01R116
DNP 0.01R117
0.01R118
DNP
VDD_O4_PLANE
VDD_O4_PLANE220 ohm
FB7
0.47µFC62
4.7µFC61
GND AGND
220 ohm
FB10
VDD_LDO_1V8
VDD_LDO_2V5
VDD_LDO_3V3
VDD_ADJ_DCDC
VDD_ADJ_LDO
0.01
R102
0.01
R105DNP
0.01R93
DNP
1 2
3 4
5 6
7 8
J3
DNP
0.01R94
DNP 0.01R95
0.01R96
DNP
VDD_O1_PLANE
VDD_O1_PLANE220 ohm
FB2
0.47µFC50
4.7µFC49
GND AGND
220 ohm
FB5
VDD_LDO_1V8
VDD_LDO_2V5
VDD_LDO_3V3
VDD_ADJ_DCDC
VDD_ADJ_LDO
0.01
R103
0.01
R106DNP
0.01R97
DNP
1 2
3 4
5 6
7 8
J4
DNP
0.01R98
DNP 0.01R99
0.01R100
DNP
VDD_O2_PLANE
VDD_O2_PLANE220 ohm
FB3
0.47µFC56
4.7µFC55
GND AGND
220 ohm
FB6
VDDREF VDDO1 VDDO2
VDDO4
VDDO3VDDVCO
J5
GRPB021VWVN-RC
DNP
J6
GRPB021VWVN-RC
DNP
J7
GRPB021VWVN-RC
DNP
J11
GRPB021VWVN-RC
DNPJ13
GRPB021VWVN-RC
DNP
J12
GRPB021VWVN-RC
DNP
0.1µFC41
0.1µFC65
0.1µFC71
0.1µFC47
0.1µFC53
0.1µFC59
0.1µFC45
0.1µFC51
0.1µFC57
0.1µFC63
0.1µFC75
0.1µFC69
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Figure A-5. Schematics, Power Distribution
7.5V
D11SMB5922BT3G4.7µF
C26 33k
R55
0.1µFC29
USB_VBUS
GND
+3.3V
10µFC27
1000 ohm
L1
J1
1776275-2
7.5V
D21SMB5922BT3G
GND
0.1µFC30
1000 ohm
L25V
VIN1
GND2
EN3
N/C4
VOUT5
U2
LP5907MFX-3.3/NOPB
VIN1
GND2
EN3
N/C4
VOUT5
U3
LP5907MFX-3.3/NOPB
VIN1
GND2
EN3
N/C4
VOUT5
U5
LP5907MFX-1.8/NOPB
VIN1
GND2
EN3
N/C4
VOUT5
U4
LP5907MFX-2.5/NOPB
IN3
OUT2
ADJ1
U7
LM317LIPK
DNP
VIN1
SW2
GND3
CTRL4
VOUT5
LOAD6
PG7
VSEL48
VSEL39
VSEL210
VSEL111
EN12
PAD13
U6
TPS62740DSSR
2.2µH
L3
5V
GND5V
DCDC_ENGND
1.0M
R7310µF0603
C38
1.0M
R75DNP
GND
TPS62_VSEL1TPS62_VSEL2TPS62_VSEL3TPS62_VSEL4
TPS62_VSEL4 TPS62_VSEL3 TPS62_VSEL2 TPS62_VSEL1 Select one combination:
------------------------
| VOUT | 4 | 3 | 2 | 1 |
------------------------
| 1.8 V| 0 | 0 | 0 | 0 |
| 2.5 V| 0 | 1 | 1 | 1 |
| 3.3 V| 1 | 1 | 1 | 1 |
------------------------
CTRL=L LOAD o- x -o VOUT
CTRL=H LOAD o-----o VOUT
VDD_ADJ_DCDC
4.7µFC40DNP
5V1000 ohm
L4DNP
0.1µFC39DNP
GND
<= 400 mA <= 100 mA
<= 250 mA
1µFC28
10µF
C37
1µFC31
5V
GND
4.7µFC32
VDD_LDO_3V3
1µFC33
5V
GND
4.7µFC34
VDD_LDO_2V5
1µFC35
5V
GND
4.7µFC36
VDD_LDO_1V8
GND
GND
GND
<= 250 mA
<= 250 mA
<= 250 mA
VDD_ADJ_DCDC VDD_ADJ_LDOVDD_ADJ_LDO
VDD_LDO_1V8
VDD_LDO_2V5
VDD_LDO_3V3
GND
+3.3V
DUT_PWR_EN_MSP430
LDO_3V3_EN
LDO_2V5_EN
LDO_1V8_EN
5V_LM
51kR77
DNP 51kR78
51kR79
DNP 51kR80
51kR81
DNP 51kR82
51kR83
DNP 51kR84
1.00k
R85DNP
1.58kR86
DNP
51k
R58DNP
51k
R63DNP
51k
R72DNP
VBUS_FB
VBUS_FB
1.0M
R74
Populate R86 feedback pull-down:
-----------------------------
| VDD_ADJ_LDO | Res in Ohm |
-----------------------------
| 1.8 V | 442 |
| 2.5 V | 953 |
| 3.3 V | 1580 |
-----------------------------
123
J24
123
J25
123
J26
123
J27
51kR64
51kR65
51kR66
51kR67
631
8
27 5
4
S2TDA04H0SB1
DCDC_ENLDO_1V8_ENLDO_2V5_EN
LDO_3V3_EN
0.01
R57DNP
J23
OUT1
GND2
OC3
EN4
IN5
U12
TPS2051BDBVR
33k
R5 TP1DNP
J28
DNP
0
R6DNP
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Figure A-6. Schematics, Power
GND
USB_VBUS VBUS1
D-2
D+3
ID4
GND5
6 7 8
11
10
9
J15
220pFC86
1.47kR143
PUR
VUSB
LABEL SW: BSL
33 0402R142
33 0402R141
VCC1
NC2
IO13
GND4
IO25
U9
TPD2E001DRLR
USB_VBUS
GND
33k
R145
+3.3V
MSP_GPIO1/I2C(SCL)
GPIO5/SPI(SOMI)/UART(RXD)
0.1µFC85
GND
0.47µF
C82
GND
P6.4/CB4/A41
P6.5/CB5/A52
P6.6/CB6/A63
P6.7/CB7/A74
P7.0/CB8/A125
P7.1/CB9/A136
P7.2/CB10/A147
P7.3/CB11/A158
P5.0/A8/VREF+/VEREF+9
P5.1/A9/VREF-/VEREF-10
AVCC111
P5.4/XIN12
P5.5/XOUT13
AVSS114
P8.015
P8.116
P8.217
DVCC118
DVSS119
VCORE20
P1.0/TA0CLK/ACLK21
P1.1/TA0.022
P1.2/TA0.123
P1.3/TA0.224
P1.4/TA0.325
P1.5/TA0.426
P1.6/TA1CLK/CBOUT27
P1.7/TA1.028
P2.0/TA1.129
P2.1/TA1.230
P2.2/TA2CLK/SMCLK31
P2.3/TA2.032
P2.4/TA2.133
P2.5/TA2.234
P2.6/RTCCLK/DMAE035
P2.7/UCB0STE/UCA0CLK36
P3.0/UCB0SIMO/UCB0SDA37
P3.1/UCB0SOMI/UCB0SCL38
P3.2/UCB0CLK/UCA0STE39
P3.3/UCA0TXD/UCA0SIMO40
P3.4/UCA0RXD/UCA0SOMI41
P3.5/TB0.542
P3.6/TB0.643
P3.7/TB0OUTH/SVMOUT44
P4.0/PM_UCB1STE/PM_UCA1CLK45
P4.1/PM_UCB1SIMO/PM_UCB1SDA46
P4.2/PM_UCB1SOMI/PM_UCB1SCL47
P4.3/PM_UCB1CLK/PM_UCA1STE48
DVSS249
DVCC250
P4.4/PM_UCA1TXD/PM_UCA1SIMO51
P4.5/PM_UCA1RXD/PM_UCA1SOMI52
P4.6/PM_NONE53
P4.7/PM_NONE54
P5.6/TB0.055
P5.7/TB0.156
P7.4/TB0.257
P7.5/TB0.358
P7.6/TB0.459
P7.7/TB0CLK/MCLK60
VSSU61
PU.0/DP62
PUR63
PU.1/DM64
VBUS65
VUSB66
V1867
AVSS268
P5.2/XT2IN69
P5.3/XT2OUT70
TEST/SBWTCK71
PJ.0/TDO72
PJ.1/TDI/TCLK73
PJ.2/TMS74
PJ.3/TCK75
RST/NMI/SBWTDIO76
P6.0/CB0/A077
P6.1/CB1/A178
P6.2/CB2/A279
P6.3/CB3/A380
U8
MSP430F5529IPN
GND
+3.3V
GND
GPIO2/SPI(SCLK)
MSP_GPIO0/I2C(SDA)
GND
0.1µF
C80
GND
0.1µF
C79EXT5V_EN
EXT5V_FAULT
EXT3.3V_EN
EXT3.3V_FAULT
PURVBUS_FBVUSB
GND
30pF
C77
30pF
C78
GND+3.3V
2200pFC83
GND
33kR140
GND
0.1µFC84
24MHzY3
1
23
Q1BSS138
1 2
3 4
5 6
7 8
9 10
11 12
13 14
J14
N2514-6002-RB
DNP
300R134
GND
100kR144
MSP_GPIO1/I2C(SCL)
MSP_GPIO0/I2C(SDA)
I2CPU
+3.3V
1.47kR149
1.47kR150
1
23
Q32N7002W-7-F
3
1
2
Q2BSS223PWH6327
3
1
2
Q4BSS223PWH6327
GPIOEN_MSP430
EEPROMSEL_LH_MSP430
REFSEL_M_MSP430
REFSEL_LH_MSP430
SCS_MSP430
EEPROMSEL_M_MSP430
SDA_MSP430
SCL_MSP430
GPIO2/SPI(SCLK)
SIMO_MSP430
GPIO5/SPI(SOMI)/UART(RXD)
RESETN_SYNC_MSP430
DUT_PWR_EN_MSP430
USB_CON_D_N
USB_CON_D_P
USB_D_N
USB_D_P
1.2MegR146
220pFC81
S1
Green
12
D3
100k
R138
100k
R139
MSP_I2CPU
MSP_I2CPU
GPIOEN_TA0CLK
0
R125
0
R127
0
R133
0
R135
0
R147
0
R151
0
R152
0
R1370
R136
0
R126
0
R128
0 R130
0
R129
0 R131
0R132
0R153
0R148
VBUS_FB
JTAG
SCLK_MSP430
SOMI_MSP430
MSP430_EEPROMSELLH
MSP430_REFSELLHMSP430REFSELM
MSP430_SCS
MSP430_EEPROMSELM
MSP430_SCLK
MSP430_SIMOMSP430_SOMI
MSP430_SYNCMSP430_PWREN
Copyright © 2017, Texas Instruments Incorporated
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Figure A-7. Schematic, USB Interface
LOGOPCB
Texas Instruments
1
H1
NY PMS 440 0025 PH
1
H2
NY PMS 440 0025 PH
1
H3
NY PMS 440 0025 PH
1
H4
NY PMS 440 0025 PH
H5
1902C
H6
1902C
H7
1902C
H8
1902C
FID2
DNP
FID1
DNP
FID3
DNP
SV601290
A
PCB Number:
PCB Rev:
Label Assembly NoteZZ1
This Assembly Note is for PCB labels only
PCB Label
LBL1
Size: 0.65" x 0.20 "
Assembly NoteZZ2
These assemblies are ESD sensitive, ESD precautions shall be observed.
Assembly NoteZZ3
These assemblies must be clean and free from flux and all contaminants. Use of no clean flux is not acceptable.
Assembly NoteZZ4
These assemblies must comply with workmanship standards IPC-A-610 Class 2, unless otherwise specified.
Variant/Label Table
Variant Label Text
001 CDCI6214EVM
LOGOPCB
Pb-Free Symbol
LOGOPCB
FCC disclaimer
FID5
DNP
FID4
DNP
FID6
DNP
SH-J23
NPB02SVAN-RC
SH-J24
NPB02SVAN-RC
SH-J25
NPB02SVAN-RC
SH-J26
NPB02SVAN-RC
SH-J27
NPB02SVAN-RC
SH-J2_5-6
DNP
SH-J3_1-2
DNP
SH-J4_1-2
DNP
SH-J8_5-6
DNP
SH-J9_5-6
DNP
SH-J10_5-6
DNP
SH-J29
NPB02SVAN-RC
SH-J30
NPB02SVAN-RC
SH-J31
NPB02SVAN-RC
SH-J32
NPB02SVAN-RC
SH-J18
DNP
SH-J20
DNP
SH-J17
DNP
SH-J21
DNP
SH-J16_2-3 SH-J19_1-2
DNP
SH-J22_1-2
DNP
Copyright © 2017, Texas Instruments Incorporated
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Figure A-8. Schematic, EVM Hardware
Revision History
Rev NotesApproved byECN # Approved Date
N/A N/A N/A N/A N/A
CDCI6214EVM
CDCI6214
Soldered
Digital Ground Analog Ground
MSP430
USB2ANY
Firmware
Micro
USB
5V
Wire
option
LDO
LM317
(adj FB)
DCDC
TPS62740
(adj FB)
LDO
LP5907
(fix 1.8V)
LDO
LP5907
(fix 2.5V)
LDO
LP5907
(fix 3.3V)
Power
Distribution
(solder and pin
header option)
Control Pins
Pin header
options
and level
shifting
Crystal
(4 pin)
SMAs
SMAs
SMAs
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Figure A-9. Schematic, Block Guidance
www.ti.com EVM Layout
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A.3 EVM Layout
Table A-1. Stack-Up
NO. LAYER NAME MATERIAL THICKNESS IN m DIELECTRICCONSTANT DESCRIPTION
1 Top Solder solder resist 0.79 3.52 1 Top Layer copper 0.67 RF signals3 Dielectric 1 FR-4 12.21 4.24 2 Middle Layer 1 copper 1.38 Ground5 Dielectric 2 FR-4 31.50 4.86 3 Middle Layer 2 copper 1.38 Ground, power routing, control signals7 Dielectric 3 FR-4 12.21 4.28 4 Bottom Layer copper 0.67 Power routing, control signals9 Bottom Solder solder resist 0.79 3.5
EVM Layout www.ti.com
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Figure A-10. Layout, Assembly Top
www.ti.com EVM Layout
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Figure A-11. Layout, Assembly Bottom
EVM Layout www.ti.com
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Figure A-12. Layout, Top Layer
www.ti.com EVM Layout
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Figure A-13. Layout, Middle Layer 1
EVM Layout www.ti.com
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Figure A-14. Layout, Middle Layer 2
www.ti.com EVM Layout
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Figure A-15. Layout, Bottom Layer
Revision History www.ti.com
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Revision History
Revision HistoryNOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from A Revision (September 2017) to B Revision .......................................................................................... Page
• Added notice for silkscreen typo to Figure 1-1 ........................................................................................ 6• Added notice for silkscreen typo to Figure 2-4....................................................................................... 13• Changed "must" to "is recommended to" ............................................................................................. 14• Updated U7 symbol in Figure A-1 ..................................................................................................... 20• Updated the off sheet connectors on pins 1 and 2 in Figure A-1 ................................................................. 20• Updated the off sheet connectors on pins 1 and 2 in Figure A-2 ................................................................. 21
Changes from Original (July 2017) to A Revision ........................................................................................................... Page
• Changed EVM image from APL to production data release......................................................................... 6• Removed reference to socket option ................................................................................................... 8• Added "device" for clarification. ......................................................................................................... 8• Updated power supply options table to reflect switch and jumper name updates .............................................. 14• Changed USB-only operation note from "required" to "recommended". ......................................................... 14• Added more FAQ answers.............................................................................................................. 17• Added Figure A-8 and Figure A-9 ..................................................................................................... 27
STANDARD TERMS FOR EVALUATION MODULES1. Delivery: TI delivers TI evaluation boards, kits, or modules, including any accompanying demonstration software, components, and/or
documentation which may be provided together or separately (collectively, an “EVM” or “EVMs”) to the User (“User”) in accordancewith the terms set forth herein. User's acceptance of the EVM is expressly subject to the following terms.1.1 EVMs are intended solely for product or software developers for use in a research and development setting to facilitate feasibility
evaluation, experimentation, or scientific analysis of TI semiconductors products. EVMs have no direct function and are notfinished products. EVMs shall not be directly or indirectly assembled as a part or subassembly in any finished product. Forclarification, any software or software tools provided with the EVM (“Software”) shall not be subject to the terms and conditionsset forth herein but rather shall be subject to the applicable terms that accompany such Software
1.2 EVMs are not intended for consumer or household use. EVMs may not be sold, sublicensed, leased, rented, loaned, assigned,or otherwise distributed for commercial purposes by Users, in whole or in part, or used in any finished product or productionsystem.
2 Limited Warranty and Related Remedies/Disclaimers:2.1 These terms do not apply to Software. The warranty, if any, for Software is covered in the applicable Software License
Agreement.2.2 TI warrants that the TI EVM will conform to TI's published specifications for ninety (90) days after the date TI delivers such EVM
to User. Notwithstanding the foregoing, TI shall not be liable for a nonconforming EVM if (a) the nonconformity was caused byneglect, misuse or mistreatment by an entity other than TI, including improper installation or testing, or for any EVMs that havebeen altered or modified in any way by an entity other than TI, (b) the nonconformity resulted from User's design, specificationsor instructions for such EVMs or improper system design, or (c) User has not paid on time. Testing and other quality controltechniques are used to the extent TI deems necessary. TI does not test all parameters of each EVM.User's claims against TI under this Section 2 are void if User fails to notify TI of any apparent defects in the EVMs within ten (10)business days after delivery, or of any hidden defects with ten (10) business days after the defect has been detected.
2.3 TI's sole liability shall be at its option to repair or replace EVMs that fail to conform to the warranty set forth above, or creditUser's account for such EVM. TI's liability under this warranty shall be limited to EVMs that are returned during the warrantyperiod to the address designated by TI and that are determined by TI not to conform to such warranty. If TI elects to repair orreplace such EVM, TI shall have a reasonable time to repair such EVM or provide replacements. Repaired EVMs shall bewarranted for the remainder of the original warranty period. Replaced EVMs shall be warranted for a new full ninety (90) daywarranty period.
3 Regulatory Notices:3.1 United States
3.1.1 Notice applicable to EVMs not FCC-Approved:FCC NOTICE: This kit is designed to allow product developers to evaluate electronic components, circuitry, or softwareassociated with the kit to determine whether to incorporate such items in a finished product and software developers to writesoftware applications for use with the end product. This kit is not a finished product and when assembled may not be resold orotherwise marketed unless all required FCC equipment authorizations are first obtained. Operation is subject to the conditionthat this product not cause harmful interference to licensed radio stations and that this product accept harmful interference.Unless the assembled kit is designed to operate under part 15, part 18 or part 95 of this chapter, the operator of the kit mustoperate under the authority of an FCC license holder or must secure an experimental authorization under part 5 of this chapter.3.1.2 For EVMs annotated as FCC – FEDERAL COMMUNICATIONS COMMISSION Part 15 Compliant:
CAUTIONThis device complies with part 15 of the FCC Rules. Operation is subject to the following two conditions: (1) This device may notcause harmful interference, and (2) this device must accept any interference received, including interference that may causeundesired operation.Changes or modifications not expressly approved by the party responsible for compliance could void the user's authority tooperate the equipment.
FCC Interference Statement for Class A EVM devicesNOTE: This equipment has been tested and found to comply with the limits for a Class A digital device, pursuant to part 15 ofthe FCC Rules. These limits are designed to provide reasonable protection against harmful interference when the equipment isoperated in a commercial environment. This equipment generates, uses, and can radiate radio frequency energy and, if notinstalled and used in accordance with the instruction manual, may cause harmful interference to radio communications.Operation of this equipment in a residential area is likely to cause harmful interference in which case the user will be required tocorrect the interference at his own expense.
FCC Interference Statement for Class B EVM devicesNOTE: This equipment has been tested and found to comply with the limits for a Class B digital device, pursuant to part 15 ofthe FCC Rules. These limits are designed to provide reasonable protection against harmful interference in a residentialinstallation. This equipment generates, uses and can radiate radio frequency energy and, if not installed and used in accordancewith the instructions, may cause harmful interference to radio communications. However, there is no guarantee that interferencewill not occur in a particular installation. If this equipment does cause harmful interference to radio or television reception, whichcan be determined by turning the equipment off and on, the user is encouraged to try to correct the interference by one or moreof the following measures:
• Reorient or relocate the receiving antenna.• Increase the separation between the equipment and receiver.• Connect the equipment into an outlet on a circuit different from that to which the receiver is connected.• Consult the dealer or an experienced radio/TV technician for help.
3.2 Canada3.2.1 For EVMs issued with an Industry Canada Certificate of Conformance to RSS-210 or RSS-247
Concerning EVMs Including Radio Transmitters:This device complies with Industry Canada license-exempt RSSs. Operation is subject to the following two conditions:(1) this device may not cause interference, and (2) this device must accept any interference, including interference that maycause undesired operation of the device.
Concernant les EVMs avec appareils radio:Le présent appareil est conforme aux CNR d'Industrie Canada applicables aux appareils radio exempts de licence. L'exploitationest autorisée aux deux conditions suivantes: (1) l'appareil ne doit pas produire de brouillage, et (2) l'utilisateur de l'appareil doitaccepter tout brouillage radioélectrique subi, même si le brouillage est susceptible d'en compromettre le fonctionnement.
Concerning EVMs Including Detachable Antennas:Under Industry Canada regulations, this radio transmitter may only operate using an antenna of a type and maximum (or lesser)gain approved for the transmitter by Industry Canada. To reduce potential radio interference to other users, the antenna typeand its gain should be so chosen that the equivalent isotropically radiated power (e.i.r.p.) is not more than that necessary forsuccessful communication. This radio transmitter has been approved by Industry Canada to operate with the antenna typeslisted in the user guide with the maximum permissible gain and required antenna impedance for each antenna type indicated.Antenna types not included in this list, having a gain greater than the maximum gain indicated for that type, are strictly prohibitedfor use with this device.
Concernant les EVMs avec antennes détachablesConformément à la réglementation d'Industrie Canada, le présent émetteur radio peut fonctionner avec une antenne d'un type etd'un gain maximal (ou inférieur) approuvé pour l'émetteur par Industrie Canada. Dans le but de réduire les risques de brouillageradioélectrique à l'intention des autres utilisateurs, il faut choisir le type d'antenne et son gain de sorte que la puissance isotroperayonnée équivalente (p.i.r.e.) ne dépasse pas l'intensité nécessaire à l'établissement d'une communication satisfaisante. Leprésent émetteur radio a été approuvé par Industrie Canada pour fonctionner avec les types d'antenne énumérés dans lemanuel d’usage et ayant un gain admissible maximal et l'impédance requise pour chaque type d'antenne. Les types d'antennenon inclus dans cette liste, ou dont le gain est supérieur au gain maximal indiqué, sont strictement interdits pour l'exploitation del'émetteur
3.3 Japan3.3.1 Notice for EVMs delivered in Japan: Please see http://www.tij.co.jp/lsds/ti_ja/general/eStore/notice_01.page 日本国内に
輸入される評価用キット、ボードについては、次のところをご覧ください。http://www.tij.co.jp/lsds/ti_ja/general/eStore/notice_01.page
3.3.2 Notice for Users of EVMs Considered “Radio Frequency Products” in Japan: EVMs entering Japan may not be certifiedby TI as conforming to Technical Regulations of Radio Law of Japan.
If User uses EVMs in Japan, not certified to Technical Regulations of Radio Law of Japan, User is required to follow theinstructions set forth by Radio Law of Japan, which includes, but is not limited to, the instructions below with respect to EVMs(which for the avoidance of doubt are stated strictly for convenience and should be verified by User):1. Use EVMs in a shielded room or any other test facility as defined in the notification #173 issued by Ministry of Internal
Affairs and Communications on March 28, 2006, based on Sub-section 1.1 of Article 6 of the Ministry’s Rule forEnforcement of Radio Law of Japan,
2. Use EVMs only after User obtains the license of Test Radio Station as provided in Radio Law of Japan with respect toEVMs, or
3. Use of EVMs only after User obtains the Technical Regulations Conformity Certification as provided in Radio Law of Japanwith respect to EVMs. Also, do not transfer EVMs, unless User gives the same notice above to the transferee. Please notethat if User does not follow the instructions above, User will be subject to penalties of Radio Law of Japan.
【無線電波を送信する製品の開発キットをお使いになる際の注意事項】 開発キットの中には技術基準適合証明を受けていないものがあります。 技術適合証明を受けていないもののご使用に際しては、電波法遵守のため、以下のいずれかの措置を取っていただく必要がありますのでご注意ください。1. 電波法施行規則第6条第1項第1号に基づく平成18年3月28日総務省告示第173号で定められた電波暗室等の試験設備でご使用
いただく。2. 実験局の免許を取得後ご使用いただく。3. 技術基準適合証明を取得後ご使用いただく。
なお、本製品は、上記の「ご使用にあたっての注意」を譲渡先、移転先に通知しない限り、譲渡、移転できないものとします。上記を遵守頂けない場合は、電波法の罰則が適用される可能性があることをご留意ください。 日本テキサス・イ
ンスツルメンツ株式会社東京都新宿区西新宿6丁目24番1号西新宿三井ビル
3.3.3 Notice for EVMs for Power Line Communication: Please see http://www.tij.co.jp/lsds/ti_ja/general/eStore/notice_02.page電力線搬送波通信についての開発キットをお使いになる際の注意事項については、次のところをご覧ください。http://www.tij.co.jp/lsds/ti_ja/general/eStore/notice_02.page
3.4 European Union3.4.1 For EVMs subject to EU Directive 2014/30/EU (Electromagnetic Compatibility Directive):
This is a class A product intended for use in environments other than domestic environments that are connected to alow-voltage power-supply network that supplies buildings used for domestic purposes. In a domestic environment thisproduct may cause radio interference in which case the user may be required to take adequate measures.
4 EVM Use Restrictions and Warnings:4.1 EVMS ARE NOT FOR USE IN FUNCTIONAL SAFETY AND/OR SAFETY CRITICAL EVALUATIONS, INCLUDING BUT NOT
LIMITED TO EVALUATIONS OF LIFE SUPPORT APPLICATIONS.4.2 User must read and apply the user guide and other available documentation provided by TI regarding the EVM prior to handling
or using the EVM, including without limitation any warning or restriction notices. The notices contain important safety informationrelated to, for example, temperatures and voltages.
4.3 Safety-Related Warnings and Restrictions:4.3.1 User shall operate the EVM within TI’s recommended specifications and environmental considerations stated in the user
guide, other available documentation provided by TI, and any other applicable requirements and employ reasonable andcustomary safeguards. Exceeding the specified performance ratings and specifications (including but not limited to inputand output voltage, current, power, and environmental ranges) for the EVM may cause personal injury or death, orproperty damage. If there are questions concerning performance ratings and specifications, User should contact a TIfield representative prior to connecting interface electronics including input power and intended loads. Any loads appliedoutside of the specified output range may also result in unintended and/or inaccurate operation and/or possiblepermanent damage to the EVM and/or interface electronics. Please consult the EVM user guide prior to connecting anyload to the EVM output. If there is uncertainty as to the load specification, please contact a TI field representative.During normal operation, even with the inputs and outputs kept within the specified allowable ranges, some circuitcomponents may have elevated case temperatures. These components include but are not limited to linear regulators,switching transistors, pass transistors, current sense resistors, and heat sinks, which can be identified using theinformation in the associated documentation. When working with the EVM, please be aware that the EVM may becomevery warm.
4.3.2 EVMs are intended solely for use by technically qualified, professional electronics experts who are familiar with thedangers and application risks associated with handling electrical mechanical components, systems, and subsystems.User assumes all responsibility and liability for proper and safe handling and use of the EVM by User or its employees,affiliates, contractors or designees. User assumes all responsibility and liability to ensure that any interfaces (electronicand/or mechanical) between the EVM and any human body are designed with suitable isolation and means to safelylimit accessible leakage currents to minimize the risk of electrical shock hazard. User assumes all responsibility andliability for any improper or unsafe handling or use of the EVM by User or its employees, affiliates, contractors ordesignees.
4.4 User assumes all responsibility and liability to determine whether the EVM is subject to any applicable international, federal,state, or local laws and regulations related to User’s handling and use of the EVM and, if applicable, User assumes allresponsibility and liability for compliance in all respects with such laws and regulations. User assumes all responsibility andliability for proper disposal and recycling of the EVM consistent with all applicable international, federal, state, and localrequirements.
5. Accuracy of Information: To the extent TI provides information on the availability and function of EVMs, TI attempts to be as accurateas possible. However, TI does not warrant the accuracy of EVM descriptions, EVM availability or other information on its websites asaccurate, complete, reliable, current, or error-free.
6. Disclaimers:6.1 EXCEPT AS SET FORTH ABOVE, EVMS AND ANY MATERIALS PROVIDED WITH THE EVM (INCLUDING, BUT NOT
LIMITED TO, REFERENCE DESIGNS AND THE DESIGN OF THE EVM ITSELF) ARE PROVIDED "AS IS" AND "WITH ALLFAULTS." TI DISCLAIMS ALL OTHER WARRANTIES, EXPRESS OR IMPLIED, REGARDING SUCH ITEMS, INCLUDING BUTNOT LIMITED TO ANY EPIDEMIC FAILURE WARRANTY OR IMPLIED WARRANTIES OF MERCHANTABILITY OR FITNESSFOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF ANY THIRD PARTY PATENTS, COPYRIGHTS, TRADESECRETS OR OTHER INTELLECTUAL PROPERTY RIGHTS.
6.2 EXCEPT FOR THE LIMITED RIGHT TO USE THE EVM SET FORTH HEREIN, NOTHING IN THESE TERMS SHALL BECONSTRUED AS GRANTING OR CONFERRING ANY RIGHTS BY LICENSE, PATENT, OR ANY OTHER INDUSTRIAL ORINTELLECTUAL PROPERTY RIGHT OF TI, ITS SUPPLIERS/LICENSORS OR ANY OTHER THIRD PARTY, TO USE THEEVM IN ANY FINISHED END-USER OR READY-TO-USE FINAL PRODUCT, OR FOR ANY INVENTION, DISCOVERY ORIMPROVEMENT, REGARDLESS OF WHEN MADE, CONCEIVED OR ACQUIRED.
7. USER'S INDEMNITY OBLIGATIONS AND REPRESENTATIONS. USER WILL DEFEND, INDEMNIFY AND HOLD TI, ITSLICENSORS AND THEIR REPRESENTATIVES HARMLESS FROM AND AGAINST ANY AND ALL CLAIMS, DAMAGES, LOSSES,EXPENSES, COSTS AND LIABILITIES (COLLECTIVELY, "CLAIMS") ARISING OUT OF OR IN CONNECTION WITH ANYHANDLING OR USE OF THE EVM THAT IS NOT IN ACCORDANCE WITH THESE TERMS. THIS OBLIGATION SHALL APPLYWHETHER CLAIMS ARISE UNDER STATUTE, REGULATION, OR THE LAW OF TORT, CONTRACT OR ANY OTHER LEGALTHEORY, AND EVEN IF THE EVM FAILS TO PERFORM AS DESCRIBED OR EXPECTED.
8. Limitations on Damages and Liability:8.1 General Limitations. IN NO EVENT SHALL TI BE LIABLE FOR ANY SPECIAL, COLLATERAL, INDIRECT, PUNITIVE,
INCIDENTAL, CONSEQUENTIAL, OR EXEMPLARY DAMAGES IN CONNECTION WITH OR ARISING OUT OF THESETERMS OR THE USE OF THE EVMS , REGARDLESS OF WHETHER TI HAS BEEN ADVISED OF THE POSSIBILITY OFSUCH DAMAGES. EXCLUDED DAMAGES INCLUDE, BUT ARE NOT LIMITED TO, COST OF REMOVAL ORREINSTALLATION, ANCILLARY COSTS TO THE PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES, RETESTING,OUTSIDE COMPUTER TIME, LABOR COSTS, LOSS OF GOODWILL, LOSS OF PROFITS, LOSS OF SAVINGS, LOSS OFUSE, LOSS OF DATA, OR BUSINESS INTERRUPTION. NO CLAIM, SUIT OR ACTION SHALL BE BROUGHT AGAINST TIMORE THAN TWELVE (12) MONTHS AFTER THE EVENT THAT GAVE RISE TO THE CAUSE OF ACTION HASOCCURRED.
8.2 Specific Limitations. IN NO EVENT SHALL TI'S AGGREGATE LIABILITY FROM ANY USE OF AN EVM PROVIDEDHEREUNDER, INCLUDING FROM ANY WARRANTY, INDEMITY OR OTHER OBLIGATION ARISING OUT OF OR INCONNECTION WITH THESE TERMS, , EXCEED THE TOTAL AMOUNT PAID TO TI BY USER FOR THE PARTICULAREVM(S) AT ISSUE DURING THE PRIOR TWELVE (12) MONTHS WITH RESPECT TO WHICH LOSSES OR DAMAGES ARECLAIMED. THE EXISTENCE OF MORE THAN ONE CLAIM SHALL NOT ENLARGE OR EXTEND THIS LIMIT.
9. Return Policy. Except as otherwise provided, TI does not offer any refunds, returns, or exchanges. Furthermore, no return of EVM(s)will be accepted if the package has been opened and no return of the EVM(s) will be accepted if they are damaged or otherwise not ina resalable condition. If User feels it has been incorrectly charged for the EVM(s) it ordered or that delivery violates the applicableorder, User should contact TI. All refunds will be made in full within thirty (30) working days from the return of the components(s),excluding any postage or packaging costs.
10. Governing Law: These terms and conditions shall be governed by and interpreted in accordance with the laws of the State of Texas,without reference to conflict-of-laws principles. User agrees that non-exclusive jurisdiction for any dispute arising out of or relating tothese terms and conditions lies within courts located in the State of Texas and consents to venue in Dallas County, Texas.Notwithstanding the foregoing, any judgment may be enforced in any United States or foreign court, and TI may seek injunctive reliefin any United States or foreign court.
Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265Copyright © 2018, Texas Instruments Incorporated
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Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265Copyright © 2018, Texas Instruments Incorporated