Abstract A recent advancement in VLSI that drasticallyimproved the circuit density is the introduction of CMOL(CMOS/nanodevices hybrid), which consists of an overlayof a nanofabric over a CMOS stack. Combinational logic inCMOL is implemented from a netlist of NOR gates and In-verters by programming nanodevices placed between over-lapping nanowires. The length of the nanowires is restricted,and therefore connectivity of the circuit elements is con-strained to be within a certain radius, else additional buffersare required.
In this paper we present a Tabu Search (TS) algorithmto address the assignment problem in CMOL. The heuristicis engineered to provide sub-optimal solution by efficientexploration of search space. Empirical results for ISCASbenchmarks are compared with previous solutions usingGA, MA, and LRMA heuristics. Results show that in almostall cases, TS exhibits more intelligent search of the solutionssubspace, and is able to find better solutions in less time. Forall tested benchmarks, over 90 % reduction in average CPUprocessing time when compared with best published tech-niques was obtained.
S.M. Sait (�)Department of Computer Engineering and Center forCommunications and IT Research, Research Institute, King FahdUniversity of Petroleum & Minerals, Dhahran 31261,Saudi Arabiae-mail: [email protected]
A.M. ArafehDepartment of Computer Engineering, King Fahd University ofPetroleum & Minerals, Dhahran 31261, Saudi Arabiae-mail: [email protected]
1 Introduction
Modern iterative non-deterministic heuristics have been in-creasingly applied to solve a variety of combinatorial op-timization problems which are NP-hard. Assigning cells toslots is an important step in the process of electronic de-sign automation. Over time, the objective of placement inVLSI design has changed from reducing the overall wirelength to reducing the layout area, to improving timing per-formance, and then to reducing the overall power dissipa-tion. With new advances in technologies come new issues.The new advancement of CMOS/nanodevice hybrid circuits,like CMOL [26], requires combinational logic to be imple-mented from a netlist of NOR gates and Inverters by pro-gramming nanodevices placed between overlapping nano-wires. Like in the case of most programmable devices, thelength of the nanowires is restricted, and therefore connec-tivity of the circuit elements is constrained to be within acertain radius, else additional buffers are required.
The aim of this work is to come up with an efficient andeffective method for the cell assignment problem that ap-pears in CMOL nanofabric crossbar architecture. We ad-dress the complexity associated with the confined CMOLnanowires crossbar on the logic connectivity and circuitsimplementation. An iterative heuristic, namely Tabu Search,will be applied to find feasible circuits implementations inCMOL technology, by minimizing the number of additionalinserted buffers that may be required. The rest of the paperis arranged as follows: in Section 2, we discuss some back-grounds and previous works. Section 3 introduces CMOLFPGA-like architecture. Section 4 details the problem for-mulation, Section 5 outlines Tabu Search, a heuristic en-gineered to solve our combinatorial optimization problem.Section 6 contains the empirical results, comparison and fur-ther discussion about the problem behavior. Finally, we con-clude the paper and provide final remarks.
Assignment or cell placement problem has been proven tobe NP-hard [22]. For relatively large instances of such prob-lems (i.e., thousands of cells), it is not possible to use enu-merative techniques; therefore we resort to heuristic tech-niques which, in reasonable execution time, can lead toacceptable solutions. Heuristic algorithms assigned to theassignment problem can be broadly classified into con-structive and iterative algorithms. The constructive heuris-tic starts from a seed component; a cell to be assigned to aslot in the layout surface divided into n slots. During eachstep of the algorithm, one cell will be placed into one ofthe empty slots. At the end of each step, we have a par-tial placement of a subset of cells/modules. Different tech-niques can be applied to choose which unplaced cell mustbe selected and where to be added to the partial placement.For example, a cell to be placed may be selected dependingon how strongly it is connected to the current partial place-ment. The ideal location of the selected cell can be found,for instance, using a heuristic known as force-directed place-ment algorithm [24], where the cell zero-force location ismathematically computed. The constructive placement al-gorithms are greedy and don’t produce optimum solutionsbecause at each step they make decisions in the absenceof complete information. For example, when the cell is se-lected during the ith step, the selection is made with re-spect to the partial placement; the unplaced modules are ig-nored. Once a cell is placed, the algorithm will not go backand retrack from its already made decision. In CMOL cir-cuits, connections between cells are done through alreadyavailable nanowires and nanodevices. Constructive heuris-tics may reach the point where design constraints (e.g., lim-ited connectivity radius in CMOL) are not met, which endup with not only costly (e.g., wirelength) but infeasible so-lutions.
On the other hand, iterative heuristics can be engineeredto modify a given initial placement while respecting prob-lem constraints and improving the given cost function.Iterative improvement procedures constitute very effec-tive approaches to produce feasible solutions with the de-sired performance. Examples of iterative heuristics, whichare also known as non-deterministic heuristics, have beenwidely used in optimization problems and not limited toonly VLSI design automation. These include Genetic Al-gorithms [9, 15, 20], Simulated Evolution [21], StochasticEvolution [23], Particle Swarm Optimization [14, 30], AntColony [16, 31], and Tabu Search [12].
Tabu Search has been applied to solve a large numberof combinatorial optimization problems in various fields ofsciences, engineering, and business. Results reported indi-cate comparable performance to other iterative heuristics.Examples of hard problems to which Tabu Search has been
applied with success include routing and networking [7],scheduling [34], and space allocation [18]. Previous imple-mentations of Tabu Search for VLSI design problems in-clude parallel multi-objective cells placement [19], wherepower, area, and delay objectives are combined in an aggre-gated fuzzy cost function. Parallelization strategy is adaptedto traverse the large search space looking for placement withminimum cost.
Feature size scaling in CMOS technology has led todifficulties in manufacturing, due to short channel effects,doping fluctuations and expensive lithography process.Meanwhile, advances in nanoelectronics are expected toachieve high density of devices that can operate at THzfrequencies [4]. Many effective applications have beenproposed that use molecular nanodevices, nanowires, andnanocrossbar fabrics [25, 26]. A new trend is emergingfor combining the flexibility and high fabrication yieldadvantages of CMOS technology with nanometer-scalemolecular devices. A self-assembly of two-terminal nanode-vices, with nanowire crossbar fabrics, enables high func-tional density and sustains acceptable fabrication costs.Likharev and Strukov [26] introduced a hybrid semicon-ductor/nanowire/molecular integrated circuit called CMOL,which uses two levels of perpendicular nanowires as cross-bar interconnection on top of inverter-based CMOS stack,and showed possible applications of CMOL in field pro-grammable gate arrays (FPGA) [29], neuromorphic Cross-Nets [17], and in memories [27].
Recently, several proposals had been introduced for cellplacement/assignment on FPGA-like CMOL architecture.Like in other nano-fabric crossbars and FPGA like devices,nanowires break at fixed intervals confining CMOL cell con-nectivity to a fixed number (M) of other cells located withinits proximity square-like connectivity domain. Each CMOLcell must be connected to one of its proximity cell mem-bers, and failure to do so will require the insertion of a bufferwhich results in increase of congestion and delay. The prob-lem here is to find an assignment that will result in smallestnumber of additional buffers.
Likharev et al. utilized existing FPGA CAD tools to per-form placement and routing on 4 × 4 tile-based version ofCMOL [28, 29]. They used reserved routing cells and re-cursive routing algorithm for inter-tile routing. Hossein etal. [11] proposed a recursive method for removing routingcongestion by keeping and ranking placement solutions infinal iterations of the placement algorithm according to cost.Subsequently, when routing of best placement configurationfailed, another placement solution was considered until rout-ing was satisfied. Instead of working at tiles level, Hung etal. [13] encoded the CMOL cell assignment as a Satisfia-bility problem at cells level, where a placement solutions isfound when all Boolean constraints are satisfied. However,when circuits sizes increased the computation time becameevident.
Cell assignment in hybrid CMOS/nanodevices architecture using Tabu Search 3
Previous attempts to use sub-optimal search heuristics arereported in [6, 32, 33]. The genetic Algorithm (GA) [32] wasused with two dimensional block PMX crossover operatorand mutation, where the fitness function evaluated the Man-hattan distance between connected cells. The heuristic wasdriven to minimize the total Manhattan distance of the pop-ulation. Nonetheless, memory requirements, choices of datastructure for chromosomes representation, and computationtime are significant disadvantages of GA. A more elaboratework was reported in [6]; where a Memetic computing ap-proach was used by implementing a hybrid of the GeneticAlgorithm and the Simulated Annealing (SA) local-basedsearch heuristic. SA was used in each generation to en-hance offsprings which resulted from PMX crossovers andpairwise interchange mutations in GA. Hung et al. [33] ex-tended their work on Memetic approach by integrating self-learning operators using Lagrangian Multipliers (LRMA).The Lagrangian relaxation technique (LRT) was applied inpopulation goodness function by assigning Lagrangian mul-tipliers to penalty values corresponding to problem con-straints and repeatedly updating them. Results reported us-ing LRMA approach is promising, however, more computa-tions are needed for the penalty updating mechanism and SAlocal-based search. A theoretical investigation on CMOLcell assignment is reported in [5]; the authors proved math-ematically that placement of 2-input NOR/INV circuits ispossible and may require adding additional buffers (i.e., pairof inverters in case of cells that require long wires to con-nect) to satisfy all connections.
3 CMOL FPGA architecture
CMOL cell-based, field-programmable gate array (FPGA)-like architecture is based on integrating conventional in-verter-based four-transistor MOSFET CMOS cell with uni-form reconfigurable nanowire fabric. Two-terminal nanode-vices “latching switches”, that have two metastable internalstates, are self-assembled at each crosspoint in CMOL fab-ric and provide diode-like I–V curves for logic circuits im-plementation. Likharev et al. predicted the density of nan-odevices to be above 1012 to cm2 for Fnano = 3 nm, whereFnano is the nanowires half-pitch. That results in abundantavailable nanodevices that can serve both inter-cells connec-tivity and wiring-logic. CMOS stack is connected to nano-fabric by Metal pins that span to top and bottom nanowirelevels as shown in Fig. 1(a). Two CMOS inverters (i.e.,inverter A and inverter C) are connected by pin-nanowire-nanodevice-nanowire-pin connection. The electrical repre-sentation of four inverter-based CMOS cells and corre-sponding nanowire and nanodevices is shown in Fig. 1(b).Inverter A has two pins; pin1 connects the input of theCMOS inverter to one of the nanowires levels making the
Fig. 1 Low-level structure of CMOL circuit: the incline angleα � 1 and dimensionless parameter β satisfy two conditions,sinα = Fnano/βFCMOS and cosα = rFnano/βFCMOS where r is aninteger
nanofabric, while pin2 connects the CMOS inverter’s outputto the second level of nanowires. The upper right cell (in-verter A) is connected to the lower left cell (inverter C) byactivating the appropriate nanodevice (nd1) in the crosspoint
4 S.M. Sait, A.M. Arafeh
Fig. 2 CMOS FPGA topology:for r = 3,M = 2r(r − 1) − 1 = 11 cells inthe “Connectivity Domain”(Highlighted by dark line) forthe input pin of cells painted indark-grey [28]. The overlapbetween connectivity domain oftwo cells is shown in light grey
Fig. 3 Example of CMOLcircuit: (a) NOR/INV logicalcircuit; (b) CMOLimplementation of (a),(c) showing only used cells.Shaded cells are connectedthrough combination ofnanowires, nanodevices andCMOS pins
between the nanowire connected to output of inverter Aand nanowire connected to input of inverter C. When twoor more nanodevice on the same nanowire are activated asshown in Fig. 1(b) (nd1 and nd2) the output of inverter Cwill be equivalent to NOR gate whose inputs are cell A andcell B. Wired-OR logic is implemented through nanowiresand nanodevice.
CMOL nanowire crossbar is rotated by angle α =arcsin (Fnano/βFCMOS) related to the CMOS pins that arearranged into a square array with side of 2βFCMOS asshown in Fig. 1(c), where FCMOS is CMOS half-pitch, andβ is a factor larger than 1. This approach allows a uniqueaccess to any nanodevice via the appropriate pin pair. EachCMOS cell has an area of A = (2βFCMOS)2. Like othernano-fabric crossbars, CMOL’s nanowires break at repeatedintervals of L = 2β2F 2
CMOS confining CMOL cells connec-tivity to only M = 2r(r − 1) − 1 other cells located withinits proximity square-like “Connectivity Domain” as shownin Fig. 2, where r is an integer value that indicates the con-nectivity domain diameter and represents the constraint ofCMOL placement. CMOL nanodevices can be configuredby setting appropriate voltages. When configuration is donethe nanodevices are set to the ON (low-resistance) state orOFF (high-resistance). If the nanowires and nanodevicesshown in Fig. 3(b) are activated, the CMOL circuit will beequivalent to circuit shown in Fig. 3(a). The first NOR gateof the circuit can be implemented by connecting inputs ‘A’and ‘B’ with inverter ‘1’ to satisfy both connectivity and
logic wiring for the desired gate. The abundance of avail-able nanodevices and nanowires provides a variety of dif-ferent possible configurations for the implementation of onecircuitry. Among those their could be only certain config-urations that satisfy connectivity domain constraint and donot require additional routing resources.
Different variations of CMOL cells architecture were de-veloped in the literature; initially, Likharev [28] extendedcell types to include latches. Later, Dong et al. [8] pro-posed two new CMOL cells for efficient sequential logic im-plementation, the T-Cell, basically a transmission gate andthe D-Cell, a transmission gate and an inverter. Those newcells can be combined with original inverter-based cells toform Tri-State buffers for MUX implementation and D Flip-Flops for sequential design. Abid et al. [1] utilized two typesof nano-junction devices with CMOL-based cells to imple-ment cryptographic algorithms. They developed XOR gateswith resistive junctions and XOR/AND gates with diode-like junctions. The proposed design combines CMOS in-verters with transmission gates, and results in sufficientlylarger cells than the conventional inverter cell of CMOL.Abid et al. [2] also introduced a 3D CMOL FPGA imple-mentation where a nano-wire crossbar is placed betweentwo CMOS layers, each layer reaches to nanowires span-ning in one direction. This arrangement provides improveddensity, but with complex inter-cell connectivity as each cellis only restricted to access one level of the nanowire cross-bar.
Cell assignment in hybrid CMOS/nanodevices architecture using Tabu Search 5
4 Problem formulation
The placement or assignment of cells in order to minimizea cost function is a NP-hard problem [23]. Even one dimen-sional placement, the simplest possible, is hard to solve. In2-D array of n locations there are as many as
S = n(n − 1)(n − 2) · · · (n − m) (1)
arrangements for placing m cells, where m could be in thethousands. Overtime, heuristic techniques have been devel-oped for solving the placement problem, and finding a goodsolution in polynomial function of m.
Given a collection of NOR/INV gates, and the collec-tion of nets (the set of ports to be connected together), theCMOL placement problem consists of finding suitable loca-tions for each gate under the constraint of connectivity do-main and are given a cost function. Formally the problemcan be restated as: for a set of gates G = g1, g2, g3, . . . , gm
and a set of netlists Γ = γ1, γ2, γ3, . . . , γm where γi ={fan-ini & fan-outi} of gi and given a set of slots or loca-tions L = L1,L2,L3, . . . ,Ln where m ≤ n, the placementproblem is to assign each gi ∈ G to a unique location Lj
such that the objective is optimized. Positions are defined bythe coordinate values (xj , yj ) and the subset of G that rep-resent inputs/outputs may be pre-assigned fixed locations orconstrained to certain positions.
Each CMOL cell can implement one inverter or one NORgate with multiple fan-in, however, complying to the con-nectivity constraint can be substantially harder if gates ofhigh fan-in are allowed. Unlike conventional CMOS-basedcell assignment, CMOL cell placement is constrained to“Connectivity Domain” of radius r . Each CMOL cell isconnectable to one of its proximity cell members, any vi-olation of this constraint would impose further processing(i.e., buffer insertion) to satisfy connectivity. However, sucha process would cause more congestion to the already con-gested CMOL circuit and could result in a substantial in-crease of timing delay. Mathematically, the “ConnectivityDomain” can be defined as follow. Given a gate and itsnetlist (gi, γ i) placed in location Li , for any gate gk ⊆ G
and gk in the netlist γ i the following inequality should besatisfied.
dist(Lj ,Lk) ≤ r (2)
where Lk is the location of gk , dist is Manhattan distance,and r is CMOL connectivity diameter. The objective ofCMOL cell assignment is to satisfy the constraint in Inequal-ity (2), and to minimize distance between connected gates incircuit G. Failing to comply with the CMOL constraint willresult in an implementation that has more delay and arearequirements. The complexity of CMOL placement arisesfrom the overlap in connectivity domain of adjacent cells asshown in Fig. 2, that results in fewer connectivity choices.
Fig. 4 Tabu list visualized as window over accepted moves
5 Tabu Search and its implementation
Tabu Search is a general iterative metaheuristic for solvingcombinatorial optimization problems. TS proceeds by mak-ing iterative perturbations while preventing cycling to cer-tain number of recently visited points in search space. TheTS procedure starts from an initial feasible solution S (cur-rent solution) in the search space Ω . A neighborhood ℵ(S)
is defined for each S. A sample of neighbor solutions V∗ ⊂ℵ(S) is generated called trial solutions (n = |V*| � |ℵ(S)|),and comprises what is known as the candidate list. Fromthis generated set of trial solutions, the best solution, sayS∗ ∈ V∗ is chosen for consideration as the next solution.A solution S∗ ∈ ℵ(S) can be reached from S by an opera-tion called a move to S∗. The move to S∗ is considered evenif S∗ is worse than S, that is, Cost(S∗) > Cost(S). Selectingthe best move in V∗ is based on the supposition that goodmoves are more likely to reach the optimal or near-optimalsolutions. The best candidate solution S∗ ∈ V∗ may or maynot improve the current solution, but is still considered. It isthis feature that enables escaping from local optima. How-ever, with this strategy, it is possible to reach the local op-timum, since moves with Cost(S∗) > Cost(S) are accepted,and then in a later iteration return back to local optimum.
In order to prevent returning to previously visited solu-tions a memory or list T, known as tabu list, is maintained.This list contains information that to some extent forbidsthe search from returning to a previously visited solution.Whenever a move is accepted, its attributes are introducedinto the tabu list T. Move reversal is prevented for the nextk = |T| iterations because they might lead back to a previ-ously visited solution. The tabu list can be visualized as awindow on accepted moves as shown in Fig. 4. The moveswhich tend to undo previous moves within this window areforbidden.
In some cases, it is necessary to overrule the tabu sta-tus since only move attributes (not complete solutions) arestored in tabu lists. These tabu moves may also prevent theconsideration of some solutions which were not visited ear-lier. This is done with the help of the notion of aspirationcriterion. Aspiration criterion is a device used to overridethe tabu status of moves whenever appropriate. It temporar-ily overrides the tabu status if the move is sufficiently good.Aspiration criterion must make sure that the reverse of a re-cently made move leads the search to an unvisited solution,generally a better one. A flow chart illustrating the basic
6 S.M. Sait, A.M. Arafeh
Fig. 5 Flow-chart of Tabu Search algorithm
short-term memory Tabu Search algorithm is given in Fig. 5.Intermediate-term and long term memory processes are usedto intensify and diversify the search respectively [10, 23].
One of the Tabu Search algorithm parameters is the sizeof the tabu list. A small tabu list size is preferred for explor-ing the solution near a local optimum, and a larger tabu listsize is preferable for breaking free of the vicinity of localminimum. The list size varying between 5 and 12 have beenused in many applications. Any aspect (feature or compo-nent of a solution) that changes as a result of a move from S
to Strial can be an attribute of that move, where a singlemove can have several attributes. The duration for whicha move containing the particular tabu attribute is forbidden(the size of tabu list) is called Tabu tenure. An algorithmicdescription of a simple implementation of the tabu search isgiven in Fig. 6.
5.1 Solution representation and initialization
A placement solution is an arrangement of logic cells in atwo dimensional layout surface. The representation used inthis work is in the form of a 2-D grid. The layout is con-structed by computing the number of required CMOL cellsto fit each benchmark circuit. The outer cells of the grid arereserved for I/O pins, where I/O pins moves are restrictedto these reserved locations. In the initialization phase each
Ω : Set of feasible solutions (i.e., placements).S: Current solution.S∗: Best admissible solution.Cost: Objective function (Reduce # of buffers).ℵ(S): Neighborhood of S ∈ Ω .V∗: Sample of neighborhood solutions.T: Tabu list.AL: Aspiration Level.
Begin1. Start with an initial feasible solution (placement) S ∈ Ω .2. Initialize tabu lists and aspiration level.3. For fixed number of iterations Do4. Generate neighbor solutions V∗ ⊂ ℵ(S).
(Each solution results from the swap of two cells).5. Find best S∗ ∈ V∗.6. If move S to S∗ is not in T Then7. Accept move & update best solution.8. Update tabu list (Store swap reversal).9. Update aspiration level.
(AL = Cost of best solution seen so far).10. Increment iteration number.11. Else12. If Cost(S∗) < AL Then13. Accept move & update best solution.14. Update tabu list & aspiration level.15. Increment iteration number.16. EndIf17. EndIf18. EndFor
End.
Fig. 6 Algorithmic description of short-term Tabu Search (TS)
logic gate is assigned a positive integer value that distin-guishes it from the rest. Then, the encoded logic gates arerandomly assigned in the 2-D layout as shown in Fig. 7.
5.2 Cost evaluation
The main objective of placement is to find a feasible assign-ment of cells in which all connections are satisfied. One wayto accomplish this is to place strongly connected cells closeto each other. A commonly used objective function is the to-tal weighted wirelength over all signal nets and is expressedas:
L(P ) =∑
n∈N
wn · dn (3)
where, dn is the estimated wirelength of net n and wn isweight of net n. Since, in CMOL all cells are connected via
Cell assignment in hybrid CMOS/nanodevices architecture using Tabu Search 7
Fig. 8 Final cost yielded by TS in four circuits vs. candidate list size(r = 12)
pre-assembled nanowires, the problem we are trying to op-timize is to place connected cells within each others con-nectivity domain as to avoid insertions of additional buffers.Therefore, we should have a measure which can quantify theoverall quality of the solution. A conventional approach isto calculate the number of nets that violate the connectivitydomain constraint. The overall cost of a solution is the totalnumber of connectivity domain violating nets (the numberof additional buffers that are needed to satisfy all connec-tions). The cost of each gate g ∈ G is expressed in Eqs. (4a)and (4b), where the overall circuit’s cost is the sum of theindividual cost of the gates.
Ci =∑
j∈γ (i)
ui,j (4a)
ui,j ={
1 if disti,j > r
0 otherwise(4b)
5.3 Neighborhood solutions generation
In each iteration we generate a number of neighbor solutions(i.e., candidate list) by making perturbations as follows: twocells (two I/O pins or two logic cells) are selected randomly,then their locations are interchanged. Each solution in thecandidate list is evaluated based on the change in number ofbuffers before and after the swap. If two or more neighbor-hood solutions have equal swap cost, which also happens tobe the best cost in the candidate list, the solution with lesserManhattan distance is chosen. We have experimented withdifferent sizes of candidate lists; Fig. 8 shows the final costyielded by TS in four benchmark circuits when candidatelist size is changed, given that all other parameters are con-stant. It is clearly seen that for this problem TS had better re-sults when more neighbor solutions are considered. Figure 9shows the per iteration cost of one circuitry given differentsizes of candidate list. Candidate list sizes in the range of 50
Fig. 9 Change in cost per iteration of s1238.blif for different candidatelist sizes (r = 12)
reach the optimal solution of zero buffers when r = 12 inless iterations, thus this size has been used throughout ourimplementation.
5.4 Tabu list and aspiration level
Different tabu attributes were tested, when two cells i and j
are swapped. One attribute was to forbid moves related tocell i, that means that any move which included i, evenswapping i with j , was tabued. Another experiment consid-ered both i and j , forbidding any perturbations that includeeither of them. The Tabu attribute of a move that is usedin all results reported in this paper is swap reversal. If twocells are involved in interchange, the reversal of this move isforbidden. A short-term memory element is used throughoutthe implementation where experiments of tabu list size rang-ing from 5 to 12 were conducted. We conclude that changein the tabu list size in this range has little impact on the qual-ity of the solutions, thus the size of tabu list is taken as afixed value equal to 5. The aspiration criterion is based onthe following: if the current solution is the best seen so far(i.e., better than the global best solution), then tabu restric-tion is overridden and the current solution is accepted as newbest solution and tabu list is updated.
5.5 Tailored neighborhood solutions
Since the number of cells that violate the given constraint arefar less than the total number of cells, it is rational for Tabuswaps to always include cell(s) that violate the connectivityradius constraint. Therefore, we experimented by modify-ing the neighborhood solutions generation by constructing alist of top 20 cells which have many long connections andexceed the connectivity radius. In each iteration, this list isupdated to keep track of the worst placed cells. Each Tabumove (i.e., swap) involves a cell from this list, and anothercell that may or may not be in the list. This modification re-sults in always including violating cells in Tabu moves, such
8 S.M. Sait, A.M. Arafeh
moves may take the search to unvisited solutions thereby en-hancing search space exploration.
To avoid being greedy, and not curtail exploration, thefollowing approach was adopted. The list of all of the cir-cuit’s cells are sorted according to the cost given in Eq. (4a).When selecting cells for swaps, one cell is selected ran-domly while the other is selected probabilistically. Those onthe top of the list which have more violations have a higherchance of being selected, while those pairs that do not haveviolating cells also have a non-zero probability of being se-lected. To perform the probabilistic selection, we used thepositive values of a Gaussian random variable which hasmean m0 = 0 and standard deviation 3σ = circuit − size.Given the Gaussian distribution, cells in the top of the listwill be more frequently selected than those in the bottom ofthe list.
5.6 Buffers insertion
Buffers insertion is a post-processing procedure which isperformed when Tabu Search terminates. Violating connec-tions are resolved by inserting buffers as intermediary cells.Buffers insertion may fail if CMOL grid is highly congestedand/or the circuit still has many violating connections. Ini-tially, the procedure starts with one buffer (pair of inverters)for each violating connection. Buffers are inserted using thesame iterative methods used for cell placement. Tabu Searchis recalled given a number of modifications. All blank cellsin the grid are considered for buffers insertion. The invert-ers are randomly assigned. Swaps are allowed only betweenadded inverters or an inverter and blank cell. The algorithmcontinuously improves the locations of the inverters. If thealgorithm terminates and still some connections violate theconnectivity domain constraint, additional buffers are addedfor those connections and the procedure is repeated. Thisprocess repeats until all connected gates are within each oth-ers connectivity domain, or when no blank cells are left inCMOL grid (i.e., the circuit is infeasible given the currentcells arrangement). In our implementation, we limited thenumber of inverters that can be inserted in a given connec-tion to 6 to avoid major deterioration of the circuit’s timingdelay.
6 Experimental results
Evaluation of search heuristic efficiency and behavior isconducted using ISCAS’89 benchmarks [3]. Further con-sideration should be given to ISCAS’89 by replacing se-quential elements’ inputs and outputs with POs and PIs re-spectively [13]. ISCAS’89 benchmarks used in this work aremapped to NOR-based gates with maximum of five inputs.Tabu Search has been implemented using Java program-ming language and executed on a machine comparable to
Fig. 10 Change of problem cost and Manhattan distance in TS itera-tions (r = 12—s1238.blif)
the one used by other simulations published in literature, ithas 1.5 GHz Intel Pentium M processor with 512 MB mem-ory. Three options were available to find a placement solu-tion that satisfy the CMOL connectivity constraint; one wasto minimize Manhattan distance, another was to minimizenumber of inserted buffers by using cost function discussedin Sect. 5.2, and the third was to minimize both distanceand buffers. Results obtained for the first option showed thatthe number of inserted buffers are more than those of thesecond option. Moreover, when minimizing buffers, Man-hattan distance was reduced to similar levels as if distancewas being optimized. Minimizing both distance and buffersrequired more processing and didn’t have significant advan-tages over minimizing buffers only. Figure 10 shows the cor-relation between the number of inserted buffers and Manhat-tan distance. It can be seen that TS is accepting bad movesto reach better solutions in terms of inserted buffers (whichis the main objective), and in this process, the Manhattandistance (wirelength) also improves.
Table 1 shows the number of cells (i.e., NOR/INV logicgates), inputs and outputs of benchmark circuits used; Area(Tiles) is the area used by CMOL FPGA CAD 1.0 tool [29],while Area (Row × Column) is the area used in GA [32],MA [6], LRMA [33] and TS. The heuristic stops when allviolations are removed or when reaching a predefined num-ber of iterations. The median value of results obtained from20 runs for each circuit is reported where each run uses dif-ferent seeds for random numbers.
6.1 Literature comparison
Comparison is performed with CMOL FPGA CAD 1.0, weset the connectivity radius to r = 12 and r = 9. GA, MAand LRMA use population size equal to 24 and stoppingcriterion when fitness score is not updated for 50 times. Thecrossover rate in MA and LRMA is RC = 0.33 and mutationrate RM = 0.01. Simulated Annealing used in each of GAiterations has initial temperature T = 0.2 and terminating
Cell assignment in hybrid CMOS/nanodevices architecture using Tabu Search 9
Table 1 ISCAS’89 Benchmarks: showing the number of Cells to be placed including Gates, Inputs and Outputs. Area is the size of CMOL 2-Dgrid. AU % is the fraction of utilized cells in CMOL grid
Circuits Cells Gates Inputs Outputs Area (Tiles) Area (Row × Column) AU % (Tiles) AU %
temperature 0.01. Tables 2 and 3 show the final results ob-tained for ISCAS’89 benchmarks when r = 12 and r = 9 re-spectively; (Delay) is the circuit’s logical levels reported bySIS tool after inserting the buffers, computation time (Time)in seconds, (Buf ) shows the number of inserted buffers tosatisfy CMOL connectivity domain.
Tabu Search solutions are more effective than those ofCMOL CAD 1.0 in terms of computation time, delay andarea utilization. The last two columns of Table 1 show thatcell-based CMOL architecture has better area utilizationAU % than that of tile-based architecture. Tables 2 and 3indicate that the tile-based approach is the most time con-suming and the least effective in timing delay. It also fails toplace big circuits.
Results obtained from implementation of TS for r = 12are better than those obtained in GA, MA and LRMA in bothcomputation time and Buffers count. TS required shorterCPU processing time due to its simplified operations com-pared to genetic crossover, mutation and Lagrangian multi-pliers calculation in LRMA. Table 2 shows that Tabu Searchfound the optimal solutions with zero buffers for all bench-marks, with 92 % average computation time saving. For ex-ample, s1238 benchmark needed only 12.87 seconds in TS,comprising only a 3.6 % of time needed by LRMA.
Table 3 shows TS results when r = 9; solutions foundby TS are better than those of MA for all benchmark cir-cuits. TS falls behind LRMA in only two circuits (s820 and
s1238) while sustaining equal averaged results. Again, TSfound solutions in lesser time with 73 % saving.
Experiments were conducted using the tailored neighbor-hood generation; quality of results was similar to those ofTabu search with random swaps, however the range of can-didate list size reduced from 30–50 swaps to 20–40 swaps.This constituted for 20–35 % reduction in candidate list sizecompared to that required when random cells were selected.
For circuits s820, s832, s1196, s1238 when r = 9, buffersinsertion heuristic was unable to resolve all of the violatingconnections due to limited CMOL grid size. For example,circuit s1238 requires 54 buffers (i.e., 108 inverters) whereonly 60 blank cells are available in CMOL grid. Therefore,a bigger CMOL grid should be used to implement the cir-cuit. For accurate comparison with previous algorithms, weused the same grid size as reported in literature. Resultsgiven for the aforementioned circuits in Table 3 indicate thenumber of violating connections rather than the number ofbuffers inserted.
7 Conclusion
In this paper we presented the implementation of TabuSearch heuristic for CMOL nano-hybrid cells placement.We analyzed the problem behavior and engineered a TabuSearch solution that exploits better understanding of the lim-itations imposed by CMOL connectivity domain. Further,
10 S.M. Sait, A.M. Arafeh
Table 2 CMOL CAD, GA, MA, LRMA and TS results comparison for ISCAS’89 benchmark circuits and connectivity radius r = 12. Delay iscircuit’s logic levels. Time is computation time in seconds. Buf is the number of inserted buffers
Circuits CMOL CAD 1.0 GA [32] MA [6] LRMA [33] Tabu Search
Delay Time Delay Time Buf Delay Time Buf Delay Time Buf Delay Time Buf
Table 3 CMOL CAD, MA, LRMA and TS results comparison forISCAS’89 benchmark circuits and connectivity radius r = 9. Time iscomputation time in seconds. Buf is the number of inserted buffers
Circuits CMOL CAD 1.0 MA [6] LRMA [33] Tabu Search
we proposed a probabilistic method to make tailored swapsand reduce candidate list size. Results obtained are betterthan those published in literature with savings in requiredcomputation time. We are investigating the implementationof other search heuristics for CMOL placement problemand are experimenting with placement and reconfigurationaround defective nanodevices.
Acknowledgements The authors acknowledge King Fahd Univer-sity of Petroleum & Minerals for its support, and Dr. William N.N.Hung and Mr. Zhufei Chu for providing ISCAS’89 benchmark files.The authors would like also to thank Dr. Rajat Subhra Chakrabortyfor his help and support. Thanks are also due to the reviewers of themanuscript whose comments helped in improving our solutions.
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Sadiq M. Sait obtained a Bach-elor’s degree in Electronics fromBangalore University in 1981, andMaster’s and Ph.D. degrees in Elec-trical Engineering from King FahdUniversity of Petroleum & Minerals(KFUPM), Dhahran, Saudi Arabiain 1983 & 1987 respectively. Since1987 he has been working at the De-partment of Computer Engineeringwhere he is now a Professor. In 1981Sait received the best Electronic En-gineer award from the Indian Insti-tute of Electrical Engineers, Banga-lore (where he was born). In 1990,
1994 & 1999 he was awarded the ‘Distinguished Researcher Award’by KFUPM. In 1988, 1989, 1990, 1995 & 2000 he was nominated bythe Computer Engineering Department for the ‘Best Teacher Award’which he received in 1995, and 2000. Sait has authored over 200 re-search papers, contributed chapters to technical books, and lecturedin over 25 countries. Sadiq M. Sait is the principal author of thebooks (1) VLSI Physical Design Automation: Theory & Practice, pub-lished by McGraw-Hill Book Co., Europe, (and also co-published byIEEE Press), January 1995, and (2) Iterative Computer Algorithmswith Applications in Engineering (Solving Combinatorial Optimiza-tion Problems): published by IEEE Computer Society Press, Califor-nia, USA, 1999. He was the Head of Computer Engineering Depart-ment, KFUPM from January 2001–December 2004, Director of Infor-mation Technology and CIO of KFUPM between 2005 and 2011, andnow is the Director of the Center for Communications and IT Researchat the Research Institute of KFUPM.
Abdalrahman M. Arafeh receivedhis B.S. degree in Computer En-gineering from Damascus Univer-sity, Damascus, Syria, and MS de-gree from King Fahd University ofPetroleum & Minerals (KFUPM),Dhahran, Saudi Arabia. He coau-thored three conference papers andtwo journal papers. His research in-terests include FPGA, VLSI, DesignAutomation, and CAD.
