CPU Design

Answers Part2Q15-30: A Relatively Simple CPU

p263 Question 15Show the logic needed to generate the control signals for registers PC, DR, TR, and IR of the Relatively Simple CPU.

Control Logic

PCLOAD JUMP3 v JMPZY3 v JPNZY3

PCINC FETCH2 v LDAC1 v LDAC2 v STAC1 v STAC2 v JMPZN1 v JMPZN2 v JPNZN1 v JPNZN2

DRLOAD FETCH2 v LDAC1 v LDAC2 v LDAC4 v STAC1 v STAC2 v STAC4 v JUMP1 v JUMP2 v JMPZY1 v JMPZY2 v JPNZY1 v JPNZY2

TRLOAD LDAC2 v STAC2 v JUMP2 v JMPZY2 v JPNZY2

IRLOAD FETCH3

Question 16Show the logic needed to generate the control signals for registers R, AC, and Z of the Relatively Simple CPU.

Control Logic

RLOAD MVAC1

ACLOAD LDAC5 v MOVR1 v ADD1 v SUB1 v INAC1 v CLAC1 v AND1 v OR1 v XOR1 v NOT1

ZLOAD ADD1 v SUB1 v INAC1 v CLAC1 v AND1 v OR1 v XOR1 v NOT1

Question 17Show the logic needed to generate the control signals for the ALU of the Relatively Simple CPU.

State ALUS[1..7]

LDAC5 0 0 1 0 X X 0

MOVR1 0 0 1 0 X X 0

ADD1 1 0 1 0 X X 0

SUB1 1 1 0 0 X X 0

INAC1 1 0 0 1 X X 0

CLAC1 0 0 0 0 X X 0

AND1 X X X X 0 0 1

OR1 X X X X 0 1 1

XOR1 X X X X 1 0 1

NOT1 X X X X 1 1 1

ALU Bit Logic

ALUS1 ADD1 v SUB1 v INAC1

ALUS2 SUB1

ALUS3 LDAC5 v MOVR1 v ADD1

ALUS4 SUB1 v INAC1

ALUS5 XOR1 v NOT1

ALUS6 OR1 v NOT1

ALUS7 AND1 v OR1 v XOR1 v NOT1

Question 18Verify the functioning of the Relatively Simple CPU for all instructions, either manually or using the CPU simulator.

A Assembly Register

0:

9:

D:

LDAC 0000

NOP

MVAC

ADD

INAC

XOR

AND

JMPZ 000D

NOP

JPNZ 0009

NOT

JMPZ 0009

JPNZ 0018

NOP

(AC ← 1)

(R ← 1)

(AC ← 2, Z ← 0)

(AC ← 3, Z ← 0)

(AC ← 2, Z ← 0)

(AC ← 0, Z ← 1)

(jump is taken)

(skipped by JMPZ 000D)

(jump is not taken)

(AC ← FF, Z ← 0)

(jump is not taken)

(jump is taken)

(skipped by JMPZ 0018)

A Assembly Register

18:

CLAC

OR

SUB

MOVR

STAC 0030

AND

JUMP 0000

(AC ← 0, Z ← 1)

(AC ← 1, Z ← 0)

(AC ← 0, Z ← 1)

(AC ← 1)

(M[30] ← 1)

(AC ← 1, Z ← 0)

(start again)

Question 19Modify the Relatively Simple CPU to include a new instruction, SETR, which performs the operation R←1111 1111. Its instruction code is 0001 0000. Show the modified state diagram and RTL code for this CPU.(Hint: One way to implement this is to clear R and then decrement it.)Answer:SETR1: R← 0SETR2: R← R - 1

Question 20For the CPU of Problem 19, show the modifications necessary for the register section.

Answer:

R needs two additional inputs: CLR, driven by new control signal RCLR, and DCR, driven by new control signal RDCR.

Question 21For the CPU of Problem 19, show the modifications necessary for the control unit. Include the hardware needed to generate any new or modified control signals.

Answer:•Add hardware to generate ISETR = I7' ^ I6' ^ I5' ^ I4 ^ I3' ^ I2' ^ I1' ^ I0', SETR1 = ISETR ^ T3, and SETR2 = ISETR ^ T4.•Add SETR1 to the OR gate driving INC of the time counter and SETR2 to the OR gate driving CLR of the time counter.•New control signals RCLR = SETR1 and RDCR = SETR2.

Question 22Verify the functioning of the CPU of Problems 19, 20, and 21 for the new instruction.

Question 23Modify the Relatively Simple CPU to include a new 8-bit register, B, and five new instructions as follows. Show the modified state diagram and RTL code for this CPU.

Answer:ADDB1: AC ← AC + BSUBB1: AC ← AC - BANDB1: AC ← AC ^ BORB1: AC ← AC v BXORB1: AC ← AC B

Question 24For the CPU of Problem 23, show the modifications necessary for the register section and the ALU.

Answer:•No ALU changes are needed•Register B is added to the CPU. It sends data to the bus through tri-state buffers but does not receive data from the bus (since it is never loaded).

Question 25For the CPU of Problem 23, show the modifications necessary for the control unit. Include the hardware needed to generate any new or modified control signals.

Answer:•Add the hardware shown below to generate IADDB, ISUBB, IANDB, IORB, and IXORB, and add hardware to generate ADDB1 = IADDB ^ T3, SUBB1 = ISUBB ^ T3, ANDB1 = IANDB ^ T3, ORB1 = IORB ^ T3, and XORB1 = IXORB ^ T3.•OR together ADDB1, SUBB1, ANDB1, ORB1, and XORB1 to generate BBUS.•Add the same five signals to the OR gate driving CLR of the counter.•Change ALUS[1..7] such that ADD1 is replaced by ADD1 v ADDB1, and so on for SUB1, AND1, OR1, and XOR1, yielding:ALUS1 = ADD1 v ADDB1 v SUB1 v SUBB1 v INAC1ALUS2 = SUB1 v SUBB1ALUS3 = LDAC5 v MOVR1 v ADD1v ADDB1ALUS4 = SUB1 v SUBB1v INAC1ALUS5 = XOR1 v XORB1 v NOT1ALUS6 = OR1 v ORB1 v NOT1ALUS7 = AND1 v ANDB1 v OR1 v ORB1 v XOR1 v XORB1 v NOT1

Question 26Verify the functioning of the CPU of Problems 23, 24, and 25 for the new instructions.

Answer:Initially AC = 1 and B = 2. Fetch cycles not shown.Instruction State Operations performedORB ORB1 AC ← 1 v 2 = 3ADDB ADDB1 AC ← 3 + 2 = 5ANDB ANDB1 AC ← 5 ^ 2 = 0XORB XORB1 AC ← 0 Å 2 = 2SUBB SUBB1 AC ← 2 - 2 = 0

Question 27For the Relatively Simple CPU, assume the CLAC and INAC instructions are implemented via the CLR and INC signals of the AC register, instead of through the ALU. Modify the input and control signals of Z so it is set properly for all instructions.

Answer:•Remove CLAC1 and INAC1 as inputs to the OR gate which generates ACLOAD.•Add control inputs to AC: CLR = CLAC1, and INC = INAC1.•Change the input to Z as shown below. ZLOAD is unchanged.

Question 28 Design a CPU that meets the following specifications.• It can access 64 words of memory, each word being 8 bits wide. The CPU does this by outputting a 6-bit address on its output pins A[5..0] and reading in the 8-bit value from memory on its inputs D[7..0].• The CPU contains a 6-bit address register (AR) and program counter (PC); an 8-bit accumulator (AC) and data register (DR); and a 2-bit instruction register (IR).• The CPU must realize the following instruction set.

Question 28 Cont.Answer:State diagram and RTL code:FETCH1: AR ← PCFETCH2: DR ← M, PC ← PC + 1FETCH3: IR ← DR[7..6], AR ← DR[5..0]COM1: AC ← AC'JREL1: DR ← MJREL2: PC ← PC + DR[5..0]OR1: DR ← MOR2: AC ← AC v DRSUB11: DR ← MSUB12: AC ← AC + DR'

Question 29Design a CPU that meets the following specifications.• It can access 256 words of memory, each word being 8 bits wide. The CPU does this by outputting an 8-bit address on its output pins A[7..0] and reading in the 8-bit value from memory on its inputs D[7..0].• The CPU contains an 8-bit address register (AR), program counter (PC), accumulator (AC), and data register (DR), and a 3-bit instruction register (IR).• The CPU must realize the following instruction set. Note that a is an 8- bit value stored in the location immediately following the instruction.

Question 30Modify the Relatively Simple CPU so that it can use a stack. The changes required to do this are as follows.• Include a 16-bit stack pointer (SP) register that holds the address of the top of the stack.• The CPU must realize the following additional instructions. Note that operations separated by semicolons occur sequentially, and operations separated by commas occur simultaneously. Also note that the value of PC used by the CALL instruction is the value of PC after has been fetched from memory.