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Chapter 1 Interconnect Extraction

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Chapter 1 Interconnect Extraction. Prof. Lei He Electrical Engineering Department University of California, Los Angeles URL: eda.ee.ucla.edu Email: [email protected]. Outline. Capacitance Extraction Introduction Table based method Formula based method Inductance Extraction Introduction - PowerPoint PPT Presentation
58
Chapter 1 Interconnect Extraction Prof. Lei He Electrical Engineering Department University of California, Los Angeles URL: eda.ee.ucla.edu Email: [email protected]
Transcript
Page 1: Chapter 1 Interconnect Extraction

Chapter 1

Interconnect Extraction

Prof. Lei HeElectrical Engineering Department

University of California, Los Angeles

URL: eda.ee.ucla.eduEmail: [email protected]

Page 2: Chapter 1 Interconnect Extraction

Outline

Capacitance Extraction– Introduction– Table based method– Formula based method

Inductance Extraction– Introduction– Table based method– Formula based method

RLC circuit model generation– Reading assignment

Finite element method (FEM) based Extraction– Overview of FEM– FEM based Extraction Flow– Reading assignment

Homework

Page 3: Chapter 1 Interconnect Extraction

Capacitance - Introduction

What’s Capacitance?

• Simplest model: parallel-plate capacitor– It has two parallel plates and homogeneous dielectric between

them

– The capacitance is permittivity of dielectric A area of plate d distance between plates

– The capacitance is the capacity to store charge charge at each plate is

– one is positive, the other is negative

++

++

- -

- -

+Q -Q

dAC

CVQ

Page 4: Chapter 1 Interconnect Extraction

Capacitance - Introduction

• For multiple conductors of any shapes and materials, and in any dielectric, there is a capacitance between any two conductors (coupling capacitance).

• Mutual capacitance between m1 and m2 is C12 = q1/v2

– q1 is the charge of m1– v1 =0 and v3 = 0

4

m1

m3

m2

c23

c13

c12

Page 5: Chapter 1 Interconnect Extraction

Capacitance - Introduction

How to represent Capacitance?• Capacitance is often represented by a symmetric matrix

• is the self-capacitance for a conductor

• e.g., c11 =c12+c13

• The charge is given by • e.g.,

5

m1

m3

m2

c23

c13

c12

C = -c21 c22 -c23

-c31 -c32 c33

c11 -c12 -c13

)(1

ijccm

jijii

Tmmmm VCQ )(

3132121111 vcvcvcq )()( 31132112 vvcvvc

Page 6: Chapter 1 Interconnect Extraction

Capacitance - Introduction

How to calculate Capacitance?

• Self-capacitance is sum of total coupling/mutual cap, i.e.

• To the first order, capacitance exists only between adjacent wires or crossing wires, and can be pre-computed for a set of (localized) interconnect structures

– Table based Cap. Extraction

– Formula based Cap. Extraction

6

)(1

ijccm

jijii

CxCx

CxCxCxCx

Page 7: Chapter 1 Interconnect Extraction

Capacitance – table/library based method

Table based Cap. Extraction (2.5D method) has two steps:

• Table (Capacitance coefficients) generation– One-time use of 3-D method

• Capacitance computation– Table lookup with linear interpolation and extrapolation

Reference:[He-et al, DAC’97]

Page 8: Chapter 1 Interconnect Extraction

Table generation

1. Lateral, Area and Fringe Capacitances

Functions of (w,s) Pre-computed for per-side per unit-length

8

layer i

ws s

Page 9: Chapter 1 Interconnect Extraction

Table generation (cont.)

2. Crossing Capacitances

• Function of (w,s,wc,sc)

9

layer i

w

s

sc

wc

sc

Page 10: Chapter 1 Interconnect Extraction

Table generation (cont.)

2. Crossing Capacitances

10

s

sc

wc

sc

wc

sc

w w

Ci,i

Per-corner Cover(w,s,wc,sc) = 4

s

Page 11: Chapter 1 Interconnect Extraction

victim

Compute the lumped cap for victim

Illustration of Capacitance Computation

Page 12: Chapter 1 Interconnect Extraction

victim

Find Nearest Neighbors on Same Layer

Page 13: Chapter 1 Interconnect Extraction

victim

w

S1

L1

Add in Per-Side Area, Fringe and Lateral Capacitances

Per-side area capacitance = CA(w,s1) * L1

Per-side fringe capacitance = CF(w,s1) * L1

Per-side lateral capacitance = CL(w,s1) * L1

Page 14: Chapter 1 Interconnect Extraction

victim

Add in Per-Side Area, Fringe and Lateral Capacitances

Page 15: Chapter 1 Interconnect Extraction

victim

Find All Crossovers and Crossunders

Page 16: Chapter 1 Interconnect Extraction

wc

sc

S1victim

w

Add in Crossing Capacitances Corner-by-Corner

One-corner crossover correction = Cover(w,S1,wc,sc)

Page 17: Chapter 1 Interconnect Extraction

wc

S1victim

w

One-corner crossover correction = Cover(w,S1,wc,)

Add in Crossing Capacitances Corner-by-Corner

Page 18: Chapter 1 Interconnect Extraction

wc

S1victim

w

One-corner crossover correction = Cover(w,,wc,)

Add in Crossing Capacitances Corner-by-Corner

Page 19: Chapter 1 Interconnect Extraction

wc

sc

victim

w

One-corner crossover correction = Cover(w,,wc,sc)

Add in Crossing Capacitances Corner-by-Corner

Page 20: Chapter 1 Interconnect Extraction

Summary of Capacitance Computation

Find nearest neighbors on the same layer.

Add in per-side lateral, area and fringe capacitance w.r.t. each neighbor.

Find all crossovers and crossunders.

Add in crossing capacitances corner-by-corner w.r.t. each crossover and crossunder.

Sum of capacitance components in above steps

is the lumped capacitance of the victim.

Page 21: Chapter 1 Interconnect Extraction

Capacitance – formula based method

• Extract the Capacitance with analytical Formulae

• Formula based on Horizontal and Vertical Parameters– Single Line

– Parallel Lines

• References:[Sakurai-Tamaru,ED’83][Wu-Wong-et al, ISCAS’96]

Page 22: Chapter 1 Interconnect Extraction

Capacitance – formula based method

Single Line Example:

– Unit-length capacitance:

– Error less than 6% when

22

w

Fp

Ff Fft

h

wkkC 100

)}(15.1)(80.2{ 222.0hw

ht

303.0

303.0

ht

hw

[Sakurai-Tamaru, ED’83]

Page 23: Chapter 1 Interconnect Extraction

Capacitance – formula based method

Single Line of Length L

– Line of length L

23

t

h

})(12.4)22()(40.1)(15.1{ 728.0222.0 hLwC ht

ht

hLw

L

})(80.2)(15.1{/ 222.0ht

hwLC

w

[Sakurai-Tamaru, ED’83]

Page 24: Chapter 1 Interconnect Extraction

Capacitance – formula based method

Two Parallel Lines on Same Layer

– Unit-length capacitance:

– Error less than 10% when

24

w ws

t

h

})]()(07.0)(83.0)(03.0{[' 34.1222.000 s

hht

ht

hwCC

,103.0 hw ,103.0 h

t 105.0 hs

[Sakurai-Tamaru, ED’83]

Page 25: Chapter 1 Interconnect Extraction

Capacitance – formula based method

Three Parallel Lines on Same Layer

– Unit-length capacitance:

– Recall

25

w ws

t

h

ws

})]()(227.1)(229.0[)(977.2{ 0398.0384.1232.0sh

st

sw

ht

hwC

})]()(07.0)(83.0)(03.0[2

)(80.2)(15.1{34.1222.0

222.0

sh

ht

ht

hw

ht

hwC

[Sakurai-Tamaru, ED’83]

[Wu-Wong-et al, ISCAS96]

Page 26: Chapter 1 Interconnect Extraction

Capacitance – formula based method

Three Parallel Lines within Two Grounds

– Two Grounds:

where

– One Ground:

26

w ws

t

h1

wsh1

}628.0)]()(348.1)(053.0[

])()[(637.1{597.1

216.0216.0

21

sh

st

sw

ht

ht

hwC

21

21

hhhhh

})]()(227.1)(229.0[)(977.2{ 0398.0384.1232.0sh

st

sw

ht

hwC

[Wu-Wong-et al, ISCAS96]

Page 27: Chapter 1 Interconnect Extraction

Reading Assignment

[1] J. Cong, L. He, A. B. Kahng, D. Noice, N. Shirali and S. H.-C. Yen, "Analysis and Justification of a Simple, Practical 2 1/2-D Capacitance Extraction Methodology", ACM/IEEE Design Automation Conference, June 1997, pp.627-632

[2] T.Sakurai, K.Tamaru, "Simple Formulas for Two- and Three-Dimensional Capacitances," IEEE Trans. Electron Devices ED-30 pp. 183-185 (Feb. 1983)

Page 28: Chapter 1 Interconnect Extraction

Outline

Capacitance Extraction– Introduction– Table based method– Formula based method– Reading assignment

Inductance Extraction– Introduction– Table based method– Formula based method– Reading assignment

RLC circuit model generation Inductance screening– Reading assignment

Finite element method (FEM) based Extraction– Overview of FEM– FEM based Extraction Flow– Reading assignment

Homework

Page 29: Chapter 1 Interconnect Extraction

Inductance - Introduction

Is RC Model Sufficient?

• As the clock frequency grows fast, the interconnect impedance is more than resistance

Z = R + jωL

• Inductance should be considered• When ωL becomes comparable to R as we move towards

GHZ designs and 1/tr

• Example: wide clock trees– Skews are different under RLC and RC models

– Neighboring signals are disturbed due to large clock di/dt noise

Page 30: Chapter 1 Interconnect Extraction

Resistance vs Inductance

0

20

40

60

80

100

120

140

160

180

200

1.00E+08 1.00E+09 1.00E+10 1.00E+11

frequency (100M-100G)

Rea

ctan

ce R

wL

2.50E-09

2.60E-09

2.70E-09

2.80E-09

2.90E-09

3.00E-09

3.10E-09

3.20E-09

1.00E+08 1.00E+10 1.00E+12 1.00E+14

frequency (100M-100T)Hz

Indu

ctan

ce(H

)

Self

mutual

R and R and L for a single wireL for a single wire Ls and Lx for two parallel wiresLs and Lx for two parallel wires

Length = 2000, Width = 0.8 Length = 2000, Width = 0.8

Thickness = 2.0, Space = 0.8Thickness = 2.0, Space = 0.8

Page 31: Chapter 1 Interconnect Extraction

Inductance - Introduction

Impact of Inductance

GndGnd GndGndClkClk

6000

u

6000

u

10u10u5u5u 5u5u

RLC modelRLC modelRC modelRC model

Page 32: Chapter 1 Interconnect Extraction

Loop Inductance

Loop inductance is defined as

the induced magnetic flux in the loop

by the unit current in other loop

The average magnetic flux can be calculated by magnetic vector potential Aij

32

jkifIforI

L kj

ijij 0

where, represents the magnetic flux

in loop i due to a current Ij in loop j

i a

iiiji

ij

i

dadlAa

1 where, ai represents a cross section of loop i

Loop i Loop j

Ij

ij

ij

ij

Page 33: Chapter 1 Interconnect Extraction

The magnetic vector potential A, defined as an integral form

Loop Inductance (cont.)

33

j a ij

jj

j

jij

jr

dadl

a

IA

4

jconductorofareacrossa

jconductorofelementdl

rrrwhere

j

j

jiij

:

:

,

i a j a

jiij

ji

jiij

i j

dadar

dldl

aaL

1

4

So, loop inductance is

Page 34: Chapter 1 Interconnect Extraction

Partial Inductance

Problems of loop inductance The loops (called return paths) are

hardly defined explicitly in VLSI In most cases, the return paths

are multiple

Partial inductance proposed by A. Ruehli The return path is assumed at infinite for each conductor

segment It can be directly appliable to circuit simulator like SPICE

34

1

2

3

4

5

Page 35: Chapter 1 Interconnect Extraction

Partial Inductance (cont.)

35

K

k

c

bi

k

k1

K

k

M

m a a

c

b

c

b

mkkm

mk

mkij

k m

k

k

m

m

dadar

dldl

aaL

1 1

1

4

M

m

c

bj

m

m1

(assume loop i consists of K segments and loop j does M segments)So, loop inductance is

i a j a

jiij

ji

jiij

i j

dadar

dldl

aaL

1

4

Loop inductance between loop i and j is

Page 36: Chapter 1 Interconnect Extraction

Partial Inductance (cont.)

Definition of partial inductance

The sign of partial inductance is not considered So, partial inductance is solely dependent of conductor

geometry

Sign rule for partial inductance

where, Skm = +1 or –1

The sign depends on the direction of current flow in the conductors

36

k m

k

k

m

m

km

a a

c

b

c

b

mkkm

mk

mkP dada

r

dldl

aaL

||1

4

K

k

M

mPkmij km

LSL1 1

Page 37: Chapter 1 Interconnect Extraction

Outline

Capacitance Extraction– Introduction– Table based method– Formula based method– Reading assignment

Inductance Extraction– Introduction– Table based method– Formula based method– Reading assignment

RLC circuit model generation– Reading assignment

Finite element method (FEM) based Extraction– Overview of FEM– FEM based Extraction Flow– Reading assignment

Homework

Page 38: Chapter 1 Interconnect Extraction

Inductance Extraction from Geometries

Numerical method based on Maxwell’s equations– Accurate, but way too slow for iterative physical design and

verification

Efficient yet accurate models– Coplanar bus structure [He-Chang-Shen-et al, CICC’99]– Strip-lines and micro-strip bus lines [Chang-Shen-He-et al,

DATE’2K]– Used in HP for state-of-the-art CPU design

Page 39: Chapter 1 Interconnect Extraction

Loop Inductance for N Traces

Tw Tw Tw

Ts Ts

TwL TwR

TsL TsR

Assume edge traces are AC-grounded leads to 3x3 loop inductance matrix

Inductance has a long range effect non-negligible coupling between t1 and t3, even with t2

between them

1.73 1.15 0.531.15 1.94 1.240.53 1.24 1.92tL t1 t2 t3 tR

It is not sufficient to consider only a single netIt is not sufficient to consider only a single net

Page 40: Chapter 1 Interconnect Extraction

Table in Brute-Force Way is Expensive

Self inductance has nine dimensions: (n, length, location,TwL,TsL,Tw,Ts,TwR,TsR)

Mutual inductance has ten dimensions: (n, length, location1, location2,TwL,TsL,Tw,Ts,TwR,TsR)

Length is needed because inductance is not linearly scalable

Tw Tw Tw

Ts Ts

TwL TwR

TsL TsR

1.73 1.15 0.531.15 1.94 1.240.53 1.24 1.92tL t1 t2 t3 tR

Page 41: Chapter 1 Interconnect Extraction

Partial Inductance for N Traces

6.17 5.43 5.12 4.89 4.665.43 6.79 6.10 5.48 5.045.12 6.10 6.79 6.10 5.334.89 5.48 6.10 6.79 5.774.66 5.04 5.33 5.77 6.50

Tw Tw Tw

Ts Ts

TwL TwR

TsL TsRtL t1 t2 t3 tR

Treat edge traces same as inner traces lead to 5x5 partial inductance table

Partial inductance model is more accurate compared to loop inductance model

Without pre-setting current return loop

Page 42: Chapter 1 Interconnect Extraction

Propose and validate five foundations

Tw Tw Tw

Ts Ts

TwL TwR

TsL TsRtL t1 t2 t3 tR

6.17 5.43 5.12 4.89 4.665.43 6.79 6.10 5.48 5.045.12 6.10 6.79 6.10 5.334.89 5.48 6.10 6.79 5.774.66 5.04 5.33 5.77 6.50

6.50

Foundation I:The self inductance under the PEEC model for a trace depends only on the trace itself (w/ skin effect for a given frequency).

Page 43: Chapter 1 Interconnect Extraction

Inductance – Table based method

Foundation II:The mutual inductance under the PEEC model for two traces depends only on the traces themselves (w/ skin effect for given frequency).

Tw Tw Tw

Ts Ts

TwL TwR

TsL TsRtL t1 t2 t3 tR

6.17 5.43 5.12 4.89 4.665.43 6.79 6.10 5.48 5.045.12 6.10 6.79 6.10 5.334.89 5.48 6.10 6.79 5.774.66 5.04 5.33 5.77 6.50

4.666.50

6.174.66

Page 44: Chapter 1 Interconnect Extraction

Foundation III:The self loop inductance for a trace on top of a ground plane depends only on the trace itself (its length, width, and thickness)

Inductance – Table based method

4.8 2.5 1.3 0.7 0.142.5 5.5 2.9 1.5 0.71.3 2.9 5.7 2.9 1.30.7 1.5 2.9 2.5 2.50.14 0.7 1.3 2.5 4.8

Tw Tw Tw

Ts Ts

TwL TwR

TsL TsRtL t1 t2 t3 tR

4.8

tR

Page 45: Chapter 1 Interconnect Extraction

Foundation IV:The mutual loop inductance for two traces on top of a ground plane depends only on the two traces themselves (their lengths, widths, and thickness)

Inductance – Table based method

4.8 2.5 1.3 0.7 0.142.5 5.5 2.9 1.5 0.71.3 2.9 5.7 2.9 1.30.7 1.5 2.9 2.5 2.50.14 0.7 1.3 2.5 4.8

Tw Tw Tw

Ts Ts

TwL TwR

TsL TsRtL t1 t2 t3 tR

0.14

tRtL

4.8

0.14 4.8

Page 46: Chapter 1 Interconnect Extraction

Validation and Implication of Foundations

Foundations I and II can be validated theoretically

Foundations III and IV were verified experimentally

Problem size of inductance extraction can be greatly reduced w/o loss of accuracy

Solve 1-trace problem for self inductance– Reduce 9-D table to 2-D table

Solve 2-trace problem for mutual inductance– Reduce 10-D table to 3-D table

Page 47: Chapter 1 Interconnect Extraction

Outline

Capacitance Extraction– Introduction– Table based method– Formula based method– Reading assignment

Inductance Extraction– Introduction– Table based method– Formula based method– Reading assignment

RLC circuit model generation– Reading assignment

Finite element method (FEM) based Extraction– Overview of FEM– FEM based Extraction Flow– Reading assignment

Homework

Page 48: Chapter 1 Interconnect Extraction

Inductance – formula based method

Inductance Extraction from Geometries

• Conductor Geometry

• Inductance Formulae– Self Inductance : Grover(1962), Hoer(1965), Ruehli(1972),

FastHenry(1994)

– Mutual Inductance : Grover(1962), Hoer(FastHenry)(1965),

Ruehli(1972)

48

x z

Dx

Dy

Dz

y

Conductor 1 Conductor 2

T

W

l

(a) Single Conductor (b) Two Parallel Conductors

Page 49: Chapter 1 Interconnect Extraction

Self Inductance – Grover’s formula

For single straight wire:– length: l– width: W– thickness: T

With the filament approximation (W, T<< l), the self-inductance Lself-L

can be written as

μ is the permeability of conductor.

49

2 1 ( )ln

2 2 4self L

l l W TL

W T l

T

W

l

Page 50: Chapter 1 Interconnect Extraction

For two parallel and aligned wires of the same width W, thickness T, length l, and center-to-center distance D.

With the filament approximation (W, T<< l), the mutual-inductance Lmutual-L can be written as

Mutual Inductance – Grover’s Formula

50

2ln 1

2mutual L

l l DL

D l

Conductor 1

Conductor 2

T

W

l

D

Page 51: Chapter 1 Interconnect Extraction

Extension from Aligned Filaments to Random Ones [Xu-HE, GLSVLSI’01]

Mutual inductance Lab =

+ - -

Mutual inductance

Lm1 Lm2 Lm3 Lm4

a

b

Page 52: Chapter 1 Interconnect Extraction

Self Inductance – Ruehli’s Formula

52

3142

3

63

3

51

2

3

4314222412712

4

17

4

16

4

12

542

2

2

73

2

34

2

6252

2

60ln

24

1ln

242060

11

60

1

20ln

24

1

tan6

1

4tan

64tan

6420

1

60ln

2460ln

24

11ln

24

2

AuAAu

Au

Au

Au

AuAA

uAA

uA

uAA

uAAu

A

uA

A

uA

u

uA

uA

uAA

u

Au

AAu

AAu

AAu

AA

ul

L

i

ii

2

47

1

46

3

45

224

223

22

21

lnln1

ln1

11

A

AuA

A

AA

A

AAuA

uAAuAW

T

W

lu

.1

111

ln31

1ln36

2

3

3

2

3

4

222

uu

uuu

uuuu

l

L

i

ii

where

If T/W < 0.01

Page 53: Chapter 1 Interconnect Extraction

Self Inductance – used by FastHenry

53

aratarawarraratatawawar

atawar

arawawwwrrar

wawwrar

aratatttrrar

tattrar

arw

t

t

w

art

w

w

t

ar

tw

tw

arataw

wt

wtarawat

tw

twarawrw

t

t

w

aratrt

w

w

t

arraww

t

t

w

arratt

w

w

t

raw

t

tat

w

wLii

111

20

1

))(1)(1)((

)1(

))()()((

)(

))()()((

)(

60

1tantantan

1

6

1

)(sinh

1

)(sinh

1

)(sinh

)(sinh

)(sinh

)(sinh

24

11sinhsinh

1sinh

1

4

12

2

2111

21

2

21

2

21

2

221

2

2

12

12

111

111 2222

22

twartatwaw

twrl

Tt

l

Wwwhere

Page 54: Chapter 1 Interconnect Extraction

Comparisons of Self Inductance Formulae

54

Formula Short Conductor(l/W < 10)

Medium Conductor

(10 < l/W < 1000)

Long Conductor(l/W > 1000)

FastHenry O O O

Ruehli X O X

Grover X O O

Page 55: Chapter 1 Interconnect Extraction

Mutual Inductance – Ruehli’s formula

55

4

1

22221 ln14 m

mmmmm

i

ij rgrgggl

L

where pgvpgvpgpgl

DyDxr

l

Dzp

l

lv

iii

j

4321

22

11

x z

Dx

Dy

Dz

y

Conductor 1 Conductor 2

Page 56: Chapter 1 Interconnect Extraction

Mutual Inductance – Hoer’s Formula

For multiple filaments

56

)()()(tan6

tan6

tan6

33360

1ln

24244

ln24244

ln24244

001.0

21

12

21

12

21

12

,

,

,

,

,

,

222

13

222

13

222

13

222222222444

22

2224422

22

2224422

22

2224422

2121

zyxzyxx

yzyzx

zyxy

xzzxy

zyxz

xyxyz

zyxxzzyyxzyxyx

zyxzz

yxyx

xz

zyxyy

zxxz

zy

zyxxx

zyzy

TTWWL

lDlD

DllD

TDTD

DTTD

WDWD

DWWD

ij

zz

zz

xx

xx

yy

yy

where

4

1

4

1

4

1

1,

,

,

,

,, ),,()1()()()(),,(

31

42

31

42

31

42i j k

kjikji

ss

ss

rr

rr

qqqq srqfzyxzyxf

Page 57: Chapter 1 Interconnect Extraction

Reading Assignment

[1] L. He, N. Chang, S. Lin, and O. S. Nakagawa, "An Efficient Inductance Modeling for On-chip Interconnects", IEEE Custom Integrated Circuits Conference, May 1999.

[2] Norman Chang, Shen Lin, O. Sam Nakagawa, Weize Xie, Lei He, “Clocktree RLC Extraction with Efficient Inductance Modeling”. DATE 2000

[3] M. Xu and L. He, "An efficient model for frequency-based on-chip inductance," IEEE/ACM International Great Lakes Symposium on VLSI, West Lafayette, Indiana, pp. 115-120, March 2001.

[4] F.W. Grover, Inductance Calculation, Dover, NY, 1962.[5] A.E. Ruehli, “ Inductance calculations in a complex integrate

circuit environment,” IBM J. Res. Develop., vol. 16, pp. 470-481, Sept. 1972.

[6] C. Hoer and C. Love, "Exact Inductance Equations for Rectangular Conductors with Applications to More Complicated Geometries," J. Res. Nat. Bureau of Standards--C. Eng. Instrum. 69C, No. 2, 127-137 (April-June 1965).

Page 58: Chapter 1 Interconnect Extraction

HW 1

1. Use FEM (finite element method) to calculate inductance, where formulae are used to calculate inductance for each filament or each pair of filaments

2. Build RC and RLC circuit models3. Compare waveform with RC and RLC circuit models

After we finish the second part of chapter 1, matlab code will be released with details and as a starting point


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