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CHAPTER 2

LITERATURE SURVEY

2.1 INTRODUCTION

The literature survey has been carried out in 3 phases. The first

phase focussed on LDPC Codes .The 2nd Phase on Projective Geometry

and Majority Logic decoding and the 3rd phase on p-adic extension of

PG LDPC Codes.

In the first phase, the introduction to LDPC Codes, their

construction,comparision is done in the references from [1],[9]-

[21].The decoding methodologies and various techniques are

discussed in references [22]-[40].The VLSI/FPGA implementation of

LDPC Codes is discussed in references [41]-[47].LDPC Codes design ,

parallel decoding architectures and related are discussed in

references[48]-[54]. Non binary ,quasi cyclic LDPC codes is the main

focus in my thesis and these are discussed in [55]-[60].

In the second phase, The finite Geometry and in particular

projective geometry based LDPC Codes performance of LDPC codes

are discussed in [61]—[79]. The majority Logic codes decoding

methodology is discussed in [80]-[[84],Galois Fields and Galois rings

based LDPC from [85]-[89],Lifting Techniques [5],[90]-[93]. The p-

adic arithmetic is discussed in [94]–[99].

In the 3rd phase, the useful information on the nanoscale memory

is discussed in [6],[100]-[106].In order to compare the performance of

PG LDPC over Reed Solomon (RS) Codes, the literature on RS codes is

39

obtained in [7],[107]-[109]. The application of PG LDPC Codes for fault

tolerance in computer networks using the Perfect Difference Networks

(PDN) and Perfect Difference Set and the generic conflict free

decoding of PG LDPC codes is documented in [110]-[120] .The

European standards for DVB is found [121]. Now, the literature

survey is detailed as per the above route map.

Gallager R.G [1] introduced LDPC code with various techniques of

construction and decoding methods

S.Lin and Costello [2] explained the Linear Block and cyclic codes,

finite geometry ,projective geometry , and majority logic decoding in

detail in different chapters in Prentice Hall first edition printed in

1981 and reprinted in 2010 .This is the main resource for this

research work.

Calderbank and Sloan [3] investigated the cyclic codes structure

over the ring of integers modulo p ( such that p is a prime and does

divide n). They generalized 2-adic binary Hamming code and the

quaternary. They worked on the 2-adic and 3 adic Golay codes.

2.2 LDPC Codes

2.2.1 On LDPC Codes & Its Construction:

Simon Haykin [9] explained LDPC codes ,its construction and the

methods of probabilistic decoding and irregular LDPC codes with an

example from page 683 to 693 in 4th edition of John Wiley publishers

J. H. Van Lint [10] provided the fundamentals in coding theory by

authoring the book on coding theory and discusses challenges in

coding theory

40

Mackay and others [11] reported Gallager’s LDPC’s empirical

performance of on Gaussian channels and showed that the

performance is comparable to turbo codes.

Benjamin Levine and others [12] proposed LDPC Codes for

wireless communication allowing higher data transportation using

the same spectrum , at the same time using appreciably small

transmission power and providing better security of data and the data

compression.

Jain Son [13] proposed LDPC codes which can overcome the

limitations like requirement of high complexity computation .

Sarah John Son [14] highlighted LDPC codes when the other codes

such as highly structured block and convolution codes were

dominant and showed that LDPC codes meet the Shannon limit,

while the others could not meet the same.

2.2.2 On Irregular LDPC Codes

Mackay, Wilson and Davey [15] succeeded in proposing LDPC

regular and irregular constructions allowing more rapid encoding

while its encoder requires small memory

Xia zheng, Lau et al [16] worked on avoiding Trapping Sets which

cause error floors LDPC codes. They introduced a parameter ‘e’ meant

to identify the number of "distinguishable" cycles in case of the

connected subgraph due to trapping set. They proposed Progressive-

Edge-Growth Approximate-minimum-Cycle-Set-Extrinsic-message-

degree (PEG-ACSE) method to avoid elementary trapping sets.

41

Tao Tian, Chris Jones [17] highlighted the problems in the cycles of the

graph, stopping sets, and the dependency of columns of the ‘parity check

matrix’ belonging to LDPC codes. They proposed Extrinsic Message Degree

method which measures the cycle connectivity.

Gianluigi and Shumei [18] provided EXIT chart technique which

determines close to the optimal degree distributions corresponding to

the LDPC code ensembles.

Thorpe J [19] used protograph as a blueprint for constructing

LDPC Codes and predicted the performance of the Codes by standard

density evolution method.

Deepak Sindhara, Christine Kelley and Joachim Rosenthal [20]

used a tree-based construction of LDPC codes that having minimum

distance suitable for iterative decoding. P-ary LDPC codes which

improve minimum distances, and pseudo codeword weights using the

finite-geometry for p >2.

Thomas Richardson and Rudiger Urbanke [21] investigated on

exploiting the low density of non zeros in the parity check matrix for

obtaining efficient linear time encoding which otherwise is a

quadratic time complexity for LDPC Codes.

2.2.3 On Decoding of LDPC Codes

Jon Feldman, David Karger and Martin Wairight [22] presented

the algorithms for decoding Turbo codes which has unprecedented

error correcting performance and LDPC codes with simple encoding

42

and belief propagation decoder . They tested the suitability of LDPC

codes for channels of binary erasure and the bounds for error

performance.

Goupil, Colas and others [23] presented a decoding scheme based

on belief propagation , having the same complexity to that over the

finite fields

Michael Lentmaier and Gerhard Fettweis [24] did a threshold

analysis of terminated generalized LDPC convolutional codes (GLDPC

CCs). The belief propagation decoding thresholds of Projective

Geometry based GLDPC CCs, coincide with the ML decoding

thresholds under some conditions.

Noam Presman and others [25] described an interesting LDPC

decoding schedules based on serial approach by dividing the Tanner

graph to sub-graphs ,yielding simple complexity of circuitry and

improved performance upon the standard schedules. They predicted

the behavior of different schedules.

Theocharides T, Link G [26] while working on wireless

communication ,proposed suitable LDPC decoder architectures in

wireless and also in disk drives. The concept is based on NOC fabric

, providing a 1.2 Gbps output throughput rate , 1KB-bit block LDPC

code and reduced the consumption by by optimization ,up to 30% .

43

Gunnam K, Choi G and Yeary M.B, [27] constructed structured LDPC

codes without comprising performance degradation which achieves

data independency between nodes of Tanner graph. This approach

has huge memory savings of by about 75% and helps in reducing the

overall memory accesses by 66%.

Radosavljevic, Alexandre [28] presented a pipelined LDPC decoder

having high throughput ,supporting multiple code rates and different

codeword sizes . This decoder achieved data throughput nearly 1 Gb/s

while not sacrificing error-correcting performance.

Tong Zhang and Keshab Parhi [29] used partly parallel realization

to simplify the complexity of the fully parallel decoder architecture.

Fossorier Marc et al [30] presented different versions of the belief

propagation methods for faster decoding of LDPC Codes on the AWGN

channel . The two algorithms, yielded a good performance and the

tradeoff with the complexity.

Eleftheriou et al [31] described different LLR-BP decoding

algorithms for LDPC codes. Two approaches for check-node updates

were introduced using the popular min-sum approximation .This

paper provides choice in choosing the correct scheme based on the

parameters like performance, the speed or required delay,

computational-complexity, and requirement of memory.

Hocevar [32] applied a layered belief propagation decoding to

irregular partitioned permutation LDPC codes which improves the

44

decoding performance by 2 times by 45-50% and the overall decoder

architecture can be reduced nearly 50% .

Quaglio, Vacca and Masera [33] designed a novel flexible decoder

that can decode different codes resorting to the same hardware.

Karkooti and Cavallaro [34] presented a revised version of Min-

Sum technique to do simple computations than Sum-Product

technique while maintaining the same performance. This design can

be easily scaled and importantly , for large size block, it is

reconfigurable.

Cocco, Dielissen [35] presented random LDPC codes to avoid the

routing congestion problem with the help of many number of

independent decoding sequential machines for every received

codeword. This method saved huge memory and proved that a simple

serial approach works .

Mohammad Mansour et al [36] designed a core-based

methodology, a new of its kind , for the LDPC decoders which are

programmable . This method significantly reduces interconnect

complexity, having message processing units set in paralelly and

transport networks which are scalable, for routing the messages with

power optimizations . It delivers a throughput of around 6.4 Gbps at

the frequency of 125 MHz and takes a power of 787 mW .

Chris Howland and Andrew Blanksby [37] implemented a 1KB bit

half rate LDPC decoder, supporting throughputs up to 1Gb/s and an

45

appreciable minimum switching activity with a desired power

dissipation of less than 220mW.

Brack, Kienle et al [38] highlighted the major problem in decoder

realization i.e., very large design space which is composed of the

related parameters enforcing drastic trade-offs in the design. They

presented a generic architecture with constrained parameters .

Huang [39] presented a variant of min-sum technique known as

single-scan version for faster decoding .This version reduces memory

usage and just needs the only one addressing from the check nodes

to corresponding variable nodes while the old min-sum algorithm

requires one more additional addressing.

2.2.4 On VLSI Based and Parallel Decoding of LDPC Codes

Christian Spagnol and Emanuel Mihai Popovici [40] proposed a

new variant of the belief propagation technique for Galois Field

extended LDPC codes and implemented on an FPGA.This

implementation is applicable for codes of short to medium length.

Zhong.H and Zhang.T [41] presented an important partial VLSI

suitable semi random design for the construction of LDPC decoder.

Tong Zhang and Keshab Parhi [42] constructed a class of regular

LDPC codes meant to fit exactly, a partly parallel VLSI based decoder

implementation for exact fitting and implemented efficient encoder.

Lee and Angus Wu [43] presented an application using a low

complexity digital decoder architecture for cellular communication

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without using complex combinational arithmetic, exponent

computations.

Hao Zhong and Tong Zhang [44] Recently highlighted semi-random

design scheme to construct the LDPC codes to fit the partially parallel

VLSI decoder implementation.This approach achieves nearly same

performance comparable to random design and fits into VLSI

implementation while the random scheme does not .

Yang, Shen, Liu and Shi [45] , keeping in mind the different

interference conditions existing in wireless communication, proposed

a multi-rate decoder of LDPC using Xilinx FPGA device. It can provide

very small BER at SNR of 1.4dB using irregular ½ mode in the worst

conditions.

Jason Kwok-San Lee [46] presented a scalable decoding

architecture using a protograph for producing a (4096,2048) LDPC

decoder working on 31Mbps using limited iterations.

Chandrasetty, V.A., Aziz, S.M [47] implemented a decoder based

on modified 2-bit Min-Sum algorithm on FPGA .This method has an

improvement of 1.5 dB Eb/No at 10-5 Berthas requires fewer decoding

iterations compared to original 2-bit Min-Sum algorithm and achieves

an average throughput of 10.2 Gbps at 4 dB Eb/No.

Sankar and Narayanan [48] presented LDPC codes that reduce the

memory requirement at the decoder and showed how to design good

LDPC codes .

47

Zhong et al [49] constructed Block-LDPC codes with efficient

encoder and decoder suitable for hardware realization.

Howland C and Blanksby [50] aimed at high coding gain with a

very low power dissipation and at the same time, to produce high

throughput using parallel architecture for decoding LDPC codes. This

is really a sort of all in one achievement.

Jilei Hou, Paul Siegel [51] proposed a technique of coding and

modulation where, the modulator receives the coded bits directly from

an irregular code .This is suitable for MIMO type fading channels .The

receiver shows the performance improvement.

Zhong and Havlicek [52] proposed a new scheme based on LDPC

codes in a robust wireless image transmission system. The system

performance for SNR per bit ranges from 1.6 to 2.1 dB .

Harihara,Girish Chandra,Suryanarayana Adiga and Pramod [53]

applied LDPC codes in the DVB-S2 standard to achieve an improved

error correction performance.

Harihara, Girish and Suryanarayana Adiga [54] applied LDPC

codes in WiMAX (802.16e) standard for mobility. They simplified the

decoder to replace the Viterbi decoder with one decoder instead of two

decoder structures.

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2.2.5 On Non Binary and Quasi Cyclic LDPC Codes

Alban Goupil and David Declercq [55] provided the need of the

next generation by providing a nonbinary LDPC coding schemes

using the method called unequal error protection (UEP) makes the

code more robust and protects the symbol error properties as well .

Hongxin Song and Cruz [56] worked on magnetic recording

channels using LDPC codes in AWGN environment .

Zhou, Kang, Song [57] proposed an alternative to RS codes by

cyclic codes which are nonbinary LDPC codes without comprising the

performance .

Chen, Bai, et al [58] constructed nonbinary LDPC ,(which can be

made quasi-cyclic codes) using cyclic maximum distance separable

(MDS) code requiring finite field operations, integer additions and

integer comparisons. They also used low-complexity nonbinary

massage-passing decoding algorithm.These codes can be applied in

communication or storage systems where high-speed and low-power

consumption are the requirements .

Li, Chen, Zeng, Lin, Fong [59] found that Quasi-cyclic - LDPC

codes form generator matrices in systematic-circulant using the

parity-check matrices.

Wang, Bai and Ma [60] presented a non-binary LDPC coded

modulation systems which combines hard-decision decoding using

the message-passing strategy with the signal detector in an iterative

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manner. It requires low computational complexity, offers good system

performance and has a fast rate of decoding convergence .

2.3 ON EUCLIDEAN & PROJECTIVE GEOMETRY BASED LDPC

CODES

Singer [61] used points in a finite projective plane PG (2, pn),

represented as the symbol (x1, x2 ,x3) using GF(pn). The totality of

points whose coordinates satisfying the equation u1x1+ …+ u3x3 = 0,

where the coefficients u1, u2, u3 ≠0, marks of the GF (pn) is called a

line. The plane then consists of p2n+pn+l = q points and q lines.

Yu Kou, Shulin et al [62] constructed geometry based LDPC codes

for higher minimum distance and classified 4 classes of LDPC codes

were proposed using the EG, PG in finite field approach. Their Tanner

graphs girth can be minimum of 6. They are best suited for iterative

decoding and can be form cyclic or a quasi cyclic codes.

Shu lin, Heng Tang et al [63] used hyper planes method for

constructing geometry based LDPC codes, suitable for decoding using

multi step MLD scheme.

Hartmann, Ducey [64] provided the structure of generalized finite-

geometry codes with newly found ideas on structures .

John Craddock [65] increased the girth to 8 in the bipartite graph

using a new method and presented a new method with the help of

structural properties of lattice geometries.

Karmarkar N.K [66] introduced a new parallel architecture to

exploit the sparse matrix computations. Using the geometry structure

, an efficient hardware has been developed.

50

Saad Bin Qaisar [67] applied the LDPC Codes to variety of

channels and could enhance their performance by applying to proper

channels .

Junho Cho,Jonghong Kim,Wonyong Sung [68] introduced a

combination of Bit Flipping and Soft Bit Flipping algorithms for

decoding the PG LDPC codes .This can be used to reduce the decoding

time. The projective-geometry LDPC codes of (1057, 813) and (273,

191) were tested.

Weldon [69] proposed a suitable choice of generator polynomial

which guarantees the polynomials corresponding to all subspaces in

Euclidean geometry will be in the null space of the code and helps in

deriving minimum distance bound on the lower side .

Zeng, Lan et al [70] used geometrical approach for LDPC codes of

non binary type.This method gives large coding gain compared with

RS codes using hard or soft decision decoding.

Beutelspacher, A. and U. Rosenbaum [71] authored a book on

projective geometry from fundamentals to applications .This is very

informative and is a good reference to study projective geometry and

its applications .

Bharadwaj , Rajeev and Narendra Karmarkar [72] solved the

interconnections between the processors , which otherwise posed a

problem to convert into parallel machines by a new parallel

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architecture. They achieved good results in pipelined memory and a

pipelined multiplier.

Joseph B.Attili [73] investigated LPDC codes with finite geometry

approach and has presented a detailed comparision of the different

type of decoding methods and their performance .This is very

informative to understand the performance of the codes based on

different decoding techniques.

Janakiram,Suryanarayana Adiga et al [74] used PGLDPC codes for

wireless applications.These codes are popular due to ease of encoding

and decoding by the simple majority logic technique. They presented

the performance of these codes for different decoding

algorithms.They modified the codes by shortening (rate reduction)

and Chase Combining for use in wireless applications .

Harihara, GirishChandra, Taraka Praveena and B.Suryanarayana

Adiga [75] proposed three novel architectures ,the first being parallel

and the other two being semi-parallel decoder architectures for

popular PG-based LDPC codes. These architectures are memory clash

free and are reconfigurable for different lengths for different

corresponding rates . They can be configured for the regular belief

propagation based decoding as well as majority logic decoding (MLD) .

Ivan Djordjevic [76] applied LDPC codes in high speed applications

such as long-haul optical based communication systems using

geometric approach. These codes have dual advantage of higher

minimum distance and simple decoding algorithms.

52

Fangni Chen [77] emphasized the construction of projective

geometry LDPC code, simulated and found that they are strong

competitors to FEC codes .

Junho Cho, Jonghong Kim [78] Implemented a projective-geometry

(PG) LDPC code using soft bit flipping (SBF) algorithm which requires

only simple interconnections but its performance is on par SPA.

Parallel processing architecture was employed for increasing the

throughput. A 4-bit SBF decoder implemented on a small area of 2.5

mm 2 while providing 6.5 Gbps .

Sheng Mei ,Zhao,Xiu-Li Zhu,Guo-Jun Sun [79] constructed

quantum LDPC based on Projective Geometry over the bit-flipping

channel .

2.4 ON MAJORITY LOGIC DECODING

Chin-Long Chen [80] proposed a decoding algorithm based on

finite geometry codes .These codes can be orthogonalized in maximum

of three steps and are majority-logic .

Huang, Kang [81] used two new reliability-based MLD scheme to

decode LDPC codes requiring only integer additions , simple logical

operations, integer additions. They offer effective trade-offs between

performance and decoding complexity .

K.J.C Smith [82] authored the book titled “Majority decodable

codes derived from finite geometries”, detailing the importance of

53

majority logic decoding in the context of finite geometry and the

corresponding codes suitable for this purpose to simplify the decoder

construction .

Rathnakumar et al [83] presented a very convincing

combinatorial scheme to calculate the exact BER in case of one-step

MLD applicable to nanoscale memories

JM.Goethals and P.Delsarte [84] used simple yet powerful codes

using infinite class of cyclic codes based on majority. They are

comparable with Bose-Chaudhuri codes .

Matthew Davey and David Mackay [85] used finite field based

LDPC codes showing very good performance improvement for the

Gaussian channel, 1/4 rate code with bit error probability of 10-4

with Eb /N0=-0.05 dB .

2.5 ON GALOIS FIELDS & RINGS BASED LDPC CODES

Lan Lan,Lingqi Zeng et al [86] worked on finite fields. These fields

which were earlier used to construct cyclic codes (for BCH and

RS codes which are hard decision based) are now used to construct

algebraic iterative based soft decision based LDPC codes for iterative

soft-decision decoding and are quasi-cyclic.This yields low error floors.

Daiel Katz [87] presented a theorem using p-adic valuation of

weights of Hamming code. The corresponding words in case of cyclic

codes extended them to code such as Abelian over Galois rings.

Interlando, Palazzo and Elia [88] introduced decoding procedure

of 4 steps over an integer residue ring pgZq (where q is a power of a

prime p), for popular Reed-Solomon codes .It is applied to the

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synthesis of a LFSR and can generate elements (forming a sequence)

in commutative ring .

Marc Armand and Ng K [89] highlighted a multistage decoding

approach to exploit the natural ring .This provides an extra coding

gain in the range of 0.07-0.1 dB.

2.6 ON VARIOUS LIFTING TECHNIQUES

Reza Asvadi, Amir Banihashemi [90] reduced the error floors by the

concept of cyclic liftings in LDPC codes. The liftings are designed to

eliminate short cycles which form the trapping sets. This method is

very generic for any channel for any decoding algorithm, iterative in

nature.

Xudong and En-hui Yang [91] used just two lifts to construct new

LDPC codes which having efficient hardware implementations and low

error floors .These codes posses low error probabilities over binary the

erasure channels .

Chih-Chun Wang [92] designed cyclic lift of the short block length

codes to reduce the frame error rate and also to reduce error floors

while maintaining the performance. This approach helped in finding

ensemble FER error floor .

Christine Kelley [93] studied the theory of voltage graphs which

provides the designing aspects of the lifts of graphs with exclusive

properties and constructed LDPC codes by choosing the permutation

voltages and illustrated its usefulness .

55

2.7 ON ‘P-adic’ ARITHMETIC

Krishnamurthy , Venu [94] presented a quick iterative scheme

for finding the reciprocal of a finite segment belonging to p-adic

numbers. This helped in finding inverse transform of the very

popular and useful Hensel code .

Lavinia Egidi [95] addressed the complexity of the decision

problem related to the theory related to p-adic numbers. The bound

for the lower side is twice exponential with alternating time having

alternations that are linear in number.

Jay Thomas and Sydney [96] used a technique using single-

modulus P arithmetic which can be used for correct calculations in

the domain of rational and complex numbers .

Gary McGuire [97] factored polynomials over Z using Euclidean

algorithm. The lift of a polynomial can be made faster using the

connection between Hensel’s Lemma and the polynomial’s roots are

nothing but the pth powers of the roots of a given polynomial .

Michele Elia [98] used the lifting over the finite rings Z2m and Z3

m

for Golay codes and also on 2-adic and 3-adic rings whose algebraic

decoding is an extension of the perfect Golay Codes .

Shu lin [99] highlighted combinatorial based expressions for the

the polynomial codes adopting information symbols and parity-check

symbols and applied to the PG codes and EG codes .

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2.8 ON NANOSCALE MEMORY

Shalini Ghosh, Patrick D. Lincoln[100] proposed Euclidean

Geometry LDPC (EG-LDPC) codes to correct soft errors in memory

codes which enables one to adjust the error correcting capacity

dynamically for improved system performance (e.g., lower power

consumption) during the periods normal operation where expected

fault arrival rate is low. The architecture has dynamic fault tolerance.

Susmit Biswas et al [101] found that the bit error rates are high in

nanoscale memory system. This unreliable bits can be bootstrapped

into contiguous address ranges into memory pages by using error

correction dynamically within thirty two bit blocks to achieve a very

good memory efficiency of sixty percent whereas thirteen percent for

four kilo -byte pages

M. Forshaw, et al [102] reviewed the scope of reducing the

nanodevices size less than CMOS technology through architectural

changes .The other parameters are the performance and power

dissipation, the parallelism to speed up the decoding , design of

robust i,e, fault tolerance decoding ,fabrication of the large circuits.

DeHon, Goldstien et al [103] working on technologies without

using photolithography .Some of the nanoscale circuits as well as

memories where the active devices as small as few nanometers

square.

DeHon [104] pointed out the high defect rates in molecular-sized

devices and proposed design with spare components to map based

57

around the defective elements. He characterized the area for this

addressing scheme.

Sun et al [105] proposed 2 fault tolerant design approaches for

fault-prone hybrid CMOS or digital based nanodevice memories. They

used BCH codes for the first one in defect tolerance and the second

one in transient fault tolerance, It suffers from storage capacity which

is reduced when the defect densities and/or fault rates which are

transient, starts increasing. The alternative provided can give better

storage capacity.

Bo Fu Ampadu, P [106] presented a hybrid ARQ (HARQ) scheme

using single-error correcting burst-error detecting (SEC-BED) codes to

address multiple errors in nanoscale on-chip interconnects. The

proposed HARQ method yields 20% energy improvement over other

burst error correction schemes. It can reduce delay uncertainty

caused by capacitive coupling and is suitable for implementation in

reliable and energy efficient on-chip communication

2.9 ON REED SOLOMON CODES

Farnaz Shayegh and Reza Soleymani [107] introduced a bit level

belief propagation (BP) decoding for Reed Solomon codes and reduced

number of 4-cycles .This method helped in improving performance of

RS codes, compared to hard decision decoding .

R.T.Berlekamp [108] authored the book on algebraic coding theory

which elaborates the coding theory .He developed a very popular

decoding scheme for RS codes meant for detecting the burst type of

errors .

58

Richard Blahut [109] discussed a decoder which works on the raw

data word, bypassing the either syndrome calculation or power-sum-

symmetric. These decoders can decode any RS or BCH codeword.

2.10 ON PDNs & GENERIC ARCHITECTURES OF LDPC CODES

Parhami and Rakov [110] found Perfect Difference Networks

(PDNs) to simplify the network using the notion of perfect difference

sets. PDNs are quite resistive to faults, both with respect to failures in

node and link .The fault diameter of PDNs is a maximum of 4 . PDNs

offer optimal performance and fault tolerance relative .

B. Parhami and C.-H. Yeh [111] indicated that in a network , the

congestion and queuing delays can be reduced) and in a shortest

path routing, the network diameter indicates the accurate

communication delay .

Parhami and Rakov [112] proposed a PDN with diameter two, such

that one can reach to a particular node in just one or two hops. The

perfect difference sets scheme can accommodate an asymptotically

highest node with the least node degree. The concept can be used in

wireless and optical interconnects.

Parhami and Rakov [113] in a companion paper, focused on

deriving low-diameter networks for example ‘two’ . PDNs allow Order

of d2 nodes, where d is the degree of nodes, or in other words, one can

state an important PDN rule that ‘ The degree of the node increases

as the square-root of the size of the network’ . PDN’s symmetry and

its rich connectivity lead to prime requirement of

59

communication traffic which is balanced and at the same time, has

good fault tolerance. When generalized, one can state that node degree

can grow as the (2q)th root of no. of nodes .

Malema and Liebelt [114] suggested an interesting network

concept of Benes which is a self routed network based on the LDPC

communication pattern . Edge coloring was used in the Bipartite

graph to schedule messages to avoid switching network output

conflicts with the help of the looping routing algorithm for Benes

networks.

Guilloud [115] proposed irregular LDPC codes in next digital

satellite broadcasting standard (DVB-S2) to protect the downlink

information. A generic architecture of an LDPC decoder on a FPGA

enables to speed up the simulations more than 500 times as against

software simulations. The proposed framework encompasses both the

data path (i.e., parallelism, node processors architectures) and the

control mode which is associated to the several decoding schedules.

Arden and Lee [116] published Chordal Rings ,a family of regular

graphs having n nodes wherein maximum length message path, is

shown to be of 0(n1/2). This helps in the determination of alternate

paths , if the node or link failure occurs.

Atheer Abbas [117] worked on Communication in chordal rings

networks. When several parallel computers configured in chordal ring

topology, the performance can be improved by decreasing the

diameter. A compact routing approach helped in minimizing the space

and time complexity in such networks .

60

Hobbs, A.M., [118] proposed strategy to build network such that It

should survive a limited attack, including attacks aimed at other

nearby targets and that a network should be bland i.e., it has no

parts especially attractive to attack. The techniques for network

survivability are explained. This topic appears in the text book ‘

“Applications of Discrete Maths’ by Michaels,Rosen, McGraw-Hill.

Parhami, B [119] authored the book “Introduction to Parallel

Processing: Algorithms and Architectures” published by Plenum, New

York, discussed the architectures suitable for parallel processing. The

context of speeding up the communication between the nodes in a

network is detailed .

Parhami, B. and D.M. Kwai [120] found that all the chordal ring

networks have same in/out degree and interconnection pattern

resulting in no scalability .Hence they proposed periodically regular

chordal (PRC) ring networks for combining small node degree along

with tiny diameter. With variable ring parameters, one can obtain

architectures from linear to logarithmic diameter while maintaining an

elegant framework for computation and communication while

retaining the advantages of software portability and fault tolerance .

ETSI [121] is an European Standard for DVB-S2 characterized by a

powerful FEC system. It is based on LDPC codes combined with BCH

codes for Quasi-Error-Free operation at about nearly unity ‘dB’ close

to Shannon limit .

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2.11 CONCLUSIONS

The literature survey is done on various related topics such as

LDPC codes, projective geometry based LDPC codes, majority logic

decoding, Galois field and Rings based LDPC codes, p-adic arithmetic,

Nanoscale memories, RS codes for comparison with PG LDPC codes,

Perfect Difference Networks concept for application of PG LDPC codes.

The problem definition is narrowed down from the above topics

using first 8 references which are the main resources for this

research work. The detailed description on each of the major topics

such as LDPC codes, PG Codes, Majority Logic Decoding, P-adic

arithmetic, Lifting concept are covered chapter wise in the following

chapters.