Chapter Chapter 8 8 ppIntroduction to 3D Introduction to 3D
Integration Technology Integration Technology i TSVi TSVusing TSVusing TSV
Jin-Fu LiJin Fu LiDepartment of Electrical Engineering
National Central UniversityNational Central UniversityJungli, Taiwan
Outline
Why 3D Integration A E l TSV P FlAn Exemplary TSV Process FlowStacking Strategiesg gConcept of 3D IC DesignSSummary
Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 2
IC Technology Evolution
ChipChip
Single-chip package
Printed wiring board(PCB) RF
Analog
Package
Flash
CPU
Other
Chemical &Bio Sensors
Package
3D-SIPRF
ADCDAC
NanoDeviceMEMS
Other Sensors,Imagers
Processor
Memory Stack
DAC
Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU
3D-IC Energy/Power
Why 3D IntegrationIntegrating more and more transistors in a single chip to support more and more powerful functionality is a trend
Using 2D integration technology to implement such complex chips is more and more expensive and difficult
S l i h l i i Some alternative technologies attempting to cope with the bottlenecks of 2D integration
h l h b dtechnology have been proposed3D integration technology using through silicon g gy g gvia (TSV) has been acknowledged as one of the future chip design technologies
Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 4
3D Integration Technology Using TSV
3D integration technology using TSVMultiple dies are stacked and TSV is used for the Multiple dies are stacked and TSV is used for the inter-die interconnection
Die 1Die 2
Die 3
TSV
The fabrication flow of a 3D IC Di / f ti
TSV
Die/wafer preparationDie/wafer assembly
Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 5
What is TSVThrough Silicon Via (TSV):
A via that goes through the silicon substrate Used for dies stacking
Top Bump
i i l
CMOSDiameter
Al wiring TSVWiring layer
Diameter50 um or less
Top Bump
SiO2 insulatorVia made by laser
Typical TSV technologiesVia first via middle and via last technologies
Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 6
Via-first, via-middle, and via-last technologies
Via-First TSV TechnologyVia-First TSV
(1) Before CMOS
(2) After CMOS & BEOL
Source: Yole, 2007.
Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 7
Via-Last TSV TechnologyVia-Last TSV
(1) After BEOL & before bonding
(2) After bonding
Source: Yole 2007
Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 8
Source: Yole, 2007.
An Exemplary Via-Last Process Flow (1/6)
Step 1: A wafer with CMOS circuits
… … …
MOSFET MOSFETRef :ITRI
Substrate
Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 9
An Exemplary Via-Last Process Flow (2/6) Step 2: via etching
… … …Via machining(by etching or laser dilling)
MOSFET MOSFET
Substrate
Ref :ITRI
Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 10
An Exemplary Via-Last Process Flow (3/6) Step 3: via filling
… …… Via filling
MOSFET MOSFET
S b
Ref :ITRI
Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 11
Substrate
An Exemplary Via-Last Process Flow (4/6) Step 4: wafer thinning
… … …
50 ~ 100 μm
Wafer thinning
50 100 μm
Ref :ITRI
Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 12
g
An Exemplary Via-Last Process Flow (5/6) Step 5: micro bump forming
Micro Bump
… … …
Ref :ITRI
Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 13
An Exemplary Via-Last Process Flow (6/6) Step 6: stacking
… …
TSV
… …
TSV
Micro (μ) Bump
ABF(Ajinomoto B ilt i Fil )Built-in Film)
… … ……Ref :ITRI
Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 14
An Exemplary 3D IC using Via-Last TSV
Bonding Bonding
P-Substrate 3rd ChipAdhesive Adhesive
N Well N Well N Well
TSVN+ N+ N+ N+ N+ N+ N+P+P+P+P+P+
P-Substrate 2nd Chip
N Well N Well N Well
TSVN+ N+ N+ N+ N+ N+ N+P+P+P+P+P+
N
P-Substrate 1st Chip
Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 15
3-Tier 3D IC Cross-Section
Source: E. G. Friedman, University of Rochester.
Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 16
Die/Wafer AssemblyBonding technologies for 3D ICs
Wafer-to-wafer (W2W) Die-to-Wafer (D2W) and Wafer to wafer (W2W), Die to Wafer (D2W), and Die-to-Die (D2D)
Comparison of different bonding technologiesComparison of different bonding technologies
D2D D2W W2WYieldFl ibilit
HighHi h
HighG d
LowPFlexibility
Production ThroughputHighLow
GoodGood
PoorHigh
Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 17
Stacking Strategies
μ Bump μ Bump μ Bump
Die2TSV
D2D Vias
Metal
Active SiDie1
Bulk Si
face-to-face back-to-back face-to-back
Lewis D L et al “A ScanIsland Based Design Enabling Prebond Testability in DieStacked Microprocessors ”
face-to-face back-to-back face-to-back
Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 18
Lewis, D.L. et al, A ScanIsland Based Design Enabling Prebond Testability in DieStacked Microprocessors, in proc. IEEE International Test Conference (ITC), 2007, pp. 1-8
Fabrication Steps for Face-to-Face Stacking
Die211 22 33 44 55Die2Die2
Die233 55
Metal
Active Si
Bulk Si
Metal
Active Si
Bulk Si
Metal
Active Si
Bulk Si
Metal
Active Si
Bulk Si
Metal
Active Si
Bulk SiBulk Si
Die1 Die2 Die1
Bulk Si
Die1 Die2
Bulk Si Bulk Si
Die1
Bulk Si
Die1
Loh, Gabriel H. et al, “Processor Design in 3D Die-Stacking Technologies,” in IEEE Micro, vol.27, issue 3, pp. 31-48, 2007
Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 19
Fabrication Steps for Face-to-Back Stacking
Die2 Die211 22 33 44 55
Handle wafer
Metal
Active Si
Bulk Si
Metal
Active Si
Bulk Si
Metal
Active SiBulk Si
Metal
Active Si
B lk Si
Metal
Active Si
B lk SiBulk Si
Die1 Die2Bulk Si
Die1 Die2Bulk Si
Die1 Die2Bulk Si
Die1Bulk Si
Die1
Loh Gabriel H et al “Processor Design in 3D Die Stacking Technologies ”Loh, Gabriel H. et al, Processor Design in 3D Die-Stacking Technologies, in IEEE Micro, vol.27, issue 3, pp. 31-48, 2007
Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 20
Electrical Characteristics of TSV
Capacitance of TSVTop Bump
CMOS
Top Bump
Diameter
Al wiring TSVWiring layer
DiameterTSV Length
Dielectric Thickness
TSV Dia TSV Diel TSV Length Cap [fF]TSV Dia[um]
TSV DielThk [nm]
TSV Length[um]
Cap [fF]
5 50 20 239.5
5 100 20 135 25 100 20 135.2
10 50 20 496.4
10 100 20 288.3
Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 21
0 00 0 88.3
Source: Proceedings of IEEE, pp. 101, Jan. 2009
RC Characteristics of TSV
1 FO4 = 22 ps
Die1
Die2~ 0.35*RCviastack
D v
ia
p(BSIM 70nm)
M9
via9
D2D
225 ps
… … M2 RCviastack
1-mm top-level metal
4x minimum size
> 11 FO4
M1
i 1
via24x minimum size
F2F D2D i8 ps
MOSFET
via1 F2F D2D via ~ 1/3*FO4
Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 22
Loh, Gabriel H. et al, “Processor Design in 3D Die-Stacking Technologies,” in IEEE Micro, vol.27, issue 3, pp. 31-48, 2007
Benefits of 3D IntegrationBenefits of 3D integration over 2D integrationintegration
High functionalityHigh performanceSmall form factorLow energy
Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 23
Source: Proceedings of IEEE, Jan. 2009
High Functionality
Heterogeneous integrationCombine disparate Chemical &
Bi SCombine disparate technologies
DRAM, flash, RF, etc.
Other Sensors,Imagers
Bio Sensors
, f , ,Combine different technology RF
NanoDeviceMEMSgy
nodesE.g., 65nm technology and 45nm t h l
ADCDAC
technology
Processor
Memory Stack
Energy/Power
Processor
Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 24
Source: Proceedings of IEEE, Jan. 2009
High Performance
3D integration technology can reduce the length of the long interconnections using TSVlength of the long interconnections using TSVFor example,
By
x x
B
x x
1 2y
1 2 z
3 4
A
y y 3 4
AA
L2D=x+2y L3D=x+y+z
Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 25
3D y
High Bandwidth3D IC allows much more IO resources than 2D ICICFor example,
Stacking of processor and memoryStacking of processor and memory
Memory Memoryy Memory
CPUCPU
B d idth i li it d b IO Many TSVs are allowed for
Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 26
Bandwidth is limited by IOs yhigh bandwidth transportation
Low Energy
SOBEnergy
SIPRF
AnalogFlash
CPU 3D IC
Package
CPU
RF
3D-IC
SRAM
Flash
Analog
CPU
Package
SRAM
Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 27
Technology
3D IC Design Approaches
L2 D$robIdq
bpredrf
rs
CPU
L2
L2
MultipleCores
I$tlbIF
bpred
alu stq
L2 L2dec
F ti U it Bl k (FUB)Entire Core
VDD
Function Unit Block (FUB)Entire Core
gndX
Y
Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 28
Transistors (circuit) LevelLogic gates (FUB splitting)
2D RAM
WordlinesBitlines
Blo
ck 0
WL
Dec
Blo
ck 1
WL
Dec
Blo
ck 2
WL
Dec
Blo
ck 3
WL
Dec
BW
Mux & SA
BW
Mux & SA
BW
Mux & SA
BW
Mux & SA
WL Pre DecAddress input
4c
Mux & SA
4cMux & SA
4c
Mux & SA
4c
Mux & SA
WL Pre-DecData output
Ls
Blo
ck 4
WL
De
Blo
ck 4
WL
De
Blo
ck 4
WL
De
Blo
ck 4
WL
De
128
WL
256 BLsRAM Subarray
Y.-F. Tsai et al, “Design Space Exploration for 3-D Cache,”
Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 29
IEEE Transactions on Very Large Scale Integration (TVLSI), vol.16, issue 4, pp. 444-555, 2008
3D Wordline-Partitioned RAM
-2ec -2ec -2ec -2ec
k 0-
2
Dec
k 1-
2
Dec
k 2-
2
Dec
k 3-
1
DecB
lock
0
WL
De
SA 0 2
Blo
ck 1
WL
De
SA 1 2
Blo
ck 2
WL
De
SA 2 2
Blo
ck 3
WL
De
SA 3 2
Blo
ck
WL
SA 0-2
Blo
ck
WL
SA 1-2
Blo
ck
WL
SA 2-2
Blo
ck
WL
SA 3-1
SA 0-2
WL Pre-DecAddress inputData output
SA 1-2 SA 2-2 SA 3-2
SA 4-2 SA 5-2 SA 6-2 SA 7-22WL Pre-Dec2 2
SA 4-2
SA 5-2
SA 6-2 SA 7-1
lock
4-2
WL
Dec
SA 4 2
lock
5-2
WL
Dec
SA 5 2
lock
6-2
WL
Dec
SA 6 2
lock
7-2
WL
Dec
SA 7 2
128
WLs
Blo
ck 4
-2
WL
Dec
Blo
ck 5
-2
WL
Dec
Blo
ck 6
-2
WL
Dec
Blo
ck 7
-1
WL
Dec
BlW BlW BlW BlW
128 BLs
Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 30
Y.-F. Tsai et al, “Design Space Exploration for 3-D Cache,” IEEE Transactions on Very Large Scale Integration (TVLSI), vol.16, issue 4, pp. 444-555, 2008
3D Bitline-Partitioned RAM
c c c c
Block 0 2WL ec Block 1 2WL ec Block 2 2WL ec Block 3 1WL ec
Block 0-2
WL
De
Mux & SA
Block 1-2
WL
De
Mux & SA
Block 2-2
WL
De
Mux & SA
Block 3-2
WL
De
Mux & SABlock 0-2W D
e
Mux & SA
WL Pre Dec
Block 1-2W De
Mux & SA
Block 2-2W De
Mux & SA
Block 3-1W De
Mux & SAWL Pre-DecAddress input
Data output
c
Mux & SA
c
Mux & SA
c
Mux & SA
c
Mux & SAWL Pre-Dec
Bl k 4 1Dec
Mux & SA
Bl k 5 1Dec
Mux & SA
Bl k 6 1Dec
Mux & SA
Bl k 7 1Dec
Mux & SA
WLs
Block 4-2
WL
Dec
Block 5-2W
L D
ecBlock 6-2
WL
Dec
Block 7-2
WL
Dec
Block 4-1
WL
D Block 5-1
WL
D Block 6-1
WL
D Block 7-1
WL
D
64 W
256 BLs
Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 31
Y.-F. Tsai et al, “Design Space Exploration for 3-D Cache,” IEEE Transactions on Very Large Scale Integration (TVLSI), vol.16, issue 4, pp. 444-555, 2008
Design Example: 3D RAM
Source: G. H. Loh, ISCA 2008
Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 32
Road Map of 3D Integration with TSVs
Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 34
Source: Proceedings of IEEE, Jan. 2009
Summary
3D integration technology using TSV is one of future IC design technologiesIt can offer many advantages over the 2D y gintegration technologyHowever there are some challenges should be However, there are some challenges should be overcome before volume-production of TSV-based 3D IC becomes possiblebased 3D IC becomes possible
Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 35