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VI - Sequential Logic © Copyright 2004, Gaetano Borriello and Randy H. Katz 1
ECE2072/TRC2300/TEC2172 Sequential logicCOMMONWEALTH OF AUSTRALIA
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Sequential circuitssimple circuits with feedbacklatchesedge-triggered flip-flops
Timing methodologiescascading flip-flops for proper operationclock skew
Asynchronous inputsmetastability and synchronization
Basic registersshift registerssimple counters
Hardware description languages and sequential logic
VI - Sequential Logic © Copyright 2004, Gaetano Borriello and Randy H. Katz 2
C1 C2 C3
comparator
value
equal
multiplexer
reset
open/closed
new equal
muxcontrol
clock
comb. logic
state
Circuits with feedbackoutputs = f(inputs, past inputs, past outputs)basis for building "memory" into logic circuitsdoor combination lock is an example of a sequential circuit
state is memorystate is an "output" and an "input" to combinational logiccombination storage elements are also memory
Sequential circuits
VI - Sequential Logic © Copyright 2004, Gaetano Borriello and Randy H. Katz 3
X1X2•••
Xn
switchingnetwork
Z1Z2•••
Zn
Circuits with feedback
How to control feedback?what stops values from cycling around endlessly
VI - Sequential Logic © Copyright 2004, Gaetano Borriello and Randy H. Katz 4
"remember"
"load""data" "stored value"
"0"
"1"
"stored value"
Two inverters form a static memory cellwill hold value as long as it has power applied
How to get a new value into the memory cell?selectively break feedback pathload new value into cell
Simplest circuits with feedback
VI - Sequential Logic © Copyright 2004, Gaetano Borriello and Randy H. Katz 5
R
S
Q
Q'
RS
Q
R'S'
Q'
S'
R'
Memory with cross-coupled gates
Cross-coupled NOR gatessimilar to inverter pair, with capability to force output to 0 (reset=1) or 1 (set=1)
Cross-coupled NAND gatessimilar to inverter pair, with capability to force output to 0 (reset=0) or 1 (set=0)
VI - Sequential Logic © Copyright 2004, Gaetano Borriello and Randy H. Katz 6
Reset Hold Set SetReset Race
R
S
Q
\Q
100
Timing behavior
R
S
Q
Q'
VI - Sequential Logic © Copyright 2004, Gaetano Borriello and Randy H. Katz 7
S R Q0 0 hold0 1 01 0 11 1 unstable
State behavior or R-S latch
Truth table of R-S latch behavior
Q Q'0 1
Q Q'1 0
Q Q'0 0
Q Q'1 1
R
S
Q
Q'
VI - Sequential Logic © Copyright 2004, Gaetano Borriello and Randy H. Katz 8
Theoretical R-S latch behavior
State diagramstates: possible valuestransitions: changesbased on inputs
Q Q'0 1
Q Q'1 0
Q Q'0 0
Q Q'1 1
SR=00SR=11SR=00
SR=10
SR=01SR=00SR=10
SR=00SR=01
SR=11 SR=11
SR=10SR=01
SR=01 SR=10
SR=11
possible oscillationbetween states 00 and 11
R
S
Q
Q'
VI - Sequential Logic © Copyright 2004, Gaetano Borriello and Randy H. Katz 9
Observed R-S latch behavior
Very difficult to observe R-S latch in the 1-1 stateone of R or S usually changes first
Ambiguously returns to state 0-1 or 1-0a so-called "race condition"or non-deterministic transition
SR=00SR=00
Q Q'0 1
Q Q'1 0
Q Q'0 0
SR=10
SR=01SR=00SR=10
SR=00SR=01
SR=11 SR=11
SR=01 SR=10
SR=11
R
S
Q
Q'
VI - Sequential Logic © Copyright 2004, Gaetano Borriello and Randy H. Katz 10
Q(t+Δ)
RS
Q(t)
S R Q(t) Q(t+Δ)0 0 0 00 0 1 10 1 0 00 1 1 01 0 0 11 0 1 11 1 0 X1 1 1 X
hold
reset
set
not allowed characteristic equationQ(t+Δ) = S + R’ Q(t)
Break feedback path
R-S latch analysis
R
S
Q
Q'
0 0
1 0
X 1
X 1Q(t)
R
S
VI - Sequential Logic © Copyright 2004, Gaetano Borriello and Randy H. Katz 11
R’
S’ Q
Q'
characteristic equationQ(t+Δ) = S + R’ Q(t)
Activity: R-S latch using NAND gates
R’S’
Q(t)
0 0
1 0
X 1
X 1Q(t)
R
S
S R S’ R’ Q(t) Q(t+Δ)0 0 1 1 0 00 0 1 1 1 10 1 1 0 0 00 1 1 0 1 01 0 0 1 0 11 0 0 1 1 11 1 0 0 0 X1 1 0 0 1 X
hold
reset
set
not allowed
VI - Sequential Logic © Copyright 2004, Gaetano Borriello and Randy H. Katz 12
enable'
S'Qbar
QR' R
S
Gated R-S latch
Control when R and S inputs matter
otherwise, the slightest glitch on R or S while enable is low could cause change in value stored
Set Reset
S'
R'
enable'
Q
Qbar
100
Bubble match inputsclarifies logic intention
Note inputs are inverted- so asserted low!
R’
enable’
S’
Q
Qbar
VI - Sequential Logic © Copyright 2004, Gaetano Borriello and Randy H. Katz 13
period
duty cycle (in this case, 50%)
Clocks
Used to keep timewait long enough for inputs (R' and S') to settlethen allow to have effect on value stored
Clocks are regular periodic signalsperiod (time between ticks)duty-cycle (time clock is high between ticks - expressed as % of period)
VI - Sequential Logic © Copyright 2004, Gaetano Borriello and Randy H. Katz 14
clock’
R’ and S’
changing stable changing stablestable
Controlling an R-S latch with a clockcan't let R and S change while clock is active (allowing R and S to pass)only have half of clock period for signal changes to propagatesignals must be stable for the other half of clock period
Clocks (cont’d)
clock’
S’Q’
QR’ R
S
VI - Sequential Logic © Copyright 2004, Gaetano Borriello and Randy H. Katz 15
clock
R
S Q
Q’ R
S Q
Q’R
S
Cascading latches
Connect output of one latch to input of anotherHow to stop changes from racing through chain?
need to be able to control flow of data from one latch to the nextmove one latch per clock periodhave to worry about logic between latches (arrows) that is too fast
VI - Sequential Logic © Copyright 2004, Gaetano Borriello and Randy H. Katz 16
Master-slave structure
Break flow by alternating clocks (like an air-lock)use positive clock to latch inputs into one R-S latchuse negative clock to change outputs with another R-S latch
View pair as one basic unitmaster-slave flip-floptwice as much logicoutput changes a few gate delays after the falling edge of clockbut does not affect any cascaded flip-flops
master stage slave stage
P
P’
CLK
R
S Q
Q’ R
S Q
Q’R
S
VI - Sequential Logic © Copyright 2004, Gaetano Borriello and Randy H. Katz 17
Set1s
catch
SR
CLKPP’QQ’
Reset
MasterOutputs
SlaveOutputs
master stage slave stage
The 1s catching problem
In first R-S stage of master-slave FF0-1-0 glitch on R or S while clock is high is "caught" by master stageleads to constraints on logic to be hazard-free
P
P’
CLK
R
S Q
Q’ R
S Q
Q’R
S
VI - Sequential Logic © Copyright 2004, Gaetano Borriello and Randy H. Katz 18
10 gates
D flip-flop
Make S and R complements of each othereliminates 1s catching problemcan't just hold previous value(must have new value ready every clock period)value of D just before clock goes low is what is stored in flip-flopcan make R-S flip-flop by adding logic to make D = S + R’ Q
D Q
Q’
master stage slave stage
P
P’
CLK
R
S Q
Q’ R
S Q
Q’
VI - Sequential Logic © Copyright 2004, Gaetano Borriello and Randy H. Katz 19
Q
D
Clk=1
R
S
(1+R+D’)’=1’=0
D’
(1+D)’=1’=0
D’ D
Q’
negative edge-triggered D flip-flop (D-FF)
4-5 gate delays
must respect setup and hold time constraints to successfully
capture input
characteristic equationQ(t+1) = D
holds D’ whenclock goes low
holds D whenclock goes low
Edge-triggered flip-flops
More efficient solution: only 6 gatessensitive to inputs only near edge of clock signal (not while high)
DClk
Q
VI - Sequential Logic © Copyright 2004, Gaetano Borriello and Randy H. Katz 20
Q
D
Clk=0
R
S
D
D’
D’
D’ D
when clock goes high-to-lowdata is latched
when clock is lowdata is held
Step-by-step analysis
Edge-triggered flip-flops (cont’d)
Q
new D=D2
Clk=0
R
S
D
(D2+D)’=1’=0
D’
0 D
where D2 ≠ old D
VI - Sequential Logic © Copyright 2004, Gaetano Borriello and Randy H. Katz 21
positive edge-triggered FF
negative edge-triggered FF
DCLK
QposQpos’QnegQneg’
100
Edge-triggered flip-flops (cont’d)
Positive edge-triggeredinputs sampled on rising edge; outputs change after rising edge
Negative edge-triggered flip-flopsinputs sampled on falling edge; outputs change after falling edge
VI - Sequential Logic © Copyright 2004, Gaetano Borriello and Randy H. Katz 22
behavior is the same unless input changeswhile the clock is high
D Q
CLK
positiveedge-triggered
flip-flop
D QG
CLK
transparent(level-sensitive)
latch
D
CLK
Qedge
Qlatch
Comparison of latches and flip-flops
VI - Sequential Logic © Copyright 2004, Gaetano Borriello and Randy H. Katz 23
Type When inputs are sampled When output is valid
unclocked always propagation delay from input changelatch
level-sensitive clock high propagation delay from input changelatch (Tsu/Th around falling or clock edge (whichever is later)
edge of clock)
master-slave clock high propagation delay from falling edgeflip-flop (Tsu/Th around falling of clock
edge of clock)
negative clock hi-to-lo transition propagation delay from falling edgeedge-triggered (Tsu/Th around falling of clockflip-flop edge of clock)
Comparison of latches and flip-flops (cont’d)
VI - Sequential Logic © Copyright 2004, Gaetano Borriello and Randy H. Katz 24
Timing methodologies
Rules for interconnecting components and clocksguarantee proper operation of system when strictly followed
Approach depends on building blocks used for memory elements
we'll focus on systems with edge-triggered flip-flopsfound in programmable logic devices
many custom integrated circuits focus on level-sensitive latchesBasic rules for correct timing:
(1) correct inputs, with respect to time, are provided to the flip-flops(2) no flip-flop changes state more than once per clocking event
VI - Sequential Logic © Copyright 2004, Gaetano Borriello and Randy H. Katz 25
there is a timing "window" around the clocking event during which the input must remain stable and unchanged in order to be recognized
clock
datachangingstable
input
clock
Tsu Th
clock
dataD Q D Q
Timing methodologies (cont’d)
Definition of termsclock: periodic event, causes state of memory element to change
can be rising edge or falling edge or high level or low levelsetup time: minimum time before the clocking event by which the
input must be stable (Tsu)hold time: minimum time after the clocking event until which the
input must remain stable (Th)
VI - Sequential Logic © Copyright 2004, Gaetano Borriello and Randy H. Katz 26
all measurements are made from the clocking event (the rising edge of the clock)
Positive edge-triggered D flip-flopsetup and hold timesminimum clock widthpropagation delays (low to high, high to low, max and typical)
Typical timing specifications
D
Clk
Q
T su1.8ns
T h 0.5ns
T w 3.3 ns
T pd3.6 ns 1.1 ns
T su1.8ns
T h 0.5 ns
T pd3.6 ns 1.1 ns
T w 3.3 ns
VI - Sequential Logic © Copyright 2004, Gaetano Borriello and Randy H. Katz 27
IN
Q0
Q1
CLK
100
Shift registernew value goes into first stagewhile previous value of first stage goes into second stageconsider setup/hold/propagation delays (prop must be > hold)
Cascading edge-triggered flip-flops
CLK
INQ0 Q1
D Q D Q OUT
VI - Sequential Logic © Copyright 2004, Gaetano Borriello and Randy H. Katz 28
timing constraintsguarantee proper
operation ofcascaded components
assumes infinitely fast distribution of the clock
Cascading edge-triggered flip-flops (cont’d)
Why this workspropagation delay exceed hold time: Tp > Th
clock width constraint exceeds setup time: Tperiod > Tp + Tsu
this guarantees following stage will latch current value before it changes to new value
Tsu1.8ns
Tp1.1-3.6ns
Th0.5ns
In
Q0
Q1
CLK
Tsu1.8ns
Tp1.1-3.6ns
Th0.5ns
VI - Sequential Logic © Copyright 2004, Gaetano Borriello and Randy H. Katz 29
original state: IN = 0, Q0 = 1, Q1 = 1due to skew, next state becomes: Q0 = 0, Q1 = 0, and not Q0 = 0, Q1 = 1
CLK1 is a delayedversion of CLK0
InQ0Q1
CLK0CLK1
100
Clock skew
The problemcorrect behavior assumes next state of all storage elementsdetermined by all storage elements at the same timethis is difficult in high-performance systems because time for clockto arrive at flip-flop is comparable to delays through logiceffect of skew on cascaded flip-flops:
VI - Sequential Logic © Copyright 2004, Gaetano Borriello and Randy H. Katz 30
How to avoid clock skew
Design wire/track layout for identical delay of related signals
VI - Sequential Logic © Copyright 2004, Gaetano Borriello and Randy H. Katz 31
Summary of latches and flip-flops
Development of D-FFlevel-sensitive used in custom integrated circuits
can be made with 4 switchesedge-triggered used in programmable logic devicesgood choice for data storage register
Historically J-K FF was popular but now less commonsimilar to S-R but with 1-1 being used to toggle output (complement state)good in days of TTL/SSI (more complex excitation function: Q+ = J Q’ + K’ Q)not a good choice for PALs/PLAs as it requires 2 inputscan always be implemented using D-FF
Preset and clear inputs are highly desirable on flip-flopsused at start-up or to reset system to a known state
VI - Sequential Logic © Copyright 2004, Gaetano Borriello and Randy H. Katz 32
Asynchronous inputs (Katz2e Sec 6.2.3)
Clocked synchronous circuitsInputs, state, and outputs sampled or changed in relation to acommon reference signal (called the clock)e.g., master/slave JK, edge-triggered D flip-flopAny number of devices from the same family can be cascaded together and will perform correctly (at the appropriate clock frequency) since setup and hold times will be satisfied.
Asynchronous circuitsInputs, state, and outputs sampled or changed independently of acommon reference signal e.g., R-S latch, asynchronous Set/Reset inputs to D flip-flopNo setup/hold constraintsGlitches/hazards a major concern since they are more likely to cause state changes than in synchronous circuits.
VI - Sequential Logic © Copyright 2004, Gaetano Borriello and Randy H. Katz 33
Asynchronous inputs to synchronous circuitsinputs can change at any time, will not meet setup/hold timesdangerous, synchronous inputs are greatly preferred
Asychronous inputs cannot be avoided for any circuit that interfaces with the outside world!
Asynchronous inputs
D Q ?
VI - Sequential Logic © Copyright 2004, Gaetano Borriello and Randy H. Katz 34
D Q
D Q
Q0
Clock
Clock
Q1
AsyncInput
Clocked Synchronous
System
D Q
D Q
Q0
Clock
Clock
Q1
AsyncInput D Q
Synchronizer
Handling asynchronous inputsNever allow asynchronous inputs to fan-out to more than one flip-flop
If input changes near clock edge, each flip-flop may enter different stateSynchronize early and then treat as synchronous signal
VI - Sequential Logic © Copyright 2004, Gaetano Borriello and Randy H. Katz 35
In is asynchronous and fans out to D0 and D1
one FF catches the signal, one does not
inconsistent state may be reached!
In
Q0
Q1
CLK
Handling asynchronous inputs (cont’d)
What can go wrong?input changes too close to clock edge (violating setup time constraint)
VI - Sequential Logic © Copyright 2004, Gaetano Borriello and Randy H. Katz 36
Synchronizer failure: MetastabilityWhen an asynchronous input changes near a clock edge, the synchronizer may enter a metastable state - neither 0 or 1Hill analogy for metastability:
Valleys represent possible stable states -- 1 or 0Current state represented by position of the ballTo move from one stable state to another, the ball must be injected with sufficient energy to climb over the hillIf just the right amount of energy is injected, the ball may remain tottering at the top of the hill
logic 0 logic 1
stablestate
stablestate
metastablestate
? hungrydog
analogy
VI - Sequential Logic © Copyright 2004, Gaetano Borriello and Randy H. Katz 37
oscilloscope traces demonstratingsynchronizer failure and eventual
decay to steady state
Synchronizer may stay in metastable state indefinitely!In practise, thermal disturbances and timing asymmetries cause the output to return to 0 or 1 after some time.System failure can occur if the flip-flop has not left the metastable state by the ed of the clock period.
Synchronization failure: Metastability
VI - Sequential Logic © Copyright 2004, Gaetano Borriello and Randy H. Katz 38
D DQ Qasynchronous
inputsynchronized
input
synchronous system
Clk
Dealing with synchronization failure
Probability of failure can never be reduced to 0, but it can be reduced(1) slow down the system clock this gives the synchronizer more time to decay into a steady state; synchronizer failure becomes a big problem for very high speed systems(2) use fastest possible logic technology in the synchronizerthis makes for a very sharp "peak" upon which to balance(3) cascade two synchronizers this effectively synchronizes twice (both would have to fail)
VI - Sequential Logic © Copyright 2004, Gaetano Borriello and Randy H. Katz 39
Speed-Independent Circuits (Katz2e Sec 6.2.5)
As circuits get larger and faster, clock skew increases and different components effectively become asynchronous.When clock skew is sufficiently problematic, a global clock must be discarded in favour of delay-insensitive signaling:
Sender (server) and receiver (client) circuits communicate without the need for a global clockSynchronization is achieved through a handshaking protocol using additional signals: request and acknowledge
Client(independently
clockedsubsystem)
Server(independently
clocked subsystem)
Data flow
Acknowledge
Request
VI - Sequential Logic © Copyright 2004, Gaetano Borriello and Randy H. Katz 40
Four-Cycle HandshakingHandshaking steps:
Client asserts request lineServer places data on data lines and asserts acknowledge lineClient receives data and unasserts request lineServer removes data from data lines and unasserts acknowledge
Undetermined delay between each step does not lead to failureRequest is asynchronous with respect the to server and acknowledge is asynchronous with respect to the client, so the potential for synchronizer failure is unavoidable!
Req
Ack
Data
VI - Sequential Logic © Copyright 2004, Gaetano Borriello and Randy H. Katz 41
Two-Cycle Handshaking
Also called non-return-to-zero signallingHandshaking steps:
Client complements request lineServer drives data lines and complements acknowledge line
Client and server require extra logic to store current state of acknowledge and request lines
Req
Ack
Data
first request second request
data 1 data 2
VI - Sequential Logic © Copyright 2004, Gaetano Borriello and Randy H. Katz 42
Self-Timed CircuitsThe client/server circuits considered above were speed insensitive but still used internal independent clocks We can also use same handshaking approach to build logic circuits without any internal clocks!
Delay line slows acknowledge signal to ensure combinational logic has sufficient time to compute a stable outputDelay line should have same number of gate levels as longest delay through combinational logic
Self-timed circuits are increasingly important as clock distribution becomes a more difficult problem
CombinationalLogic
Delay
Input
Req
Output
Ack
VI - Sequential Logic © Copyright 2004, Gaetano Borriello and Randy H. Katz 43
Flip-flop features
Reset (set state to 0) – Rsynchronous: Dnew = R' • Dold (when next clock edge arrives)asynchronous: doesn't wait for clock, quick but dangerous
Preset or set (set state to 1) – S (or sometimes P)synchronous: Dnew = Dold + S (when next clock edge arrives)asynchronous: doesn't wait for clock, quick but dangerous
Both reset and presetDnew = R' • Dold + S (set-dominant)Dnew = R' • Dold + R'S (reset-dominant)
Selective input capability (input enable or load) –LD or EN
multiplexor at input: Dnew = LD' • Q + LD • Doldload may or may not override reset/set (usually R/S have priority)
Complementary outputs – Q and Q'
VI - Sequential Logic © Copyright 2004, Gaetano Borriello and Randy H. Katz 44
R S R S R SD Q D Q D Q D Q
OUT1 OUT2 OUT3 OUT4
CLK
IN1 IN2 IN3 IN4
R S
"0"
Registers
Collections of flip-flops with similar controls and logicstored values somehow related (for example, form binary value)share clock, reset, and set linessimilar logic at each stage
Examplesshift registerscounters
VI - Sequential Logic © Copyright 2004, Gaetano Borriello and Randy H. Katz 45
Register Files
A register file groups multiple registers in a single element:RE/WE indicate when a read or write operation is performedAddress lines A1-A5 indicate which register is to be read/writtenWord to be written is sent to data inputs D1-D8
Word to be read is asserted on outputs Q1-Q8
If no external clock, WE is used to generate internal clock
WERE
A1A2A3A4A5
D1D2…D8
Q1Q2…Q8
VI - Sequential Logic © Copyright 2004, Gaetano Borriello and Randy H. Katz 46
Random Access Memories (RAM)
A register file typically holds 4-32 data words, but many digital systems require thousands or millions of data wordsRandom access memory (RAM) generalizes the concept of a register file by using a transistor-efficient storage elementA large RAM can hold 128 million binary values (16 MBs)
CSWE
A9A8A7A6A5A4A3A2A1A0
I/O3I/O2I/O1I/O0
1024x4 SRAM Dj Dj
Writej
Static RAM (SRAM) storage element
Dj
Writej
capacitor
Dynamic RAM (DRAM) storage element
VI - Sequential Logic © Copyright 2004, Gaetano Borriello and Randy H. Katz 47
D Q D Q D Q D QIN
OUT1 OUT2 OUT3 OUT4
CLK
Shift register
Holds samples of inputstore last 4 input values in sequence4-bit shift register:
VI - Sequential Logic © Copyright 2004, Gaetano Borriello and Randy H. Katz 48
parallel inputs
parallel outputs
serial transmission
Shift register application
Parallel-to-serial conversion for serial transmission
VI - Sequential Logic © Copyright 2004, Gaetano Borriello and Randy H. Katz 49
D Q D Q D Q D QIN
OUT1 OUT2 OUT3 OUT4
CLK
OUT
Pattern recognizer
Combinational function of input samplesin this case, recognizing the pattern 1001 on the single input signal
VI - Sequential Logic © Copyright 2004, Gaetano Borriello and Randy H. Katz 50
clear sets the register contentsand output to 0
s1 and s0 determine the shift function
s0 s1 function0 0 hold state0 1 shift right1 0 shift left1 1 load new input
left_inleft_out
right_out
clearright_in
output
input
s0s1
clock
Universal shift register
Holds 4 valuesserial or parallel inputsserial or parallel outputspermits shift left or rightshift in new values from left or right
VI - Sequential Logic © Copyright 2004, Gaetano Borriello and Randy H. Katz 51
Nth cell
DQ
CLK
Q[N-1](left)
Q[N+1](right)
Input[N]
to N-1th cell
to N+1th cell
clear s0 s1 new value1 – – 00 0 0 output0 0 1 output value of FF to left (shift right)0 1 0 output value of FF to right (shift left)0 1 1 input
Consider one of the four flip-flopsnew value at next clock cycle:
Design of universal shift register
s0 and s1control mux0 1 2 3
CLEAR
VI - Sequential Logic © Copyright 2004, Gaetano Borriello and Randy H. Katz 52
D Q D Q D Q D QIN
OUT1 OUT2 OUT3 OUT4
CLK
Counters
Sequences through a fixed set of patternsin this case, 1000, 0100, 0010, 0001 – called a ‘ring counter’Is this self-starting?Only counts in above pattern if one of the patterns is its initial state (by loading or set/reset)
VI - Sequential Logic © Copyright 2004, Gaetano Borriello and Randy H. Katz 53
Activity
How does this counter work?
D Q D Q D Q D QIN
OUT1 OUT2 OUT3 OUT4
CLK
Counts through the sequence: 1000, 1100, 1110, 1111, 0111, 0011, 0001, 0000
Known as Mobius (or Johnson) counter
Above circuit not self-starting!
VI - Sequential Logic © Copyright 2004, Gaetano Borriello and Randy H. Katz 54
D Q D Q D Q D Q
OUT1 OUT2 OUT3 OUT4
CLK
"1"
Binary counter
Logic between registers (not just multiplexer)XOR decides when bit should be toggledalways for low-order bit,only when first bit is true for second bit,and so on
VI - Sequential Logic © Copyright 2004, Gaetano Borriello and Randy H. Katz 55
Counter Design Example
Step 1: Draw state transition diagramStep 2: Derive state transition tableStep 3: Express each next state bit as function of present stateExample: 3-bit binary counter
111 000
001
010
011100
101
110
C B A C+ B+ A+
0 0 0 0 0 10 0 1 0 1 00 1 0 0 1 10 1 1 1 0 01 0 0 1 0 11 0 1 1 1 01 1 0 1 1 11 1 1 0 0 0
State transition diagram State transition table
A+ = A’B+ = B A’ + B’ AC+ = C A’ + B’ C + C’ B A
Next state logic
VI - Sequential Logic © Copyright 2004, Gaetano Borriello and Randy H. Katz 56
EN
DCBALOADCLKCLR
RCOQDQCQBQA
(1) Low order 4-bits = 1111
(2) RCO goes high
(3) High order 4-bits are incremented
Four-bit binary synchronous up-counter
Standard component with many applicationspositive edge-triggered FFs w/ synchronous load and clear inputsparallel load data from D, C, B, Aenable inputs: must be asserted to enable countingRCO: ripple-carry out used for cascading counters
high when counter is in its highest state 1111implemented using an AND gate
VI - Sequential Logic © Copyright 2004, Gaetano Borriello and Randy H. Katz 57
EN
DCBALOADCLKCLR
RCOQDQCQBQA
"1"
"0""0""0""0"
"0"
EN
DCBALOADCLKCLR
RCOQDQCQBQA
"1"
"0""1""1""0"
Offset counters
Starting offset counters – use of synchronous loade.g., 0110, 0111, 1000, 1001,1010, 1011, 1100, 1101, 1111, 0110, . . .
Ending offset counter – comparator for ending valuee.g., 0000, 0001, 0010, ..., 1100, 1101, 0000
Combinations of the above (start and stop value)
VI - Sequential Logic © Copyright 2004, Gaetano Borriello and Randy H. Katz 58
Hardware Description Languages (Verilog)and Sequential Logic
Behavioral Verilog module for edge-triggered D flip-flip:
module dff (clk, d, q);input clk, d;output q;reg q;
always @(posedge clk)q = d;
endmodule
Indicates that q should be considered for a register –it is necessary for variables updated in an always block to be declared “reg”, even if they are not allocated a register!
Indicates that statement should only be executed on positive edge of signal in sensitivity list.For negative edge-triggered flip-flop use negedge
VI - Sequential Logic © Copyright 2004, Gaetano Borriello and Randy H. Katz 59
Edge-triggered D flip-flop with Asynchronous Set and Reset (replace text p296 version)
module dff_async_rs (clk, r, s, d, q);input clk, r, s, d;output q;reg q;
always @(posedge clkor posedge r or posedge s)
beginif (s) q = 1'b1;else if (r) q = 1'b0;else q =d;
endendmodule
Indicates a 1-bit binary number with the value 0.
Format specifier:width ’ radix value
where radix = b (binary), d (decimal)h (hex), o (octal)
Four valid binary values:0, 1, x (unknown), z (high impedance)
VI - Sequential Logic © Copyright 2004, Gaetano Borriello and Randy H. Katz 60
Shift Register Implementation
Shift register: D Q D Q D Q D QIN
OUT1 OUT2 OUT3 OUT4
CLK
module shift4bit (clk, in, out1, out2, out3, out4);input clk, in;output out1, out2, out3, out4;reg out1, out2, out3, out4;
always @(posedge clk) beginout4 = out3;out3 = out2;out2 = out1;out1 = in;
end
endmodule
Order within block is important! Thefollowing won’t work:
out1 = in;out2 = out1;out3 = out2;out4 = out3;
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Delayed Assignment
Delayed (or non-blocking) assignments are indicated by <=instead of =, and take place simultaneous at end of block rather than in the order written.The following shift register implementation is correct:
Shorthand notation for multiple assignments:
always @(posedge clk) beginout1 <= in;out2 <= out1;out3 <= out2;out4 <= out3;
end
always @(posedge clk) begin{out1, out2, out3, out4} <= {in, out1, out2, out3};
end
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Example: 3-bit Binary Counter
module counter (clk, q0, q1, q2);input clk;output q0, q1, q2;reg [2:0] count;
initial count = 0;
always @(posedge clk)count = count + 1;
assign q2 = cnt[2];assign q1 = cnt[1];assign q0 = cnt[0];
endmodule
3-bit state
initial block executed only once at start of simulation. Note: the initial block can appear anywhere in the module; it is still executed once at start
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Example: Register Filemodule register_file_32_by_8 (we, re, abus, dbus, obus);parameter mem_size = 32;parameter dbus_width = 8;parameter abus_width = 6;input we, re;input [abus_width-1:0] abus; input [dbus_width-1:0] dbus; output [dbus_width-1:0] obus; reg [dbus_width-1:0] out;reg [dbus_width-1:0] regfile [mem_size-1:0];
always @(posedge we) regfile[abus] = dbus;always @(posedge re) out = regfile[abus];assign obus = (re) ? out : 8’bzzzzzzzz;
endmodule
VI - Sequential Logic © Copyright 2004, Gaetano Borriello and Randy H. Katz 64
HDL for Sequential Logic Summary
reg keyword may create a memory variable to store the state of a sequential circuit – needed when always blocks used even for combinational circuits.Event control keywords posedge and negedge allow us to implement edge-triggered behavior in latches.Delayed (non-blocking) assignment removes dependency on order of statements in sequential block (between begin and end keywords)
Affected registers are updated simultaneously at end of block
VI - Sequential Logic © Copyright 2004, Gaetano Borriello and Randy H. Katz 65
Sequential logic summary
Fundamental building block of circuits with statelatch and flip-flopR-S latch, R-S master/slave, D master/slave, edge-triggered D flip-flop
Timing methodologiesuse of clockscascaded FFs work because propagation delays exceed hold timesbeware of clock skew
Asynchronous inputs and their dangerssynchronizer failure: what it is and how to minimize its impact
Basic registersshift registerscounters
Hardware description languages and sequential logic