Chip, Package and System (CPS) Design€¦ · 1 © 2011 ANSYS, Inc. June 18, 2012 . Chip, Package...

© 2011 ANSYS, Inc. June 18, 2012 1

Chip, Package and System (CPS) Design

Steve G. Pytel, PhD. SI Product Manager

Confidence by Design Chicago, IL June 14, 2012

© 2011 ANSYS, Inc. June 18, 2012 2

• On August 1st, 2011, ANSYS announced that it successfully closed acquisition of Apache Design Solutions, Inc.

– Apache is the leading simulation software provider for advanced, low power solutions in the electronics industry.

• The addition of Apache’s technology is complementary and expands the breadth, depth, functionality, usability and interoperability of ANSYS’ simulation capabilities.

• Apache will operate is a wholly-owned subsidiary of ANSYS

ANSYS and Apache: Acquisition

© 2011 ANSYS, Inc. 3

Focused •Simulation is all we do. •Leading product technologies in all physics areas •Largest development team focused on simulation

Capable More than 2,000 employees 60 locations, 40 countries

Trusted 96 of top 100 FORTUNE 500 industrials •ISO 9001 and NQA-1 certified

Proven Recognized as one of the world’s most innovative and fastest-growing companies*

Independent Long-term financial stability CAD agnostic

*BusinessWeek, FORTUNE

ANSYS Strengths


Apache Strengths

Largest global R&D and support team focused on power and noise

Irvine, CA San Jose, CA

Seattle

San Diego, CA Texas

North Carolina

New Hampshire Colorado

United Kingdom

Sales, Support Offices

R&D Centers

Israel

France

Germany

Chengdu, China

Shanghai, China

Noida, India

Beijing, China

Bangalore, India

Japan

South Korea

Taiwan

Singapore

• Established 2001

• HQ in San Jose, CA

• 22 Offices

• 11 Countries

• 7 R&D Centers

At a Glance Global Footprint


Old Paradigms Single Physics Circuit and System Simulation Single User and Single Component Simulation Few Design Points Studied

New Paradigms Single-Platform Multiphysics Simulation Including SI/PI, EMI/EMC, Electronics Cooling, RF/MW and Structural Mechanics Circuit and System Simulation Integrated with High-Fidelity Multiphysics Analysis Collaborative Multi-user and Multi-scale Simulation (component to system) Extensive Multiphysics and Multiscale Design Exploration with High-Performance Computing

ANSYS Vision for Electronics Industry


ANSYS & Apache Technology

Power Integrity Signal Integrity

Thermal/Stress Electromagnetic Interference


Apache Strengths

System Cooling

Interference

Battery life

Integration

40/28/22nm EM and ESD

Power Budgeting Power Delivery

Advanced Reliability Chip – Package - System


Highly Complementary

• ANSYS –Leader in package/board EM, system, and

mechanical/thermal for electronics

• Apache –Leader for mobile low power, reliability

and chip-package-system simulation

Expand Breadth and Depth of Simulation

• Design Flow for Chip/Package/System

• Allows for an end-to-end chip/package/system

solution platform

ANSYS and Apache: Synergy

End-to-End Chip-Package-System Power, Thermal, EMI, Timing Platform

CHIP RedHawk

Totem, PowerArtist

PACKAGE HFSS, SIwave

Q3D, TPA Sentinel – NPE, PSI, TI

Icepak, Mechanical

BOARD SIwave, HFSS Q3D

DesignerSI Icepak

CONNECTOR HFSS, Q3D


Infotainment

• Voice, Video, Internet, apps, etc., …

Impacts

• System miniaturization

• Power and cooling

• EMI

• IP and SoC integration

ANSYS Software used

• HFSS / DesignerSI / Q3D Extractor

• SIwave / Icepak

• RedHawk

• Totem

ANSYS and Apache: Examples

Smartphone EMI Simulation in HFSS

SIwave Calculates PCB Power & Currents

Board Temperature and Forced Air Cooling using IcePak

Power Temp

CPM from RedHawk

© 2011 ANSYS, Inc. 10

Mobile Data

• Mobile data to grow over 2500% by 2015 from 2010 levels*

Impacts

• Antennas and EMI

• RF-IC modules

• I/O DDR jitter

ANSYS Software used

• DesignerSI / SIwave / HFSS

• Sentinel-SSO / PSI


Cellular Base Station Antenna Using HFSS

RF Module in ANSYS Designer using HFSS Solver on Demand (Model Courtesy Skyworks)

IO/DDR Power and Signal integrity aware timing/jitter using Sentinel-SSO

* Jeffries Mobility 2020

© 2011 ANSYS, Inc. 11

Power Consumption / Power Budget

• Gap is Increasing

• 6X gap in 2015 to be 10X gap in 2010

Impacts

• Battery life

• Handset / Tablet cooling

• Reliability

ANSYS Software Used

• PowerArtist

• Sentinel-TI

• ANSYS CFD / HFSS


Modern 3DIC Stacked Die Simulation in Sentinel-TI

RTL Design for Power Flow using

PowerArtist

Mu

lti-

ph

ysic

s b

att

ery

mo

del

ing

* ITRS

© 2011 ANSYS, Inc. 12

More and Faster Data

• 2 GHz and beyond designs

• Lowered voltage supply to reduce power consumption

Impacts

• Noise margin and power integrity

• Power induced noise

ANSYS Software Used

• HFSS / Q3D / SIwave / Sentinel

• RedHawk

• Totem-CSE


Multi-core high speed ARM based mobile processor power analysis using RedHawk (from

blogs.ARM.com)

Power Noise Coupling Analysis Using Totem-CSE

HFSS and Q3D Electrical Simulators evaluate how

signals enter and exit

© 2011 ANSYS, Inc. 13

ANSYS and Apache: The Future

The future will require greater co-simulation capabilities and innovations

• Automotive EMI • 3DIC With Thermal • High-speed I/O

© 2011 ANSYS, Inc. 14

ANSYS and Apache: The Future

Model Based Electronic System Co-Analysis

SoC Level Simulation

System Level Analysis

CPM

Package, PCB Model

Chip Power Model

• Captures chip current & parasitics

• Distributed and cross-coupled • SPICE ready

Package, PCB Extraction

• S-parameter or RLCG

• 3D full-wave / Hybrid / 3D Quasi-static • Full package / PCB extraction • IC on PKG on PKG on BRD Extraction

Co-Simulation

• Direct CPM import

• AC, DC, transient, EMI analysis • Integrated query and editing

© 2011 ANSYS, Inc. 15

Chip-Package-System co-simulation environment

© 2011 ANSYS, Inc. 16

CPS Solution

Ansoft

Package/PCB

RTL

PowerArtist

SoC

RedHawk

Analog/IP

Totem

RTL Power Model (RPM)

Compact Macro Model (CMM)

Chip Power Model (CPM)

Chip Package Protocol

(CPP)

RPM

CMM CPP

CPM

© 2011 ANSYS, Inc. 18

EM Extraction Product portfolio

© 2011 ANSYS, Inc. 19

Product portfolio (Quasi-Static)

Large-scale and application specific

Attentive and flexibility

Speed Accuracy

Quasi-Static RLCG Analysis

Q3D •Golden Standard RLCG •Adaptive Mesh •3D MCAD I/F

Connector model extraction QFP(Lead flame) extraction PBGA extraction

Sentinel-NPE •ECAD I/F - For PKG •Large scale •High speed extraction •CPS flow

Large scale power model extraction Power/Signal extraction for SSO

TPA •Used Q3D Solver Engine - Non Adaptive Mesh •ECAD I/F - For PKG specific

BGA signal extraction Middle Scale Model extraction

© 2011 ANSYS, Inc. 20

Product portfolio (Full-wave)

Large-scale and application specific

Attentive and flexibility

Speed Accuracy

Full-wave Analysis

Sentinel-PSI •High Speed FEM of Prism element •PI/SI analysis for Package •Complement 3D effect for SIwave •The power supply for SSO and Signal of package and board with single substance EMI

SIwave •High speed Hybrid solver for PKG/BRDの •Large scale analysis

• Large-scale board power supply model extraction

• Package-Board EMI analysis

HFSS •Golden Standard Full wave analysis •Flexible full 3D •Strong extraction for critical net • Layout front end for HFS System level sign off Critical PCB signal extraction

© 2011 ANSYS, Inc. 22

Redhawk I/F from Sentinel-NPE/Q3D/TPA

© 2011 ANSYS, Inc. 23

Interface for chip analyses

ploc File

gsr file

Chip pad location

power-supply-voltage domain

Redhawk

Package

Compiler

Check Package structure

Termination process of solder ball

Connect Chip-Package pins

Check passivity

Export corrected package model

Export corrected ploc

CPP header

Package

Model

Redhawk

Totem

Sentinel-NPE

Q3D

Dynamic

voltage drop

Timing

impact

ESD

Dynamic low

power

Signal

Power

EM

Create CPM

© 2011 ANSYS, Inc. 24

Package compiler - Pin mapping

VDDC

VDDQ

VSSQ

VSSC

* Start Power Ground Ports

* D1-105:( 0.586232E+01 -0.460654E+01):GND-MP_1_1=GND:GND_Group_1:DIE








* D1-146:( 0.586232E+01 -0.355600E-02):GND-MP_1_1=GND:GND_Group_1:DIE

* D1-148:( 0.586232E+01 0.220980E+00):GND-MP_1_1=GND:GND_Group_1:DIE

* D1-15:(-0.382067E+01 -0.586334E+01):GND-MP_1_1=GND:GND_Group_1:DIE

* P1-B3:(-0.133350E+02 0.146050E+02):VCC-MP_2_2=VCC:VCC_Group_2:PCB

* P1-C2:(-0.146050E+02 0.133350E+02):VCC-MP_2_2=VCC:VCC_Group_2:PCB

* P1-C24:( 0.133350E+02 0.133350E+02):VCC-MP_2_2=VCC:VCC_Group_2:PCB

* P1-C25:( 0.146050E+02 0.133350E+02):VCC-MP_2_2=VCC:VCC_Group_2:PCB

* P1-C3:(-0.133350E+02 0.133350E+02):VCC-MP_2_2=VCC:VCC_Group_2:PCB

* End Power Ground Ports

DVDD1 4905 878.85 METAL4 POWER

DVSS1 4880 938.85 METAL4 GROUND





















Redhawk Pin location Package Model(CPP Header)

315° Rotate

X axis center flip

Matched Pin location!

© 2011 ANSYS, Inc. 25

Package compiler－Create Package model structure

Chip side Multi ports

Connect Redhawk DB

by Ploc

Solder Ball side Single port

V

Terminal process

by importing Gsr

© 2011 ANSYS, Inc. 26

Sentinel-PSI, SIwave I/F from Redhawk

© 2011 ANSYS, Inc. 27

The interface for system analysis

CPM

(Chip Power Model)

Impedance in Chip

Pad current

Model supply

Sentinel-PSI

SIwave Redhawk

Totem

Dynamic

Voltage drop

Timing

Impact

ESD

Dynamic low

power

Signal

Power

EM

Create CPM

© 2011 ANSYS, Inc. 28

CPM overview

Static (Iavg, R) Frequency Domain(RLC) Time Domein (I(t), RLC)

Analysis Mode Model

reduction

The real chip in the system analysis is available.

© 2011 ANSYS, Inc. 29

System AC Simulation

Package/PCB DC Analysis

Capacitor in package

Capacitor in board

BGA Package Bulk capacitor

Power Line

GND Line

CPM

PDN analysis in whole system

Capacitor placement Time domain system analysis

© 2011 ANSYS, Inc. 31

CPS Example

‐EMI Co-Simulation‐

Apache Design : CPM Integration RH+CPM+SIwave+DesignerSI

© 2011 ANSYS, Inc. 32

SIwave CPS Design Flow

PoPoBoPiP

ddr3_report1.pdf

© 2011 ANSYS, Inc. 33

• PDF and HTML report files

Virtual Compliance Reporting

© 2011 ANSYS, Inc. 35

DesignerSI

Nexxim &

HSPICE

CPS Down Stream System Design Flow: SI, PI & EMI

FWS, SYZ, Transient, Near & Far Field

Solutions

RedHawk Totem

CPM

Package Databases

PCB Database

SIwave HFSS for ECAD

Sentinel-PSI

FWS, SYZ for SI, PI, & EMI

Frequency-Domain Sources

for EMI

HFSS for MCAD

© 2011 ANSYS, Inc. 37

Chip-Pkg-System EMI Co-Simulation

• Chip-Pkg-System Co-Simulation

– The real operated noise source of IC is applied.

EMI analysis model

The waveform of supplied power and ground.

Transient analysis

Apache CPM

PCB+Pkg SIwave

ANSYS DesignerSI™ with Nexxim®

© 2011 ANSYS, Inc. 38

Chip-Pkg-System EMI Co-Simulation

• Chip-Pkg-System Co-Simulation

– Extraction Model （Package + Board）

With Decoupling 3m Far Field plot（dBμV/m）

Far Field - 1.27v with Decaps

-20.00

-10.00

0.00

10.00

20.00

30.00

40.00

50.00

60.00

0.00 0.50 1.00 1.50 2.00GHz

dB

uV

/m__

Without Decoupling

✍Virtual EMI Test environment

Near Field Plot (1.5GHz）

© 2011 ANSYS, Inc. 39

J3 V

olt

ag

e [

dB

V]

Frequency [Hz]

J3 V

olt

ag

e [

dB

V]

Frequency [Hz]

Conclusion - CPS Simulation Example Automotive Electronic Verification for EMI

• ST Microelectronics

– Already demonstrated solution using tools from ANSYS, Apache, and other vendors

• New Opportunity

– Single vendor for integrated multi-physics platform

– Data transfer and model exchange

– Component, sub-system and system level validation

– Monitor and validate entire design chain

– From virtual prototyping to design sign-off

– From specification planning to system acceptance

System EMI

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