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Click to edit Master title style STT-RAM Circuit Design Column Circuitry Simulation (IBM 45nm SOI)...

Date post: 19-Jan-2018
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Body contacted (BC) v.s. floating body (FB) device  Choosing device for access transistor –Best available BC device has 2x worse drive strength as compared to FB device, it also has body contact making it really big. –In the interest of area, it is better to use FB device, but FB device has variation on R MOS depending upon V body (can range from V in our design), the following slide will analyze how this will affect the effective TMR. 3
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STT-RAM Circuit Design Column Circuitry Simulation (IBM 45nm SOI) Fengbo Ren
Transcript
Page 1: Click to edit Master title style STT-RAM Circuit Design Column Circuitry Simulation (IBM 45nm SOI) Fengbo Ren.

Click to edit Master title style

STT-RAM Circuit Design

Column Circuitry Simulation(IBM 45nm SOI)

Fengbo Ren

Page 2: Click to edit Master title style STT-RAM Circuit Design Column Circuitry Simulation (IBM 45nm SOI) Fengbo Ren.

Summary Use floating body device as access transistor won’t degrade effective

TMR as long as we perform pre-charge in reading operation.

The bipolar current (due to the floating body) will appear at the beginning of writing operation. It should be not enough to be destructive (12uA/um, last for 80 ps).

Min. cell size can be achieved is 17F2 (F=0.095 um). For min. cell size, I_W(P->AP)=645 uA, I_W(AP->P)=415 uA. More write current than 65-nm for the same cell size.

Use NMOS-only-MUX results in 15-20% write current degradation.

Still working on how to do reliable short pulse reading.

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Page 3: Click to edit Master title style STT-RAM Circuit Design Column Circuitry Simulation (IBM 45nm SOI) Fengbo Ren.

Body contacted (BC) v.s. floating body (FB) device

Choosing device for access transistor– Best available BC device has 2x worse drive strength as

compared to FB device, it also has body contact making it really big.

– In the interest of area, it is better to use FB device, but FB device has variation on RMOS depending upon Vbody (can range from 0-0.65V in our design), the following slide will analyze how this will affect the effective TMR.

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FET Name Idsat (uA/um) Area (for same I)Regular-Vt floating body NFET 1229 1Analog body contacted NFET 687 5

Page 4: Click to edit Master title style STT-RAM Circuit Design Column Circuitry Simulation (IBM 45nm SOI) Fengbo Ren.

Effective TMR Some definition

– TMR = (RAP-RP)/RP

– Effective RP (RP_Eff) = RP+RMOS1

– Effective RAP (RAP_Eff) = RAP+RMOS2

– Effective TMR = (RAP_Eff-RP_Eff)/RP_Eff

– _BC: body connected case– _FB: floating body case

Best case in reading– Vbody >> 0 and are same when reading RP and RAP

– RP_Eff_FB < RP_Eff_BC, RAP_Eff_FB < RAP_Eff_BC,

Worst case in reading– Vbody = 0 when reading RP, Vbody >> 0 when reading RAP

– RP_Eff_FB = RP_Eff_BC, RAP_Eff_FB < RAP_Eff_BC

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0500

10001500

2000

2030

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500

20

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100

120

Rp (Ohm)

Effective TMR when TMR=125%

Cell Size (F2)

Effec

tive

TMR

(%)

20

30

40

50

60

70

80

90

100

Page 5: Click to edit Master title style STT-RAM Circuit Design Column Circuitry Simulation (IBM 45nm SOI) Fengbo Ren.

Effective TMR when body is floating Best case improve effective TMR a little bit Worst case degrade effective TMR by 5-6% For our reading circuit, BL and SL are always pre-charged to the same

voltage level. So, Vbody should always be the same (somewhere between VDD and VSS) regardless of MTJ resistance. Therefore, by performing pre-charge, we are always in the best case, which means using FB device won’t degrade TMR in our design.

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Page 6: Click to edit Master title style STT-RAM Circuit Design Column Circuitry Simulation (IBM 45nm SOI) Fengbo Ren.

Bipolar Current (FB device) When g = 0, d = 1, s = 1-> 0, since body is floating

(Vbody>>0), we have bipolar current (Ibipolar). In our design, this current will be seen at

the beginning of writing operation.

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Bipolar current at the beginning of writing operation

Ibipolar has a peak of 12 uA/um and last for 80 ps, which should be not enough to accidentally flip MTJs. In our design we have 128 WLs, the peak of Ibipolar_total will be around 1.5 mA, a high but short current pulse.

Page 7: Click to edit Master title style STT-RAM Circuit Design Column Circuitry Simulation (IBM 45nm SOI) Fengbo Ren.

Min. Cell Size Transistor size:

– W = 434 nm– L = 40 nm

Cell size:– 0.154 um2

– 17 F2 ● Feature size: 0.095 um

From 65 -> 45nm– Metal pitch

● 0.2 -> 0.19 um (M4)● 0.2 -> 0.14 um (M1)

– Transistor pitch (D/S shared)

● 0.5 -> 0.38

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0.405 um

Note: This is the min. cell size can be achieved without violating design rule.

Page 8: Click to edit Master title style STT-RAM Circuit Design Column Circuitry Simulation (IBM 45nm SOI) Fengbo Ren.

Boosted VDDW

VBIAS

VBIAS

BL

SL

S

SS’

S’

Boosted dual VWL

“1” “0”

Cell Size v.s. Write Current Rp = 700 Ohm, TMR = 125% Boost up VDDW, VWL

– dual VWL (VWL_P , VWL_AP)

Recall 65-nm

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  Cell Size (F2, F=0.095 um (C1))  17 20 25 30 35 40Transistor

W (um) 0.43 0.57 0.81 1.05 1.29 1.52 IWP (uA) 645 789 982 1100 1220 1270IWAP (uA) 415 452 492 513 535 547

Cell Size (F2)27.75 30 35 40 45 50

Transistor W (um) 0.75 0.84 1.04 1.24 1.44 1.64

IWP (uA) 723 779 884 972 1040 1090

IWAP (uA) 410 422 443 458 471 480

Page 9: Click to edit Master title style STT-RAM Circuit Design Column Circuitry Simulation (IBM 45nm SOI) Fengbo Ren.

Using NMOS only in MUX Mux size W

– NMOS: W– PMOS: 2W

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Using NMOS only in MUX will result in 15-20% write current degradation for P->AP, 10-15% degradation for AP->P.

The main reason causes the degradation is that the VGS of the NMOS that close to VDD will be very low during the write operation (Shown in green in the bottom Fig. ), in which case we need a PMOS. So, simply increasing the size of NMOS won’t help.

Page 10: Click to edit Master title style STT-RAM Circuit Design Column Circuitry Simulation (IBM 45nm SOI) Fengbo Ren.

Read Normal X-INV based reading

– Monte Carlo, TMR=125%

Still working on how to do reliable short pulse reading.– No positive result yet.

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Rp (Ω) 500 750 1000Read time

(ps)60~160 80~160 120~270


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