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CLOCKLESS CHIPS
BY- SAURABH SINGHEC III (B)
1016431096PSIT,KANPUR
PRESENTATION FLOW:
Introduction. Concept of clock Problems with synchronous circuits. Clockless / Asynchronous circuits. How clockless chips work? Simplicity in design. Advantages Recent Commercial Interest Challenges. Conclusion References
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INTRODUCTION.
Struggle for the improvement in the
microprocessor’s performance/functioning.
Pipelining
(Simultaneous) Multithreading
Clockless / Asynchronous logic
Synchronous
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CONCEPT OF CLOCK:
Tiny crystal oscillator.
Sets basic rhythm used throughout the machine. The system clock for an integrated circuit is a voltage
signal that pulses at a regular frequency.1
0 The clock tells each stage of a circuit that the inputs of
that stage are valid and can be processed.
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PROBLEMS WITH SYNCHRONOUS APPROACH
o Clock distribution: requires significant designer effort.
o Wastage of energy.
o Clock burns large fraction of chip power (~40-70%).
o Fixed clock rate: poor match foro designing reusable componentso interfacing with mixed-timing environments
o Traverse the chip’s longest wires in one clock cycle.
o Order of arrival of the signals is unimportant.
o Distributing the clock globally.
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CLOCKLESS CHIPS (ASYNCHRONOUS LOGIC CIRCUITS)
Clockless chips/Asynchronous/self-timed circuits.
Functions away from the clock.
Different parts work at different speeds.
Hand-off the result immediately.
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HOW DO THEY WORK?
No centralized clock required.
Data moves only when required, not always.
Minimizes power consumption.
Less EMI less noise more applications.
Stream data applications. Uses handshake signals for the data exchange.
HOW HANDSHAKING WORKS
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Processing Data Idle
Stage 1 Stage 2
HOW HANDSHAKING WORKS
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TransmittingData
Idle
Request
Data
Stage 1 Stage 2
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HOW HANDSHAKING WORKS
TransmittingData
DataReceived
Request
Acknowledge
Data
Stage 1 Stage 2
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HOW HANDSHAKING WORKS
IdleProcessing
Data
Stage 1 Stage 2
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DIFFERENT STYLES: Simplest implementation of asynchronous
design.
Assumption: we know the largest amount of time for each component to perform its task.
Very similar to synchronous design.
Function delay is introduced here.
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ADVANTAGES Works at increased speed (2.8 times). Low power consumption.
• Twice life-time. Less heat generated.
• Good to mobile devices. Less EMI less noise more applications.
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RECENT COMMERCIAL INTEREST
Several commercial asynchronous chips:Philips: asynchronous 80c51 microcontrollersUniv. of Manchester: async ARM996HS processor
[2006]Motorola: async divider in PowerPC chip [2000]HAL: async floating-point divider
Recent experimental chips: IBM, Sun and Intel: IBM/Columbia/UNC: asynchronous digital FIR filter
Several recent startups:Theseus Logic, Fulcrum, Self-Timed Solutions
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CHALLENGES Interfacing between synchronous and
asynchronousMany devices available now are synchronous in
nature.Special circuits are needed to align them.
Lack of expertise. Lack of tools. Engineers are not trained in these fields. Academically, no courses available.
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CONCLUSION: Clocks are getting faster , while chips are getting
bigger both of which make clock distribution harder
There are also various other problems associated with it. So we could only get out of it , if more focus , especially at the university level is given to the asynchronous design.
It is certainly a challenge , but as software community is moving towards concurrency, hardware community must move to incorporate asynchronous logic.
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REFERENCES Google Wikipedia Digital Design—MORIS MANO Digital Circuits & Design—SALIVAHANAN www.technologyreview.com www.seminarprojects.com www.slideshares.net www.handshakesolutions.com
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Any queries
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THANKS