CMOS - 1
CMOS Detector Technology
Alan HoffmanRaytheon Vision Systems
Scientific Detector Workshop, Sicily 2005
Markus LooseRockwell Scientific
Vyshnavi SuntharalingamMIT Lincoln Laboratory
CMOS - 2
Outline
• General Concept & Architecture• Common Features of CMOS Sensors • Stitching Technology Enables Large Arrays• Monolithic CMOS
• Hybrid CMOS– History of Hybrid CMOS– ROIC Input Cells – Detector Materials & Properties
• Low Noise Through Multiple Sampling
• CMOS Processing and General Limitations• Emerging Technologies
– Vertical Integration– Geiger-Mode Avalanche Photodiode Arrays
• Comparison: CMOS vs. CCD for Astronomy
Markus Loose
Alan Hoffman
Vyshi Suntharalingam
CMOS - 3
HgCdTe 4K x 4K mosaic, 18 µm pixels
Collection of High-Performance CMOS Detectors
InSb 2K x 2K, 25 µm pixels
HgCdTe 2K x 2K, 20 µm pixels
HgCdTe 2K x 2K, 18 µm pixels
3D stacked CMOS wafer sandbox
Monolithic CMOS 4K x 4K, 5 µm pixels
CMOS - 4
General CMOS Detector Concept
CCD Approach CMOS Approach
PixelCharge generation &
charge integration Charge generation,
charge integration & charge-to-voltage conversion
+
PhotodiodePhotodiode Amplifier
Array ReadoutCharge transfer
from pixel to pixel
Multiplexing of pixel voltages: Successively
connect amplifiers to common bus
Sensor Output Output amplifier performs
charge-to-voltage conversion
Various options possible:- no further circuitry (analog out)- add. amplifiers (analog output)- A/D conversion (digital output)
CMOS - 5
General Architecture of CMOS-Based Image Sensors
Pixel Array
Horizontal Scanner / Column
Buffers
Vert
ical
Sca
nner
fo
r Row
Sel
ectio
n
Control &
TimingLogic (opt.)
Bias Generation
& DACs(optional)
Analog Amplification
A/D conversion (optional)
Analog Output
Digital Output
CMOS - 6
Common CMOS Features
• CMOS sensors/multiplexers utilize the same process as modern microchips
– Many foundries available worldwide– Cost efficient– Latest processes available down to 0.13 µm
• Electronic shutter (snapshot, rolling shutter, non-destructive reads)– No mechanical shutter required
• CMOS process enables integration of many additional features– Various pixel circuits from 3 transistors up to many 100 transistors per pixel– Random pixel access, windowing, subsampling and binning– Bias generation (DACs)– Analog signal processing (e.g. CDS, programmable gain, noise filter)– A/D conversion – Logic (timing control, digital signal processing, etc.)
• Low power consumption• Radiation tolerant (by process and by design)
CMOS - 7
Special Scanning Techniques Supported by CMOS
• Different scanning methods are available to reduce the number of pixels being read:
– Allows for higher frame rate or lower pixel rate (reduction in noise)– Can reduce power consumption due to reduced data
Random Read• Random access (read
or reset) of certain pixels
• Selective reset of saturated pixels
• Fast reads of selected pixels
Subsampling• Skipping of certain
pixels/rows when reading the array
• Used to obtain higher frame rates on full-field images
Windowing• Reading of one or
multiple rectangular subwindows
• Used to achieve higher frame rates (e.g. AO, guiding)
Binning*• Combining several
pixels into larger super pixels
• Used to achieve lower noise and higher frame rates
* Binning is typically less efficient in CMOS than in CCDs.
CMOS - 8
Astronomy Application: Guiding• Special windowing can be used to
perform full-field science integration in parallel with fast window reads. Simultaneous guide operation and science
data capture within the same detector.
Full field row Window Full field row
Full field row
Window Window
Full field row Full field row
• Two methods possible:– Interleaved reading of full-field and window
• No scanning restrictions or crosstalk issues• Overhead reduces full-field frame rate
– Parallel reading of full-field and window• Requires additional output channel• Parallel read may cause crosstalk or conflict• No overhead maintains maximum full-field
frame rate
CMOS - 9
Electronic Shutter: Snapshot vs. Rolling Shutter
Row 1
Row 2
Row 3
Row 4
Row 5
start integrating
stop integrating
Read pixels of selected row
start 2nd integration if pixel supports
“integrate while read”
integration time
integration time
integration time
integration time
integration time
• Snapshot Shutter– All rows are integrating at the same time.– Typically more transistors per pixel and
higher noise.
Row 1 integration time
• Rolling Shutter (Ripple Read)– Each row starts and stops integrating at
a different time (progressively).– Typically less transistors per pixel and
lower noise.
integr
Row 2 integration time inte
Row 3 integration time int
Row 4 integration time i
Row 5 integration time
start integrating
Read pixels of selected row stop
integrating
CMOS - 10
Stitching Enables Large Sensor Arrays
array
horiscan1
horiscan2
V3
V2
V1
array array array
array array array
array array array
horiscan1 horiscan2
V3
V2
V1
• The small feature size of modern CMOS processes limits the maximum area that can be exposed in one step (so-called reticle) to about 22 mm.
• However, larger chips can produced by breaking up the design into smaller sub-blocks that fit into the reticle.– Sub-blocks are exposed one after
another– Some blocks are used multiple
times– Ultimate limit is given by wafer size
Reticle
Stitched CMOS Sensor
22mm
CMOS - 11
CMOS-Based Detector Systems• Three possible CMOS Detector Electronics Configurations
Detector ArrayIncludes
ADC, bias & clock
generation
Digital data
Acquisition System
Single Chip– All electronics integrated
in sensor chip– Small, low system power– Not always desirable (high
design effort, glow) Detector Array
Requires ext. ADC, bias
and/or clock generation
Analog output Bias Clocks
ADC DACLogic
Memory
Acquisition System
Digital data
Discrete Electronics– Assembly of discrete
chips and boards– Large, higher power– Reusable, modular, only
PCB design required
Analog output
Bias Clocks
ASIC
Acquisition System
Digital data
Detector ArrayRequires ext.
ADC, bias and/or clock generation
Dual Chip– All electronics integrated in
a single companion chip– Small, low system power– Can be placed next to
detector => low noise
CMOS - 12
Monolithic CMOS
Reset
Select
SF
PD
Read Bus
Read Bus
Select
SFPinned PD
Reset
p-sub
n+n+p+
TG
• A monolithic CMOS image sensor combines the photodiode and the readout circuitry in one piece of silicon
– Photodiode and transistors share the area => less than 100% fill factor– Small pixels and large arrays can be produced at low cost => consumer
3T Pixel
4T Pixel
applications (digital cameras, cell phones, etc.)
photodiode transistors
CMOS - 13
Complete Imaging Systems-on-a-Chip• Monolithic CMOS technology has enabled highly integrated,
complete imaging systems-on-a-chip:– Single chip cameras for video and digital still photography– Performance has significantly improved over last decade and is
better or comparable to CCDs for many applications.– Especially suited for high frame rate sensors (> Gigapixel/s) or
other special features (windowing, high dynamic range, etc.)
2 Mpixel HDTV CMOS Sensor
Quantum Efficiency of a CMOS sensor
Si PINNIR AR coating
Si PINUV AR coating
3T pixelw/ microlenses
• However, monolithic CMOS is still limited with respect to quantum efficiency:
– Photodiode is relatively shallow => low red response
– Metal and dielectric layers on top of the diode absorb or reflect light => low overall QE
– Backside illumination possible, but requires modification of CMOS process
photodiode
• Microlenses increase fill factor:
CMOS - 14
Outline
• General Concept & Architecture• Common Features of CMOS Sensors • Stitching Technology Enables Large Arrays• Monolithic CMOS
• Hybrid CMOS– History of Hybrid CMOS– ROIC Input Cells – Detector Materials & Properties
• Low Noise Through Multiple Sampling
• CMOS Processing and General Limitations• Emerging Technologies
– Vertical Integration– Geiger-Mode Avalanche Photodiode Arrays
• Comparison: CMOS vs. CCD for Astronomy
Markus Loose
Alan Hoffman
Vyshi Suntharalingam
CMOS - 15
CMOS Processing Evolution for Hybrid Focal Planes
MOS w/surface channel CCD
CMOS
1975 1980 1985 1990 1995 2000 2005
PMOS or NMOS
Indium bump hybrid invented, circa 1975
CMOS ultimately "won" due to ease of design and availability of foundries
CMOS - 16
Sensor Chip Assembly (SCA) Structure:Hybrid of Detector Array and ROIC Connected by Indium Bumps
Mature interconnect technique:–Over 4,000,000 indium bumps per SCA demonstrated–99.9% interconnect yield
Silicon Readout Integrated Circuit (ROIC)
Indium bump
Detector Array
16,000,000
• Also called a Focal Plane Array (FPA) or Hybrid Array
Detector Array
CMOS - 17
CMOS SCA Revolution
• Large CMOS hybrids revolutionized infrared astronomy• Growth in size has followed "Moore's Law" for over 20 years
– 18 month doubling time
1E+02
1E+03
1E+04
1E+05
1E+06
1E+07
1E+08
1E+09
1980 1985 1990 1995 2000 2005 2010Year First used in Astronomy
Num
ber o
f Pix
els
per A
rray MWIR arrays
Moore's law with 18 month doubling timepredicted
CMOS - 18
Input Circuit Schematics
Output S/F FET
reset switch
enable switch
detector
SFD
inputFET Cint
DI
load
driver
Cfb
CTIA
CMOS - 19
Three Most Common Input Circuits for CMOS ROICs
Circuit
SFD(Source Follower per Detector)also called "Self Integrator"
CTIA(Capacitance Transimpedance Amplifier)
DI(Direct Injection)
Advantages
• simple• low noise• low FET glow• low power
• very linear• gain determined by
ROIC design (Cfb)• detector bias remains
constant
• large well capacity• gain determined by
ROIC design (Cint)• detector bias remains
constant• low FET glow• low power
Disadvantages
• gain fixed by detector and ROIC input capacitance
• detector bias changes during integration
• some nonlinearity
• more complex circuit• FET glow• higher power
• poor performance at low flux
Comments
Most common circuit in IR astronomy
Very high gains demonstrated
Standard circuit for high flux
CMOS - 20
Temperature and Wavelengths ofHigh Performance Detector Materials
Si:As IBC
Si PIN
InSb
InGaAsSWIR HgCdTe
LWIR HgCdTe
MWIR HgCdTe
Approximate detector temperatures for dark currents << 1 e-/sec
CMOS - 21
Detector Material Choices for CMOS Hybrid Arrays
DetectorMaterial
Si PIN
InGaAs
HgCdTe:1.7m2.5 m5.2 m10 m
InSb
Si:As IBC(BIB)
SpectralRange*, m
0.4 – 1.0
0.9** – 1.7
0.9** – 1.70.9** – 2.50.9** – 5.2 5 – 10
0.4 – 5.2
5 – 28
* Long wave cutoff is defined as 50% QE point** Spectral range can be extended into visible range by removing substrate*** Approximate detector temperatures for dark currents << 1 e-/sec
OperatingTemp***, K
~ 200
~ 130
~ 140~ 90~ 50
~ 25?
~ 35
~ 7
General Comments
• All detectors can have:– 100% optical fill factor– 100% internal QE (total QE
depends on AR coat)• Exception: Si:As is 40-70%
between 5 and 10 m
• ROICs are interchangeable among detectors (except Si:As)
• HgCdTe and InGaAs require special packaging due to CTE mismatch between detector and ROIC
CMOS - 22
Noise in CMOS SCA/Hybrids
• Temporal– White (uncorrelated) noise
• Reduced by multiple sampling– 1/f (drift) noise
• Not a limiting factor in most astronomy focal planes• Fixed pattern noise
– Caused by residual non-uniformity after calibration• Can be reduced (eliminated?) by calibrating at multiple points in the
dynamic range• Random Telegraph Signal (RTS)
– Randomly occurring charge trapping/detrapping events – Process, design and characterization dependent
• Personal experience: have not seen this
CMOS - 23
CMOS SCA Sampling Techniques
• Periodic sampling of detector signal possible during a long integration• Two general methods of white noise reduction by multiple sampling
– Fowler sampling: average 1st N samples and last N samples; then subtract– Sample up the ramp (SUTR): fit line (or polynomial) to all samples
Reset begins integration
Voltage ramp for
a single pixel
CMOS - 24
Example of Noise vs Number of Fowler Samples
Data courtesy of Dr. Craig McMurtry, University of Rochester
2 e-
100 sec integrationsin all cases
Bare multiplexer
CMOS - 25
6
8
10
12
10 20 30 40 50
Number of Fowler Pairs
Rel
ativ
e S/
N
Fowler
SUTR (100 samples)
Example of Fowler and SUTRSampling in Uncorrelated (White) Noise Limit
Peak at Fowler N/3
6% difference
CMOS - 26
Hybrid CMOS Summary
• CMOS ROIC– Wide choice of processing foundries and analog circuits– "System on a chip" is possible
• Clocks & biases• A/D & DAC• Any digital function
• Detectors– Wide choice of detector materials– Interchangeability among detectors and ROICs
• SCAs– Up to 4K x 4K arrays successfully hybridized
CMOS - 27
Outline
• General Concept & Architecture• Common Features of CMOS Sensors • Stitching Technology Enables Large Arrays• Monolithic CMOS
• Hybrid CMOS– History of Hybrid CMOS– ROIC Input Cells – Detector Materials & Properties
• Low Noise Through Multiple Sampling
• CMOS Processing and General Limitations• Emerging Technologies
– Vertical Integration– Geiger-Mode Avalanche Photodiode Arrays
• Comparison: CMOS vs. CCD for Astronomy
Markus Loose
Alan Hoffman
Vyshi Suntharalingam
CMOS - 28
CCD CMOS> 35 years of evolution
“Trailing edge” fabsEconomics of scale accelerate progressLower fabrication cost, Foundry access
High resistivity (deep depletion) substratesControlled temperature ramps & stress control
Epi doping optimized for digital CMOSScalable to 300mm
Buried channelMultiple oxidation cycles
Complex implant engineering Rapid Thermal Processing (RTP)
Single gate dielectric thickness Multiple gate dielectric thicknesses
Doped polysilicon (single type) Complementarily doped polysiliconSilicided polysilicon and FET source/drain
Highly nonplanar surfacesConservative design rules
Fine-line patterningMultiple metal layers (dense routing)
Vulnerable to space-radiation-induced traps Highly suitable for long-term space-based applications
Process Comparison
Stacked via to poly2m
180-nm SRAM cell2m 2m
Four-Poly OTCCD
CMOS - 29
<0.25m CMOS Technology Features
Feature 0.35 - 0.60 m 0.18 - 0.25 m
Field Isolation LOCOS STI
Voltage 3.3 - 5V 1.8 - 2.5V
Gate Oxide 70 - 125A 32 - 50A
Device Polycide/Poly Salicide
Junction Profile Graded Junction Shallow Junction
Planarization SOG and Reflow CMP
Thermal Budget Furnace Anneal RTP
Spacer Etch Oxide spacer SiN spacer
Dielectric Material SiO2 SiO2/SiN/SiON
CMOS - 30
Poly
STI
ONO spacer
Double S/D imp
PeripheryPixel
Deposit oxideSpin coat organic material
Etch-back and remove oxide
Organic materialOxide
Photo resist
Silicide
Remove organic materialPattern oxide (photo/etch)
Form silicide on peripheral devices
CMOS Pixel Process Flow
Adapted from S. Wuu, TSMC
CMOS - 31
0.3um
Silicide gate
non-silicide S/D 0.4um
Cross Sectional TEM Photograph of Pixel
Courtesy S. Wuu, TSMC
CMOS - 32
RST
ROW
OUT
VDD
photodiode
Pixel Layout
p-epi
n-Wellp-wellField Oxide
VDD
p+
ROWOUT
n+
p+ Substrate
RST
Limitations of Standard Bulk CMOS APS
• Fill factor tradeoff– Photodetector and pixel transistors share
same area– PD from Drain-Substrate or Well-Substrate
diode
• Low photoresponsivity– Shallow, heavily doped junctions– Limited depletion depth– Absorption and reflection in poly, metal, and
oxide layers– Surface recombination at Si/SiO2 interface– QE*FF > 60% is good, many < 20%
• High leakage– LOCOS/STI, salicide– Transistor short channel effects
• Substrate bounce and transient coupling effects
CMOS - 33
Conventional Monolithic APS 3-D Pixel
pixel
AddressingA/D, CDS, …
Add
ress
ing
LightPD
3Tpixel
PD
ROIC
Processor
Advantages of Vertical Integration
• Pixel electronics and detectors share area
• Fill factor loss• Co-optimized fabrication• Control and support electronics
placed outside of imaging area
• 100% fill factor detector• Fabrication optimized by layer
function• Local image processing
– Power and noise management• Scalable to large-area focal
planes
CMOS - 34
Approaches to 3D Integration
10 m
Bump Bond used to flip-chip interconnect
two circuit layers
Two-layer stack using Lincoln’s SOI-based vias
Two-layer stack with insulated vias through
thinned bulk Si
10 mPhoto Courtesy of RTI
3D-Vias
Tier-1
Tier-2
(To Scale)
10 m
3D-Vias
CMOS - 35
Tiled Arraymechanical mockup
Tile withDaughter Chip
8 mm
FoundryChip
pixel
Four-Side Abuttable Goal
• 3-D CMOS imagers tiled for large-area focal planes• Foundry fabricated daughter chip bump bonded to non-imaging
side
CMOS - 36
Cross Sections Through 3-D Imager
5 m
SOI-CMOS (Wafer 2)
Photodiode(Wafer 1)
Pixel
3D-ViaCMOS Vias
Transistor
BondInterface
Diode
SEM cross section
8 m decorated
CMOS - 37 Presented at 2005 ISSCC
Four-Side Abuttable Vertically Integrated Imaging Tile
• Wafer-Scale 3D circuit stacking technology– Silicon photodetector tier– SOI-CMOS address and readout tier
• Per-pixel 3D interconnections– 1024x1024 array of 8mx8m pixels– 100% fill factor– >1 million vertical interconnections per imager
Front Illuminated Back Illuminated
CMOS - 38
Geiger-Mode Imager: Photon-to-Digital Conversion
APD
Digitaltimingcircuit
Digitallyencodedphotonflight time
photon
Lensletarray
APD/CMOS array
Focal-plane concept
Pixel circuit
• Quantum-limited sensitivity• Noiseless readout• Photon counting or timing
CMOS - 39
3-D Laser Radar Sensor Development
Active intensity image
Npe= 105
SUVSUV behind camouflage
• Objective: single flash, non-scanned 3D area imager– Pixel stores range, not intensity, information
• 3-D imaging provides– Robust object recognition
• relatively independent of lighting, reflectivity– Separates objects behind foliage, camouflage
3-D Brassboard image
QuickTime™ and a decompressor are needed to see this picture.
CMOS - 40
Technology Development Evolution
1996
2001
APD’s
Discrete 4x4 arrays
4x4 arrays wire bonded to 16-channel
CMOS readout 32x32 arrays fully integrated with
32x32 CMOS readout
CMOS - 41
APD APDTier-1: Avalanche Photodiode
Tier-2: 3.3V FDSOI CMOS
Tier-3: 1.5V FDSOI CMOS
Pseudorandom counter circuit
Avalanche PD
APD drive/sense circuit
VISA APD Pixel Circuit (~250 transistors/pixel)
3D-Integrated Tier-1/Tier-2 wafer pair electrical test vehicle
150 mm
3D Laser Radar Focal Plane (3D)2
• Laser radar focal plane based on single-photon-sensitive Geiger-mode avalanche photodiodes
– 64 x 64 demonstration circuit (scalable)– Pixel size reduction from 100 m to 30 m– Timing resolution reduction from 1 ns to
0.1 ns– 100x reduction in voxel volume
CMOS - 42
Outline
• General Concept & Architecture• Common Features of CMOS Sensors • Stitching Technology Enables Large Arrays• Monolithic CMOS
• Hybrid CMOS– History of Hybrid CMOS– ROIC Input Cells – Detector Materials & Properties
• Low Noise Through Multiple Sampling
• CMOS Processing and General Limitations• Emerging Technologies
– Vertical Integration– Geiger-Mode Avalanche Photodiode Arrays
• Comparison: CMOS vs. CCD for Astronomy
Markus Loose
Alan Hoffman
Vyshi Suntharalingam
CMOS - 43
Comparison CMOS vs. CCD for Astronomy
Property CCD Hybrid CMOSResolution > 4k x 4k 2k x 2k in use, 4k x 4k demonstrated
Pixel pitch 10 – 20 µm 18 – 40 µm, < 10 µm demonstrated
Typ. wavelength coverage
400 – 1000 nm 400 – 1000 nm with Si PIN400 – 5000 nm with InSb or HgCdTe
Noise Few electrons Few electrons with multiple sampling
Shutter Mechanical Electronic, rolling shutter
Power Consumption High Typ. 10x lower than CCD
Radiation Sensitive Much less susceptible to radiation
Control Electronics High voltage clocks, at least 2 chips needed
Low voltage only, can be integrated into single chip
Special Modes Orthogonal Transfer,Binning,Adaptive Optics
Windowing, Guide Mode,Random Access, Reference Pixels,Large dynamic range (up the ramp)
Silicon PIN hybrid detectors have become a serious alternative to CCDs providing a number of significant advantages, specifically for large mosaic focal plane arrays.
CMOS - 44
Conclusion
CMOS
It’s happening!
CCD