IBM Research
CMOS Device Scaling, Past, Present, CMOS Device Scaling, Past, Present, and Futureand Future
Effendi Leobandung
IBM T.J. Watson Research CenterYorktown Heights, New York 10598
2 Leobandung, IBM T.J. Watson research Center
OUTLINEOUTLINE•Brief History of CMOS Scaling
•Current CMOS Devices:•FINFET on bulk and/or insulator•Ultra Thin Body SOI
•Future Scaling:•Nanowire•Higher mobility III-V/Ge Device•Beyond CMOS
•Conclusion
3 Leobandung, IBM T.J. Watson research Center
Why is IBM in Semiconductor Business?Why is IBM in Semiconductor Business?
Mainframes Unix Servers
• Largest Area, highest frequency and power chips• Highest power-in, power-out, …
• Most “advanced” interconnect:• Most number of metal layers• Most number of “pins” on packages
• Most reliable• ……
4 Leobandung, IBM T.J. Watson research Center
OUTLINEOUTLINE•Brief History of CMOS Scaling
•Current CMOS Devices:•FINFET on bulk and/or insulator•Ultra Thin Body SOI
•Future Scaling:•Nanowire•Higher mobility III-V/Ge Device•Beyond CMOS
•Conclusion
5 Leobandung, IBM T.J. Watson research Center
CMOS Scaling: CMOS Scaling: DennardDennard’’ss TheoryTheory
p substrate, doping *NA
Scaled Device
L/ xd/
GATEn+ source
n+ drain
WIRINGVoltage, V /
W/tox/
SCALING:Voltage: V/aOxide: tox /aWire width: W/aGate Length: L/aDiffusion: xd /aSubstrate: a*NA
RESULTS:Higher Density: ~a2Higher Speed: ~aPower Density: ~Constant
SmallerFasterLower Power
Scaled technology generations
Power - Performance
6 Leobandung, IBM T.J. Watson research Center
CMOS Scaling: A Closer Look @ Planar DeviceCMOS Scaling: A Closer Look @ Planar Device
SCALING:Voltage: V/aOxide: tox /aWire width: W/aGate Length: L/aDiffusion: xd /aSubstrate: a*NA
Hasn’t followed exactly Vdd/ scaling; Low power drives Vdd scaling but challenged by SRAM Vmin and non scaled VT.
SiO2 scaling hit a brick wall at ~ 90 nm generation. Saved by introduction of HK/MG. But further Tox scaling at 22nm and beyond challenged by gate lkg and reliability.
Gate length scaling in 65/45/32/22* are limited (10-15%) due to SCE. Also causes significant capacitance issue at 22nm node and beyond.
. Junction depth scaling & abruptness improvement – tradeoff in parasitic resistance, junction lkg and GIDL. Increased substrate doping for better SCE: increased jct lkg; increased Vtmm and AVT (driven by random dopant fluctuation) – gating SRAM Vmin
7 Leobandung, IBM T.J. Watson research Center
Non Conventional ScalingNon Conventional Scaling
Silicon on Insulator– First introduced into production by IBM
– Parasitic Capacitance Reduction -> Better overall chip performance at same drive current.
– Floating Body Effect -> Dynamically lower threshold Voltage and increase overdrive . Careful modeling of hysteresis needed.
Strain Silicon:– Embedded SiGe source drain for PFET -> Enhanced hole mobility with unaxial
stress. First introduced by Intel– Dual Stress Contact Liner -> Applicable for both NFET and PFET. First introduced
by IBM in 90 nm node– Stress Memorization Technique -> Mainly use to enhance electron mobility. First
introduced by TSMC. High-k Metal Gate:
– Enable gate dielectric scaling by reducing poly depletion and increasing intrinsic gate capacitance
– Two alternate path -> Gate Last (Intel) and Gate First (IBM&Alliance)
8 Leobandung, IBM T.J. Watson research Center
Historical account on SOIHistorical account on SOI Concept was introduced around 1980’s Key benefit:
– Parasitic capacitance reduction in source/drain junction due to lower k in buried oxide
– Floating body induced threshold lowering during switching.
– Stacked circuit Benefit Easier to integrate Significant initial challenges due to
defect introduced with lateral seeding and SIMOX.
IBM works with vendor to overcome material and substrate challenges.
– Today we have established SOI wafer infrastructure.
Accurate SOI Model is also a key challenges:
– IBM has worked with academic and vendor to provide accurate SOI model that take into account floating body benefit and hysteresis
Buried Oxide
Substrate
Gate
Source Drain Cj
Majority carriercharge accumulation
Leobandung et al.
45% faster
9 Leobandung, IBM T.J. Watson research Center
Mobility enhancement using Mobility enhancement using eSiGeeSiGe Embedded SiGe:
– Replace source drain with SiGe. Larger lattice constant -> Net effect compression under the channel
– Likely deliver the highest stress magnitude since due to stress proximity to channel
Introduced by Intel in 90 nm Key challenges:
– Cavity shape and distance to balance stress with short channel effects
– Selective epitaxy and preclean -> Introduction of insitu epi preclean help tremendously.
SiGe SiGe
Thompson et al., Intel
10 Leobandung, IBM T.J. Watson research Center
Mobility enhancement with Dual Stress LinerMobility enhancement with Dual Stress Liner
Yang et al.
Dual Stress Liner:– Utilized Compressive and Tensile
Nitride Liner to stress silicon channel
– NFET Ieff improvement by up to 20% and PFET Ieff improvement by up to 32%
In production in IBM for more than 10 years
Challenges:– Deposit conformal film under
stress/strain without peeling
– IBM collaborate with tool vendor to modify film property successfully.
Yang et al.
11 Leobandung, IBM T.J. Watson research Center
Scaling of gate dielectric with HighScaling of gate dielectric with High--k k
Two existing flow in production Gate First: High-k and Metal Gate
Prior to Source Drain Anneal:– More scalable to higher Cinv
– More manufacturable -> similar to conventional Poly/SiON
– PFET Work function difficult to achieve
Gate Last: Use dummy gate which is replaced with Metal gate Post source drain anneal:
– Easier to set PFET Work Function
– Integration flow and planarity requirement very challenging
– More compatible with future device flow
IBM Gate First
Intel Gate Last
12 Leobandung, IBM T.J. Watson research Center
0.8
0.9
1.0
1.1
1.2
1.3
1.4
1.5
10100Technology Node
Tinv
or [
EOT+
0.4n
m] (
nm)
32 22
Gate Last ReferencesK. Mistry e al., IEDM’07 S. Natarajan et al., IEDM’08 C. Auth et al., VLSI’12
Gate First ReferencesD-G. Park et al., VLSI’04V. Narayanan et al., VLSI’06M. Chudzik et al., VLSI’07F. Arnaud et al., IEDM’09B. Greene, et al., IEDM’09S.Narasimha et al., IEDM’12(IBM 22nm SOI)
Gate First
Gate Last
Gate First AdvantageGate First Advantage
Industry-leading Tinv values achieved by Gate First(Narasimha, IEDM’12)
13 Leobandung, IBM T.J. Watson research Center
OUTLINEOUTLINE•Brief History of CMOS Scaling
•Current CMOS Devices:•FINFET on bulk and/or insulator•Ultra Thin Body SOI
•Future Scaling:•Nanowire•Higher mobility III-V/Ge Device•Beyond CMOS
•Conclusion
14 Leobandung, IBM T.J. Watson research Center
Advantage of Advantage of UndopedUndoped FullyFully--Depleted FinFETsDepleted FinFETs
Short channel effect controlled by the thickness of the thin body instead of channel doping
– Reduced random dopant fluctuation– Improved mobility due to lower vertical field and less coulombic scattering– Improved DIBL and SS
D. Frank et al, IEDM 1992 W. Haensch et al, IBM J of R&D July 2006
Planar bulk Planar FDSOI FD DGFET/FinFET
Source
Source
DrainGate Source
Source
DrainGate
Lg
Dfin
m
TinvSource
Drain
Hfin
Terminology: Terminology: HfinHfin, , DfinDfin
15 Leobandung, IBM T.J. Watson research Center
A Decade of FINFET R&D at IBM/AllianceA Decade of FINFET R&D at IBM/Alliance
High speed FinFET deviceN&P (2001)
FinFETfully-depleted RO demo(2003)
Funtional SRAM 0.22um2 (2002)
0.063um2 SRAM with FinFET (2010)
FinFETCMOS demo(2002)
Conformal doping in FinFET(2011)
MultiVt solution in FINFET (2012)
0.1
1
10
100
1000
10000
400 500 600 700 800
Ieff (uA/um)
Ioff
(nA
/um
)
WF-Tuned-Multi_VtNch-Tuned-Multi_VtLdes-Tuned-Multi_VtDfin-Tuned-Multi_VtCounterDoping (WF f ixed at highest VT)
Dfin fr
om 1
0 to
6nm
Lg from 18 to 30nm
Nchfrom 5e16 to 4.5e18cm
-3
16 Leobandung, IBM T.J. Watson research Center
DamageDamage--free Conformal Dopingfree Conformal Doping
implanted
Conformal doping
■ Avoid implant damage on Fins – no TED ■ Improve junction gradient ■ Reduce external resistance■ Many other conformal doping idea out there such as plasma doping, solid
phase doping, etc-> need collaboration with tooling vendor
Epi-merge
T. Yamashita, VLSI 2011
17 Leobandung, IBM T.J. Watson research Center
Fully Depleted (FD) Device Fully Depleted (FD) Device
FINFET (14nm node)
– Demonstrated A 0.063 μm2 FinFET SRAM cell demonstration with conventional lithography using a novel integration
– Conformal doping is crucial for 3D devices to reduce parasitic resistance.
V. Basker et al. VLSI ’10
18 Leobandung, IBM T.J. Watson research Center
silicon substrate
HCH
HCS
silicon substrate
Junction-IsolatedBulk FinFET
Dielectric-IsolatedBulk FinFET
Gate Electrode Gate Electrode
Fin Fin
Punch-through stop
dep/etch ox.dep/etch ox.
ReplacementOxide fill
SOI is built for SOI is built for FinFETFinFET TechnologyTechnology
Fin on bulk–Fin height controlled by ox etch –Complex isolation scheme–Fin doping control possible issue–Uses bulk wafer
silicon substrate
Dielectric-IsolatedSOI FinFET
Gate Electrode
Fin
BOX
Fin on SOI–Fin height set by substrate–Simpler isolation scheme–Requires SOI wafer
Fin on oxide over bulk–Doping isolation requirement removed–Isolation scheme still complex–Uses bulk wafer
Courtesy : G. Patton
19 Leobandung, IBM T.J. Watson research Center
6nm SiGe channel
Ge Hf Ti Ni
SiGeRSD
40nm
BOX
gate
State-of-the-art ETSOI SiGe Transistor
•6nm cSiGe
•22nm Lgate
•100nm contacted gate pitch
•Gate-first HK / MG
• ISBD SiGe RSD
Contact
(K.Cheng et al., IEDM’12)
21 Leobandung, IBM T.J. Watson research Center
OUTLINEOUTLINE•Brief History of CMOS Scaling
•Current CMOS Devices:•FINFET on bulk and/or insulator•Ultra Thin Body SOI
•Future Scaling:•Nanowire•Higher mobility III-V/Ge Device•Beyond CMOS
•Conclusion
22 Leobandung, IBM T.J. Watson research Center
G
Si NW
SD
20 nm
5 nmHKMG
Poly-SiSiO2
Si Si nanowirenanowire gate all around (GAA) devicegate all around (GAA) device
GAA devices offer improved electrostatics and a further scaling path Fabrication challenges (8nm & beyond)
(Sarunya et al. VLSI’10)
24 Leobandung, IBM T.J. Watson research Center
RRextext vs. vs. NanoNano Wire SizeWire Size
As the NW size gets smaller, an increase in series resistance, REXT is observed.
This is largely due to an unscaled spacer width with respect to nanowire size.
NW
Epithicken
Gate
NW
Epithicken
Gate
Bangsaruntip et al.
25 Leobandung, IBM T.J. Watson research Center
NanoWireNanoWire Capacitance Capacitance
Capacitance measured for NW array as small as DEFF ~ 3 nm. C/A for NW diverges from planar limit and shows dependency in NW size, as is expected for
cylindrical capacitors. Parasitic cap in RO structure is approximately half of the total capacitance.
Gated p-i-n NW Diode )1ln(1
rtoxrA
C
2rE =
Bangsaruntip et al.
26 Leobandung, IBM T.J. Watson research Center
Why nonWhy non--Si Channels? Si Channels? –– High Electron & Hole High Electron & Hole MobilitiesMobilities
0.1785077000InSb
0.7310003000GaSb
0.3550040000InAs
0.7430012000InGaAs(53%)
1.424008500GaAs
1.342005400InP
0.6619003900Ge
1.124801350Si
Eg(eV)
µh(cm2/Vs)
µe(cm2/Vs)
Material
27 Leobandung, IBM T.J. Watson research Center
IIIIII--V CMOS ChallengesV CMOS Challenges
Czornomaz et al.
28 Leobandung, IBM T.J. Watson research Center
- Gate-first UTB III-V on insulator MOSFET with Si ICL- Self-aligned S/D metal alloy- Clear benefit of on-insulator structure compared to planar on InAlAs- Large size wafer supply, ESH, tooling are key area needing innovations
SOI is also built for handling III-V on Insulator
(L.Czonomaz et al., IEDM’12)
•UTB III-V MOSFET •DIBL•GF & RSD
29 Leobandung, IBM T.J. Watson research Center
First Demonstration of high mobility CMOSFirst Demonstration of high mobility CMOS
30 Leobandung, IBM T.J. Watson research Center
Beyond CMOS ? Beyond CMOS ?
Example : Single Electron Quantum Dot Transistor
31 Leobandung, IBM T.J. Watson research Center
SummarySummary
Conventional Scaling lasted until around 90 nm node
Since then new device structure has manage to fill in the gap:– SOI
– Stressor
– High-k
– FINFET
Where do we go from here:– Likely both new device structure and new material is needed
– High mobility III-V/Ge
– Other speculative structure : CNT, graphene, quantum devices, etc.