CMOS

StyleProcess

-GM

MOSFET

source

drain

substrate

SiO2 insulator

metal / polysilicon contact

gate

+

-

+G

S

D

10N-type

S

D

n channelnMOS

MOSFET

source

drain

substrate

SiO2 insulator

metal /polysilicon contact

gate

-

+

-G

S

D

10P-type

S

D

p channelpMOS

Inverter

pMOS

nMOS

Vi Vo

A A’

pMOS

nMOS

1

10

VGSp

VGSn

VDD = +5V

VGSn = Vi – 0V = 0V – 0V = 0V

VGSp = Vi – (+5V) = 0V – 5V = -5V

When Vi = 0V= 5

VGSn = Vi – 0V = 5V – 0V = 5V

VGSp = Vi – (+5V) = 5V – 5V = 0V

When Vi = +5V

pMOS = “ON” nMOS = “OFF”

pMOS = “OFF” nMOS = “ON”

= 5

= 0

= 0

= 0

= -5

01

Logic Design (NOR Gate)

Pull-upnetwork

Pull-downnetwork

Inputs

Inputs

NOR Gate

A B Y

0 0 1

0 1 0

1 0 0

1 1 0

A

A

B

B

VDD

Y

0 0

1

pMOS (1)

nMOS (0)

Comparison

A

A’

+

A A’

pMOS

nMOS

+

Bipolar CMOSEnergy efficiencyLarger energy dissipationSlowerLess HeatEase of construction

FasterMore heat

Quad-Core AMD Opteron processorAMD Phenom II overclocked with liquid helium (6.5 GHz @ -267 degrees celcius.Samsung Galaxy

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