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Introduction Cmos(1)

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    Circuits and CMOS Technology

    Hooman NabovatiSadjad Institute for Higher Education

    Mashhad, Iran

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    19th Century - Solid-State Rectifiers 1907 - Application of Crystal Detector in Radio

    1947 - BJT Constructed by Bardeen and Brattain andschockly

    2

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    Invention: 1947,at Bell Laboratories.

    John Bardeen, WalterBrattain, andWilliam Schockly developed the firstmodel of transistor (a Three Pointstransistor, made with Germanium)

    They received Nobel Prize in Physics.

    12/21/20093

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    - TM Device characteristics

    # of transistors 42 000 000 Line width: 0.18 m=>( 0.13 m)

    P4 die size: 224 mm

    4

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    12/21/20095

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    Evolution in Complexity

    6

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    u yMPU Gate Length (nm)

    30

    35

    20

    25

    10

    15

    0

    5

    7

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    ec no ogy oa map as emor esbits/cm2

    .

    . +

    12/21/20098

    1.00E+10

    2009 2010 2011 2012 2013 2014 2015 2016 2017 2018 2019 2020 2021 2022 2023 2024

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    em con uc or anu ac ur ng ar e

    Systemspecification

    Design PackagingFabrication TestIC

    $200 billion

    Tools: designsimulationemulation

    Equipment Material Equipment Equipment

    $3.4 billion $16.8 billion $2.0 billion $5.2 billion

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    11

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    - Typically use p-type substrate for nMOS transistors

    Requires n-well for body of pMOS transistors

    A

    n+ +

    YDD

    n+ +

    SiO2

    n+ diffusion

    p+ diffusion

    p substraten well polysilicon

    metal1

    14

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    Substrate must be tied to GND and n-well to VDD Metal to lightly-doped semiconductor forms poor

    connection called Shottky Diode

    A

    Y DD

    n+

    p substrate

    p+

    n well

    n+p+ n+ p+

    /2115/09

    substrate tap well tap

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    Transistors and wires are defined by masks

    Cross-section taken along dashed line

    A

    Y

    GND VDD

    substrate tap well tapnMOS transistor pMOS transistor

    16

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    Six masks

    n-well

    Polysilicon

    n well

    p+ diffusion

    Contactn+ Diffusion

    MetalContact

    p+ Diffusion

    Metal

    /2117/09

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    Start with blank wafer

    Build inverter from the bottom up

    First step will be to form the n-well 2

    Remove layer where n-well should be built

    Implant or diffuse n dopants into exposed wafer Strip off SiO2

    p substrate

    18

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    Grow SiO2 on top of Si wafer 900 1200 C with H2O or O2 in oxidation furnace

    p substrate

    SiO2

    /2119/09

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    Spin on photoresist Photoresist is a light-sensitive organic polymer

    Softens where exposed to light

    SiO2

    Photoresist

    p substrate

    20

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    Expose photoresist through n-well mask

    Strip off exposed photoresist

    Photoresist

    p substrate

    SiO2

    /2121/09

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    Etch oxide with hydrofluoric acid (HF)

    Only attacks oxide where resist has been exposed

    SiO2

    Photoresist

    p substrate

    22

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    Strip off remaining photoresist

    Use mixture of acids called piranah etch

    Necessary so resist doesnt melt in next step

    p substrate

    SiO2

    23

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    - n-well is formed with diffusion or ion mplantation

    Diffusion Place wafer in furnace with arsenic gas

    Ion Implanatation

    Blast wafer with beam of As ions Ions blocked by SiO2, only enter exposed Si

    n well

    SiO2

    /2124/09

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    Strip off the remaining oxide using HF

    Back to bare wafer with n-well

    Subsequent steps involve similar series of steps

    n well

    p substrate

    25

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    Deposit very thin layer of gate oxide < 20 (6-7 atomic layers)

    Chemical Vapor Deposition (CVD) of silicon layer

    Forms many small crystals called polysilicon

    Heavily doped to be good conductor

    Polysiliconn ga e ox e

    p substraten well

    26

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    Use same lithography process to pattern polysilicon

    Polysilicon

    p substrate

    Thin gate oxide

    o ys con

    n well

    27

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    - Use oxide and masking to expose where n+ dopants

    s ou e use or mp an e

    N-diffusion forms nMOS source, drain, and n-well

    p substraten well

    28

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    - Pattern oxide and form n+ regions

    e -a gne processw ere ga e oc s us on

    Polysilicon is better than metal for self-aligned gates because itdoesnt melt during later processing

    n+ Diffusion

    n well

    29

    p substrate

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    - . Historically dopants were diffused

    Usually ion implantation today

    But regions are still called diffusion

    n well

    n+n+ n+

    p substrate

    30

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    - Strip off oxide to complete patterning step

    n wellsubstrate

    n+n+ n+

    /2131/09

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    - Similar set of steps form p+ diffusion regions for

    p source an ra n an su s ra e con ac

    p+ Diffusion

    p substraten well

    n+n+ n+p+p+p+

    32

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    Now we need to wire together the devices

    Cover chip with thick field oxide

    Etch oxide where contact cuts are needed

    Contact

    p substrate

    Thick field oxide

    n well

    n+n+ n+p+p+p+

    /2133/09

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    Sputter on aluminum over whole wafer

    Pattern to remove excess metal, leaving wires

    Metal

    Metal

    Thick field oxide

    n well

    n+n+ n+p+p+p+

    34

    p substrate


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