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CMOS LOGIC CIRCUIT DESIGN
CMOS LOGIC CIRCUIT DESIGN
CMOS LOGIC CIRCUIT DESIGN
John P. UyemuraGeorgia Institute of Technology
KLUWER ACADEMIC PUBLISHERS NEW YORK, BOSTON, DORDRECHT, LONDON, MOSCOW
eBook ISBN: 0-306-47529-4Print ISBN: 0-7923-8452-0
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Print ©2001 Kluwer Academic Publishers
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Dordrecht
DedicationThis book is dedicated to
Christine and Valerie
for all of the joy and happinessthat they bring into my life
Preface
This book is based on the earlier Kluwer title Circuit Design for CMOS/VLSIwhich was published in 1992. At that time, CMOS was just entering the main-stream as a technique for high-speed, high-density logic circuits. Although thetechnology had been invented in the 1960’s, it was still necessary to include Sec-tion 1.1 entitled Why CMOS? to justify a book on the subject. Since that time,CMOS has matured and taken its place as the primary technology for VLSI andULSI digital circuits. It therefore seemed appropriate to update the book and gen-erate a second edition.
Background of the Book
After loading the old files and studying the content of the earlier book, it became clear to me thatthe field is much more stable and well-defined than it was in the early 1990’s. True, technologicaladvances continue to make CMOS better and better, but the general foundations of modern digitalcircuit design have not changed much in the past few years. New logic circuit techniques appearingin the literature are based on well-established ideas, indicating that CMOS has matured.
As a result of this observation, the great majority of the old files were abandoned and replacedwith expanded discussions and new topics, and the book was reorganized to the form describedbelow. There are sections that didn’t change much. For example, Chapter 1 (which introducesMOSFETs) includes more derivations and pedagogical material, but the theme is about the same.But, many items are significantly different. For example, the earlier book contained about 60 pageson dynamic logic circuits. The present volume has almost three times the number of pages dedi-cated to this important area. In addition, the book has been written with more of a textbook flavorand includes problem sets.
ContentsChapter 1 introduces the MOS system and uses the gradual-channel approximation to derive thesquare-law equations and basic FET models. This sets the notation for the rest of the book. Bulk-charge models are also discussed, and the last part of the chapter introduces topics from small-device theory, such as scaling and hot electrons.
viii
Chapter 2 is an overview of silicon fabrication and topics relevant to a CMOS process flow.Basic ideas in lithography and pattern transfer are covered, as are items such as design rules, FETsizing, isolation, and latch-up. This chapter can be skipped in a first reading, but it is important tounderstanding some problems that are specific to layout and fabrication issues. It is not meant toreplace a dedicated course in the subject.
Circuit design starts in Chapter 3, which is a detailed analysis of the static CMOS inverter. Thestudy is used to set the stage for all of the remaining chapters by defining important DC quantities,transient times, and introducing CMOS circuit analysis techniques. Chapter 4 concentrates on adetailed study of the electrical characteristics of FETs when used as voltage-controlled electronicswitches. In particular, the treatment is structured to emphasize the strong and weak points ofnFETs and pFETs, and how both are used to create logic networks. This feeds into Chapter 5,which is devoted entirely to static logic gates. This includes fully complementary designs in addi-tion to variants such as pseudo-nMOS circuits and novel XOR/XNOR networks. Chapter 6 ontransmission gate logic completes this part of the book.
Dynamic circuit concepts are introduced in Chapter 7. This chapter includes topics such ascharge sharing and charge leakage in various types of CMOS circuit arrangements. RC modellingis introduced, and the Elmore formulas for the time constant of an RC ladder is derived. Clocks areintroduced and used in various types of clocked static and dynamic circuits. Dynamic logic familiesare presented in Chapter 8. The discussion includes detailed treatments of precharge/evaluate rip-ple logic, domino logic cascades, self-resetting logic gates, single-phase circuits and others. I havetried to present the material in an order that demonstrates how the techniques were developed tosolve specific problems. Chapter 9 deals with differential dual-rail logic families such as CVSLand CPL with short overviews of related design styles.
The material in Chapter 10 is concerned with selected topics in chip design, such as intercon-nect modelling and delays, crosstalk, BSD-protected input circuits, and the effects of transmissionlines on output drivers. The level of the presentation in this chapter is reasonably high, but the top-ics are complex enough so that the discussions only graze the surface. It would take another volume(at least) to do justice to these problems. As such, the chapter was included to serve as an introduc-tion for other courses or readings.
Use as a TextThere is more than enough material in the book for a 1-semester or 2-quarter sequence at the seniorundergraduate or the first-year graduate level. The text itself is structured around a first-year gradu-ate course entitled Digital MOS Integrated Circuits that is taught at Georgia Tech every year. Thecourse culminates with each student completing an individual design project.
My objectives in developing the course material are two-fold. First, I want the students to beable to read relevant articles in the IEEE Journal of Solid-State Circuits with a reasonable level ofcomprehension by the end of the course. The second objective is more pragmatic. I attempt tostructure the content and depth of the presentation to the point where the students can answer all ofthe questions posed in their job interviews and plant visits, and secure positions as chip designersafter graduation. Moreover, I try to merge basics with current design techniques so that they canfunction in their positions with only a minimum amount of start-up time.
Problem sets have been provided at the end of every chapter (except Chapter 2). The questionsare based on the material emphasized in the chapter, and most of them are calculational in nature.Process parameters have been provided, but these can easily be replaced by different sets that mightbe of special interest. Most of the problems have appeared on my homeworks or exams; others arequestions that I wrote, but never got around to using for one reason or another. I have tried toinclude a reasonable number of problems without getting excessive. Students that can follow thelevel of detail used in the book should not have many problems applying the material. SPICE sim-ulations add a lot to understanding, and should be performed whenever possible.
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Apologies
No effort was made to include a detailed list of references in the final version of the book. I initiallyset out to compile a comprehensive bibliography. However, after several graduate students per-formed on-line literature searches that yielded results far more complete than my list, I decided toinclude only a minimal set here. The references that were chosen are books and a few papers whosecontents are directly referenced in the writing. The task is thus left to the interested reader.
I have tried very hard to eliminate the errors in the book, but realize that many will slip through.After completing six readings of the final manuscript, I think that I caught most of the major errorsand hope that the remaining ones are relatively minor in nature. I apologize in advance for those Imissed.
Acknowledgments
Many thanks are due to Carl Harris of Kluwer who has shown amazing patience in waiting for thisproject to be completed. He never seemed to lose hope, even when I was quite ill (and crabby) forseveral months and unable to do much. Of course, those who know Carl will agree with me that heis a true gentlemen with exceptional qualities. And a real nice guy.
Dr. Roger P. Webb, Chair of the School of Electrical & Computer Engineering at Georgia Tech,has always supported my efforts in writing, and has my never ending thanks. Dr. William (Bill)Sayle, Vice-Chair for ECE Undergraduate Affairs, has also helped me more times than I can countduring the many years we have known each other. I am grateful to my colleagues that have takenthe time to discuss technical items with me. On the current project, this includes Dr. Glenn S.Smith, Dr. Andrew F. Peterson, and Dr. David R. Hertling in particular.
I am grateful to the reviewers that took the time to weed through early versions of the manu-script that were full of typos, missing figures, and incomplete sections to give me their comments.Feedback from the many students and former students that have suffered through the course havehelped shape the contents and presentation.
Finally, I would like to thank my wife Melba and my daughters Valerie and Christine that haveput up with dad sitting in front of the computer for hours and hours and hours. Their love has keptme going through this project and life in general!
John P. UyemuraSmyrna, Georgia
Table of Contents
Preface vii
Table of Contents xi
Chapter 1Physics and Modellingof MOSFETs 1
1.1 Basic MOSFET Characteristics 11.1.11.1.2
The MOS Threshold Voltage 3Body Bias 9
1.2 Current-Voltage Characteristics1.2.11.2.21.2.3
Square-Law Model 14Bulk-Charge ModelThe Role of Simple Device Models
1819
10
1.3
1.4
p-Channel MOSFETs
MOSFET Modelling
19
221.4.11.4.21.4.31.4.4
Drain-Source ResistanceMOSFET CapacitancesJunction Leakage CurrentsApplications to Circuit Design
2324
3537
1.5 Geometric Scaling Theory1.5.11.5.21.5.31.5.4
Full-Voltage ScalingConstant-Voltage ScalingSecond-Order Scaling EffectsApplications of Scaling Theory
3740
4344
44
1.6 Small-Device Effects1.6.11.6.21.6.3
1.7
1.81.8.1
45Threshold Voltage Modifications 45Mobility Variations 50Hot Electrons 52
Small Device Model 53
56MOSFET Modelling in SPICEBasic MOSFET Model 56
xii
1.9 Problems 58
1.10 References 59
Chapter 2Fabrication and Layoutof CMOS Integrated Circuits
2.12.1.12.1.22.1.32.1.4
Overview of Integrated Circuit Processing 61Oxides 61Polysilicon 63Doping and Ion Implantation 64Metal Layers 67
2.2
2.3
Photolithography
The Self-Aligned MOSFET2.3.1 The LDD MOSFET 72
68
71
2.4 Isolation and Wells2.4.12.4.22.4.3
LOCOSImproved LOCOS ProcessTrench Isolation
7477
78
The CMOS Process FlowSilicide Structures 83
73
782.52.5.12.5.2
2.62.6.12.6.22.6.32.6.4
2.72.7.1
2.82.8.1
2.9
2.10
Other Bulk Technologies 83
Mask Design and LayoutMOSFET Dimensions 88Design Rules 90Types of Design Rules 90General Comments 94
85
Latch-UpLatch up Prevention 97
Defects and Yield ConsiderationsOther Failure Modes
Chapter Summary
References
94
99
101
102
100
61
xiii
Chapter 3The CMOS Inverter:Analysis and Design
3.1 Basic Circuit and DC Operation 103
103
3.1.13.1.23.1.3
DC CharacteristicsNoise MarginsLayout Considerations
106109
112
3.23.2.13.2.23.2.33.2.43.2.53.2.63.2.73.2.8
Inverter Switching Characteristics 113Switching Intervals 114High-to-Low Time 115Low-to-High Time 117Maximum Switching Frequency 118Transient Effects on the VTC 119RC Modelling 120Propagation Delay 122Use of the Step-Input Waveform 124
125
134
3.3 Output Capacitance
3.4 Inverter Design3.4.13.4.2
DC DesignTransient Design
134137
3.5
3.6
3.7
3.8
Power Dissipation
Driving Large Capacitive Loads
Problems
References
140
144
152
154
Chapter 4Switching Propertiesof MOSFETs 155
4.14.1.14.1.24.1.34.1.44.1.5
nFET Pass TransistorsLogic 1 Input 156Logic 0 Input 158Switching Times 159Interpretation of the Results 159Layout 161
pMOS Transmission Characteristics4.24.2.1 Logic 0 Input 163
163
155
xiv
4.2.24.2.3
Logic 1 Input 164Switching Times 165
4.3
4.4
The Inverter Revisited
Series-Connected MOSFETs4.4.14.4.24.4.3
nFET Chains 167pFET Chains 168FETs Driving Other FETs 169
166
167
4.5 Transient Modelling4.5.14.5.2
The MOSFET RC Model 171Voltage Decay On an RC Ladder 173
4.6
4.7
MOSFET Switch Logic4.6.1 Multiplexor Networks 186
Problems
170
185
189
Chapter 5Static Logic Gates 193
5.1
5.2
Complex Logic Functions
CMOS NAND Gate5.2.15.2.25.2.35.2.4
DC Characteristics 197Transient Characteristics 201Design 205N-Input NAND 205
5.3 CMOS NOR Gate5.3.15.3.25.3.35.3.45.3.55.3.6
206
193
195
DC Transfer Characteristic 207Transient Times 210Design 213N-Input NOR 213Comparison of NAND and NOR Gates 213Layout 214
5.4 Complex Logic Gates5.4.15.4.25.4.3
215Examples of Complex Logic Gates 217Logic Design Techniques 219FET Sizing and Transient Design 221
5.5
5.6
5.7
5.8
Exclusive OR and Equivalence Gates 2245.5.1 Mirror Circuits 226
Adder Circuits 230
232
234
SR and D-type Latch
The CMOS SRAM Cell
xv
5.8.1 Receiver Latch 237
5.9 Schmitt Trigger Circuits
5.10
5.11
Tri-State Output Circuits
Pseudo-nMOS Logic Gates
238
243
2455.11.15.11.2
Complex Logic in Pseudo-nMOS 248Simplified XNOR Gate 251
5.12
5.13
Compact XOR and Equivalence Gates 253
256Problems
Chapter 6Transmission GateLogic Circuits 259
6.1 Basic Structure6.1.1 The TG as a Tri-State Controller 260
259
6.2 Electrical Analysis6.2.16.2.2
Logic 1 Transfer 263Logic 0 Transfer 264
6.3 RC Modelling
262
2666.3.16.3.26.3.36.3.4
TG Resistance Estimate 266Equivalent Resistance 267TG Capacitances 270Layout Considerations 271
6.4 TG-Based Switch Logic Gates 2716.4.16.4.26.4.36.4.4
Basic Multiplexors 272OR Gate 273XOR and Equivalence 274Transmission-gate Adders 276
6.5
6.6
6.7
6.8
6.9
TG Registers
The D-type Flip-Flop
nFET-Based Storage Circuits
Transmission Gates in Modern Design
Problems
276
278
281
283
284
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Chapter 7Dynamic LogicCircuit Concepts 287
7.1 Charge Leakage7.1.17.1.27.1.37.1.47.1.5
Junction Reverse Leakage Currents 289287
Charge Leakage Analysis 291Subthreshold Leakage 295pFET Leakage Characteristics 296Junction Leakage in TGs 297
7.2 Charge Sharing7.2.1 RC Equivalent 305
7.3 The Dynamic RAM Cell7.3.17.3.2
Cell Design and Array Architecture 314DRAM Overhead Circuits 319
7.4 Bootstrapping and Charge Pumps7.4.17.4.2
Physics of Bootstrapping 324Bootstrapped AND Circuit 326
7.5 Clocks and Synchronization7.5.17.5.27.5.3
Shift Register 327TGs as Control Elements 330Extension to General Clocked Systems 330
7.6
7.7
7.8
7.9
Clocked-CMOS
Clock Generation Circuits
Summary Comments
Problems
303
311
319
326
331
335
345
345
Chapter 8CMOS DynamicLogic Families 349
8.1
8.2
Basic Philosophy
Precharge/Evaluate Logic8.2.18.2.28.2.38.2.48.2.5
NAND3 Analysis 352Dynamic nMOS Gate Examples 358nMOS-nMOS Cascades 359Dynamic pMOS Logic 363nMOS-pMOS Alternating Cascades 367
349
350
xvii
8.3 Domino Logic 3698.3.18.3.28.3.38.3.48.3.5
Gate Characteristics 371Domino Cascades 374Charge Sharing and Charge Leakage Problems 377Sizing of MOSFET Chains 381High-Speed Cascades 389
8.4 Multiple-Output Domino Logic8.4.18.4.2
Charge Sharing and Charge Leakage 395Carry Look-Ahead (CLA) Adder 396
392
8.5
8.6
Self-Resetting Logic
NORA Logic8.6.1 NORA Series-Parallel Multiplier 414
404
408
8.7
8.8
8.9
Single-Phase Logic
An Overview of Dynamic Logic Families
Problems
8.10 References
416
430
431
433
Chapter 9CMOS DifferentialLogic Families 435
9.1
9.2
Dual Rail Logic
Cascode Voltage Switch Logic (CVSL)
435
4379.2.19.2.29.2.39.2.49.2.59.2.6
The pFET Latch 437CVSL Buffer/Inverter 438nFET Switching Network Design 440Switching Speeds 445Logic Chains in CVSL 445Dynamic CVSL 447
9.3 Variations on CVSL Logic9.3.19.3.29.3.3
Sample-Set Differential Logic (SSDL) 448ECDL 451DCSL 453
448
9.4 Complementary Pass-Transistor Logic (CPL) 4539.4.19.4.29.4.3
2-Input Arrays 4563-Input Arrays 459CPL Full-Adder 462
9.5 Dual Pass-Transistor Logic (DPL) 462
xviii
9.6
9.7
9.8
9.9
465
468
473
475
Summary of Differential Design Styles
Single/Dual Rail Conversion Circuits9.7.19.7.29.7.3
Single-to-Dual Rail Conversion 468Dual-to-Single Rail Conversion 468A Basic Current Source 472
Problems
References
Chapter 10Issues in Chip Design 477
10.1 On-Chip Interconnects 47710.1.110.1.210.1.310.1.4
Line Parasitics 477Modelling of the Interconnect Line 480Clock Distribution 490Coupling Capacitors and Crosstalk 492
10.2 Input and Output Circuits10.2.110.2.2
Input Protection Networks 498Output Circuits 504
498
10.3 Transmission Lines10.3.110.3.2
Ideal Transmission Line Analysis 510510
Reflections and Matching 513
10.4
10.5
Problems
References
521
523
Index 525
CMOS LOGIC CIRCUIT DESIGN
