CMOS ICs require design and manufacturing tests for eliminating design and manufacturing faults, respectively.
Faults in CMOS logic chips can have 2 principally different origins:
• The design does not fulfill the required specifications for thefunctionality of the CMOS logic circuit.
• During manufacturing a defect was introduced into a specificpart of the chip, which therefore doesn’t function as designed.
Design fault ! All chips will have an incorrect function !
Manufacturing fault ! Only the incorrectly manufactured chips have an incorrect function !
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Design or Functionality Tests
The quality of the design/functionality test for CMOS logic circuits depends largely on the experience of the designer.
There is no general theory for a correct and complete test of the functionality of a CMOS logic circuit design.
Advised procedure for assuring design correctness• Use a well-structured design method, which exploits- Hierarchical design partitioning- Module concept for all partitioned circuit parts- Regular structure of partitioned circuits and layouts- Locality of signals as far as possible
• Functional-, logic- and timing simulation as close as possibleto the way the fabricated chip will be used afterwards
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Manufacturing Test
For cost reasons all chip-manufacturing faults should be found by the test on the wafer level.
The purpose of the manufacturing test is to distinguish the good and the bad chips on the fabricated wafer.
Shorts between metal lines, resulting in stuck-at (unchange-able) input values of gates, are common fabrication faults.
Stuck-at-1 fault SA1 (Schematic for right example)
Layout example for the origin of SA1 and SA0 faults
Stuck-at-0 fault SA0 (Schematic for right example)
Connection ofinput and VDD
Connection ofinput and VSS
Manufacturingfaults
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“Shorted-Nodes” Fault Model
Unwanted connections between nodes of a transistor network are another common manufacturing fault.
Shorted-nodes in schematic (Schematic for right example)
Layout example for the origin of shorted-node faults
Short of internaland output node
Short between inputand VSS node(Corresponds to SA0)
Manufacturingfaults
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“Stuck-Open” Fault Model
Stuck-open faults can lead to a dependence of the output values of a gate on the history of the inputs.
Circuit without “stuck-open” fault Layout example for a
stuck-open fault
Disconnection ofone transistor fromthe output
Manufacturingfault
Circuit with “stuck-open” fault of layout
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Node Observability and Controllability
The aim of a good circuit design is to ensure good observability and controllability of all nodes.
Node controllability is a measure for the ease of
setting internal nodes to 1 or 0 from the input pins.
I1I2
In
O1O2
Om
CMOS logic circuit
internal node
controlla-bility
observa-bility
Node observability is a measure for the ease of
detecting internal-node-state changes at the output pins.
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Manufacturing-Test Concept with Stuck-At Model
For each internal circuit node 2 faulty test circuits (SA0 and SA1 fault) are constructed. Input test pattern with different outputs for correct and faulty circuits are then determined.
I1I2
In
O1O2
Om
CMOS logic circuitSA1
I1I2
In
O1O2
CMOS logic circuit
Om
SA0
faulty circuit with stuck-at-1 (SA1) fault
I1I2
In
O1O2
Om
CMOS logic circuit
correct circuit
node undertest
faulty circuit with stuck-at-0 (SA0) fault
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Fault Coverage with Stuck-At Model
A good manufacturing test achieves a high fault coverage with a small number k of test pattern.
Detected Stuck-At Faults with Test-Pattern Set
Total Number of Possible Stuck-At FaultsFault-coverage for
stuck-at faults
Set of test patternfor CMOS logic circuit
( )
=•••=
kn
2n
1n
k2
22
12
k1
21
11
k21
III
III
III
IIII
L
MOMM
L
L
=
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Faults Causing Changed Switching Delay
Faults causing increased switching delay may lead to severe performance degradation and are difficult to detect.
Layout with a manufacturing fault causing longer switching delay.
1 of 2 parallel n-MOSFETsdisconnected. Manufacturing
fault
Resulting circuit: 1 of 2 parallel n-MOSFETs disconnected.
No functional mistake, but longer tf than designed.
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Design Strategies which Simplify Testing
- Guidelines and Examples for Simplified Testing
- Structured Approaches to Improved Testability
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Guidelines for Achieving Simplified Testing
Design strategies which simplify testing provide methods for improving controllability and observability of internal nodes.
Design techniques for improving testability include:
• Partitioning of large sequential circuits.
• Adding test points to the circuit.
• Adding multiplexers for access to nodes,
which are difficult to test.
• Providing an easy state-reset function for
the circuit.
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Counter Design for Testability with Multiplexer
Controllability of internal counter nodes Q<7:0> is improved with an extra multiplexer for loading test data into the register.
Normal counter designwithout special measures for improved testability.
Counter design for testability with a multiplexer for loading test signals into the register.
multiplexer
loadfunction
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Accumulating Adder Design with Test Points
A test bus and test points are often used to make internal nodes of problematic circuits controllable and observable.
The testability of accumulating adders is
normally very bad.
normaloutput
normalinput
normalinput
test-outputpoints
test-inputpoints
Substantial improvement is possible with a test bus
and test points.
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Design Strategies which Simplify Testing
- Guidelines and Examples for Simplified Testing
- Structured Approaches to Improved Testability
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Principle of Scan-Based Test Techniques
A scan-based test makes the inputs of all logic blocks controllable and the outputs of all logic blocks observable.
additionalserial scan chain
normaldata path
Test Procedure: • Shift test patterns into all scan registers• Test all combinational logic blocks in parallel• Scan out all test results for analysis
All registers in a CMOS logic circuit are connected into a single serial chain
Idea:
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Principle of Self-Test Techniques
Self tests enhance register capabilities in CMOS circuits with functions for test-pattern generation and test-result analysis.
IdeaEnhance registers with test functions.
CombinantionalCircuit
Regn bit
Regm bit
n n m m
CombinantionalCircuit
Regn bit
+PRSG
Regm bit
+SA
n n m m
PRSG: Pseudo-Random-SequenceGenerator
SA:Signature Analyzer
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Built-In-Block-Observation (BILBO) Register
A BILBO register can carry out all necessary functions for a self-test of combinational logic blocks in CMOS circuits.
C0 C1
0 0011
Mode
101
Scan ModeReset
PRSG or SANormal parallel registers
1
0
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System-Level Testing
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Interconnect between chips
Serial interconnect for testing
I/O PAD and boundary-scan cell Serial
data inSerial data out
Chip
The scan-based methodology has been standardized as the “boundary-scan architecture” for system testing.
