Today's Goalskilyos.ee.bilkent.edu.tr/~eee314/downloads/l19.pdf · MOS transistors NMOS logic CMOS...

Digital Device DefinitionsPhysical BasicsDiodesBJTsRTL-DTL-TTLECLMOS transistorsNMOS logicCMOS logic

Transfer characteristicsPower dissipationDelayFan-outLogic designLogic familiesDynamic logic

LayoutBiCMOS logic

Transfer characteristicsPower dissipationDelayFan-out

InterfacingBistable circuits

● Cover Bistable circuits

● Chapter 5 of Eshraghian book is reading assignment for CMOS logic and CMOS flip-flops.

● Chapter 9 of Taub-Schilling book is reading assignment for CMOS and flip-flops.

Today's Goals



LayoutBiCMOS logic



HW-4

1) Derive TPLH2) 9.53) 9.10

Due May 12th Friday



LayoutBiCMOS logic



Quiz

Implement in NMOS, CMOS and DOMINO LOGIC

F=AB+C(A+D)

Describe the behaviour of the following circuit.



LayoutBiCMOS logic



Dynamic CMOS



LayoutBiCMOS logic



Dynamic CMOS



LayoutBiCMOS logic



Dynamic CMOS

Cascading problem!



LayoutBiCMOS logic



Dynamic CMOS: Domino

can be cascaded



LayoutBiCMOS logic



Dynamic CMOS

There are a number of dynamic CMOS logic families of varying complexity.



LayoutBiCMOS logic



CMOS MSI logic families

74HC(T) SeriesLG=3 microntox=60nmVdd=4.5 to 5.5 VDelay in driving 50pF is about 35 ns.Double bufferedInverter stages has the following widths

1st 2nd 3rd PMOS 9 35 90NMOS 3.5 15 35

1st stages of NAND/NOR etc scaled accordingly. Buffer stages the same.

This is good for a circuit at a few 10 Mhz.

Fan out when driving LSTTL is 10.



LayoutBiCMOS logic



CMOS bufferingT PHL=...

C L

K N [ V TN

12V DD−V TN

2

2

V DD−V TN

ln 2 V DD−V T

V DD]

T PHL=T PLH=t p=2CL

K V DD

Further simplify to T PHL=T PLH=t p=R C L

where

R= 2K V DD



LayoutBiCMOS logic



CMOS buffering

Assuming for K p=K n we must have W p=2 W n

C input=C1=3W L tox

Rn=R p=R1=2K V DD



LayoutBiCMOS logic



CMOS buffering

T d1=R1 C L

T d2=R1 N C1R1

NC L

T d3=R1 N C1R1

NN 2 C1

R1

N 2C L



LayoutBiCMOS logic



CMOS buffering

T d1=R1 C L

T d2=R1 N C1R1

NC L

T d3=R1 N C1R1

NN 2 C1

R1

N 2C L

Assume C L=100C1 and N=5

T d1=100 R1 C1

T d2=25 R1 C1

T d3=14 R1 C1



LayoutBiCMOS logic



Sequential logic

Dynamic memory elementsDynamic latchesDynamic flip-flopsDynamic RAM

Static memory elementsStatic latchesStatic flip-flopsStatic RAMROM, HD, CD, etc...

Static memory :: The data is retained even when the CLOCK is stopped.

Sometimes the following distinction is madeLatch: level triggered (enabled)Flip-flop: edge triggered



LayoutBiCMOS logic



CMOS Transmission Gate



LayoutBiCMOS logic



Clock requirements

Must decide LOGIC FAMILYDynamic logicStatic logic

Must decide clocking scheme2 phasePseudo 2 phase4 phasePseudo 4 phase

We must consider the following problems:

Clock skewClock overlap

More difficult with increased # of clocks



LayoutBiCMOS logic



Static Memory elements

What do we need to implement static memory elements?

Feedback

Using feedback, what sort of system do we want to create?

Bi-stable

True even for new approaches

Ferromagnetic RAMMillepedePhase transition RAMetc...



LayoutBiCMOS logic



Multivibrators

Multivibrators are two-state digital circuits that employ positive feedback

Monostable multivibratorBistable multivibratorAstable multivibrator

No other alternatives since digital.



LayoutBiCMOS logic



The basic latch

The classical approach based on positive feedback loopscan be drawn cross-coupled gates



LayoutBiCMOS logic



SR latch

S R Q Qnew0 0 Q Q1 0 Q 1 (set)0 1 Q 0 (reset)1 1 Q XX SR=11 not valid

Can have multiple S,R inputs



LayoutBiCMOS logic



SR latch

S' R' S R Q Qnew1 1 0 0 Q Q0 1 1 0 Q 1 (set)1 0 0 1 Q 0 (reset)0 0 1 1 Q XX

Can have multiple inputs

S' is my shorthand for Sbar



LayoutBiCMOS logic



Gated SR latch

Q does not change when enable is 0.



LayoutBiCMOS logic



Gated SR latch with async control

Preset Clear Operation0 0 normal SR1 0 Q=10 1 Q=01 1 XX

Problem when Enable=1 R=1, S=0 Q=0

Preset=1, Clear=0 Q=1So asynch OK, only when Enable=0

S R Q Qnew0 0 Q Q1 0 Q 1 (set)0 1 Q 0 (reset)1 1 Q XX



LayoutBiCMOS logic






Problem when Enable=1 R=1, S=0 Q=0

Preset=1, Clear=0 Q=1So asynch OK, only when Enable=0



LayoutBiCMOS logic








LayoutBiCMOS logic



Falling clock trig SR MS flip-flop

Async inputs must control both master and slave



LayoutBiCMOS logic



JK Latch

J K Q Qnew0 0 Q Q1 0 Q 1 (set)0 1 Q 0 (reset)1 1 Q Qbar



LayoutBiCMOS logic



JK Master Slave



LayoutBiCMOS logic



D flip flop



LayoutBiCMOS logic



D Flip-Flop

Figure 9.13-2 from TS scanned



LayoutBiCMOS logic



CMOS implementation



LayoutBiCMOS logic



Alternative 2 phase D latch



LayoutBiCMOS logic



Alternative 2 phase MS D FF



LayoutBiCMOS logic



Alt. 2 phase MS D FF with SR



LayoutBiCMOS logic



Pseudo 2 phase latch



LayoutBiCMOS logic






LayoutBiCMOS logic




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Today's Goalskilyos.ee.bilkent.edu.tr/~eee314/downloads/l19.pdf · MOS transistors NMOS logic CMOS...

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