CMP annual meeting, January 23rd, 2014 - mycmp.fr · been designed and fabricated...

J.P.Nozières, G.Prenat, B.Dieny and G.Di PendinaSpintec, UMR-8191, CEA-INAC/CNRS/UJF-Grenoble1/Grenoble-INP, Grenoble, France

CMP annual meeting, January 23rd, 2014

J.P. Nozières CMP annual meeting, January 23rd, 2014

ReRAM

Vwr1~0.9V@5nsVwr0~-0.9V Vread~0.3VVwr1~0.9V@5nsVwr0~-0.9V Vread~0.3VVwr1~0.9V@5nsVwr0~-0.9V Vread~0.3V


Power consumption is strongly increasing,with a large contribution of leakage

Existing Solutions:Technology level (SOI, HiK...)Circuits level (dynamic logic...)System level (Multiple Threshold CMOS, Variable Threshold CMOS, Power Gating, Clock Gating…)

T. Kawahara, in Design and Test of Computers, Volume 28, Issue 1, 2010

Qualities of MTJs in terms of non-volatility, speed, power consumptionand cyclability allows to ease these techniques « Normally-off electronics »



- MTJ used as a variable resistance- Resistance compatible with CMOS (~ kΩ)

- « End-of-back-end » process- No trade-off with logic process

-Easy / cheap to embedd - 0 to 3 add-masks- No HV required

- Low-T BE process (T<350°C)

Magneticelement level

CMOS logic level

MRAM IS AN “ABOVE-IC” PROCESS


Intrinsically non-volatileHigh writing/reading speed (≈ns)Endurance (>1013 )Writing voltage compatible with CMOSRadiation Hard

Ferro 1

Ferro 2

Insulator

↑↑

↑↑↑↓ −=R

RRTMR

H

R


Bit line

Word line

Transistor ON Transistor OFF

0 100 200 300 400 500 600 700 800 900 100010

-6

10-5

10-4

10-3

10-2

10-1

100

Resistance

Nor

mal

ised

Cou

nt

0 100 200 300 400 500 600 700 800 900 100010

-6

10-5

10-4

10-3

10-2

10-1

100

10-1

100

Resistance

Nor

mal

ised

Cou

nt

Rmin Rmax

>25σ


Replacement of DRAM or Cache 3 or 2 by STT MRAM without changing theoverall architecture of electronic circuits

Strong decrease in static power consumption (suppressed leakage inDRAM, power gating)No more need for DRAM refreshment

Hybrid cache proposed by toshiba for ultra-low power processors

HDD SSD

File Cache

DRAM

Cache 2

Cache 1

Registers

ALUCPUFF

100ns

ms

30ns

3ns

1ns

2GHz-500ps

HDD SSD

MRAM

Cache 1

Registers

ALUCPUFF

Présentateur

Commentaires de présentation

Remplacement des blocs memoires dans les hauts niveaux de hierarchie (suffisamment lent) pour que le 1-to-1 replacement fonctionne L2, L3 cache On peut alors faire du power gating, sauvegarder les contextes, .. On dominue le leakage


Non-volatily can gates (Flip-flop, ALU…)

HDD SSD

File Cache

DRAM

Cache 2

Cache 1

Registers

ALUCPUFF

100ns

ms

30ns

3ns

1ns

2GHz-500ps

HDD SSD

MRAM

NV-ALUNV-CPUNV-FF

T.Kawahara, IEEE Design and test of computers, 52, Janv/Feb 2011)

introduction of Non-Volatility in the logic part / memory-in-logicFurther decrease in power consumptionIncreased resilience (roll-back mechanisms…)Ultra-fast “on-fly”reconfigurabilityNew functionalities


Two logic differential data (magnetic and electronic parts)Latch/Flip-Flop can operate as a standard CMOS (nominal speed)Possibility to backup the electric content into the magnetic partRestoration of data in a few 100ps (during AZ phase, SRAM acts like a senseamplifier and copies the content of the MTJs in the latch)

A set of NV FF has been designed, characterized by simulation andintegrated as standard cells in a digital design flow

W. Zhao et al.,in International Solide-State and Integrated Circuit Technology,

Shanghai, China, 2006.

N.Sakimura et al., IEEE-CICC, 2008

S. Kang et al., IEEE-NVMW, 2010

W. C. Black Jr. and B. Das, Journal of Applied Physics,87(9) :6674, May 2000.

Présentateur


NV-SRAM latch/flipflop= SRAM + MTJ = vitesse de la SRAM fonctionnement normal) + a tout moment on peut sauvegarde une donnee ou un contrexte (contenu) dans la SRAM et la restaurer. Il faut de la circuitrie pour piloter l MRAM (additional floor space) mais toujours plus interessant que de passer par des bus entre la moire off chip et le circuit logique Pourrait servir en cache L1 (sauvegarde de temps en temps, pas a chaque cycle)


Circuit whose functionality can be changed keeping the same hardware

Composed of elementary logic functions, called LUT (Look Up Tables)programmable by an operating code stored in a configuration memory

Radiation hardness in traditional SRAM-based FPGAs :

Duplicating circuits (Triple Modular Redundancy, TMR)

Refreshing the SRAM content (“scrubbing”) to avoid errors accumulation

Présentateur


It is traditionally used for low-volume production or prototyping (no dedicated masks set) Today, used for new applications like dynamically reconfigurable computing (changing the configuration in operation to optimize the performance) LUT presented is a 3-input LUT (8 bit configuration memory), composed of a MUX (multiplexer) and a 8-bits memory When the selection inputs of the MUX (inputs of the LUT) e0, e1 and e2 are “000”, the content of the first memory is routed to the output : the output is “0” The output is “1” only when the inputs are “111” => “and” logic gate (a “or” logic gate would be programmed by the operating code “01111111”) LUTs connected together by an interprogrammable routing network (routing configuration memory)


Configuration memory based on DRAMLocal MRAM (intrinsically immune toradiations) acts as a reference todetect/correct errorsPeriodic refresh of DRAM using MRAMcontent (scrubbing)

Advantages:High density (DRAM)No redundancyLow power (non-volatile, powergating)Shadowed reconfiguration

O.Gonçalves thesis

Same approach for interconnections : a full tile was designed

Présentateur


The idea here is to use a MRAM memory to store locally the configuration. Since the MRAM is immune to radiations, the content of the memory cell can be used as a reference and avoids TMR The configuration memory is a DRAM: DRAM is not used classically for FPGAs, because the connections memory are always active and DRAM needs refreshing (standby power consumption) Since, in hardened FPGAs, the configuration has anyway to be reloaded, the scrubbing technique is used to refresh the DRAM The advantages are a high density, since DRAM and MRAM are dense, and MRAM avoids redondancy Due to the non-volatility, it is possible to cut off the power supply of unused blocks => gain in power consumption It is also possible to make shadowed reconfiguration (reconfigure the FPGA in operation, by writing only the MRAM) The “MRAM” part is composed of differential pairs of MTJs, with selection transistors (to select the cell to be written or read) The selection transistor are synchronised with selections transistor of the “DRAM” to refresh sequentially the DRAM cells from the corresponding MRAM cells The reading part is based on a latch (approach very close to the Black and Das one)


A 2-inputs LUT manufactured using the hybrid TowerJazz/Crocus- process130 nm CMOSMagnetic materials in Back End above CMOSTested on a digital tester at Spintec

All possible 2-inputs functions successively programmed in the MRAMand transferred to the DRAMAll the combinations of inputs tested and the corresponding outputsuccessfully checked

Présentateur


We had the opportunity to implement the LUT structure in a run of CROCUS technology, in an hybrid CMOS/Magnetic TowerJazz/Crocus technology The circuit implemented is a 2-inputs LUT


MRAM has a unique combined set of qualities, allowing to introduce Non-Volatility at any level of the memory hierarchy

Reduce power consumptionImprove reliability (endurance, rad-hard, …)Add new functionalities

A full Process Design Kit has been developed by CMP and Spintec for theCrocus/TowerJazz 130nm technology, allowing to offer MPW service

A silicon demonstrator of a radiation hardened LUT for space applications hasbeen designed and fabricated atCrocus/TowerJazz

The circuit has been tested and is fully functional, proving the viability of thistechnology for logic applications

Présentateur


We propose a new architecture of radiation hardnened LUT architecture for space applications Based on DRAM for the configuration memory, refreshed by the content of a local MRAM memory Very dense (DRAM, MRAM and no redondancy) Low power (non volatility => power gating) Performance (density => speed, reconfiguration capabilities) For space or aerospace applications

Date post:	16-Jul-2018
Category:	Documents
Upload:	phamquynh
View:	213 times
Download:	0 times

CMP annual meeting, January 23rd, 2014 - mycmp.fr · been designed and fabricated...

Documents