April 30, 2014 1
700V Power Management Platform with record logic density :
SOC power solutions are finally enabled for 700V….
April 30, 2014
Dr. Shye Shapira Director of Global Power Management
Research and Development TowerJazz
April 30, 2014 2
Total 8˝ Equivalent Capacity of ≈1.7M WPY
April 30, 2014 3
TS18/35PM Technology Applications POE, DC/DC, LED Backlight TS35PM (5V CMOS)
PMIC, Digital Controlled Power TS18PM (1.8/5V CMOS)
High Power/Motor Drive, POE Shallow Isolated TS18/35PM
AMOLED, Audio Deep Isolated TS18/35PM
• Scalable 7 to 60V Vds with low Rsp • Embedded no mask-adder NVM • Thick Power Metal (Cu /Al) • 60V Vgs, 80V Vds options
• Fully isolated devices with buried layer • Up to 80V operation with low Rsp • Noise isolation for >2 Amp applications
• 1.8V CMOS for 125 kgates/mm2
• Same HV modules as TS35PM • Multi-Fab sourcing
• Fully isolated devices with deeper isolation • Allows positive/negative bias
Modular power management platform with best-in class performance and design enablement (models, PDK, IP and Design Services)
April 30, 2014 4
Ultra High Voltage (UHV) Technology Applications
LED lighting AC to DC up to 700V Industrial LED lighting for street lighting and incandescent bulb replacement
AC to DC offline converters
Integrated Power
Integrated control circuits for MOSFET / IGBT power devices in white appliances
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Lighting System Topologies Single stage (a) and more advanced Multiple (b) stage From (Branas et al IEEE solid state lighting magazine Dec 2013 )
Advanced lighting Solutions require more than one voltage stage
700V ac to Midvoltage
Midvoltage to LED
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Digital Power Control
• Better efficiency and control of color and power and can be achieved by Digital Power Control.
• Advanced CMOS technology nodes are Required
MultiChip Solution (high density CMOS; Power) See
• Tetervenoks, O. “ Choice of power and control coupling elements for dimmable led driver for smart lighting networks” Industrial Electronics Society, IECON 2013 - 39th Annual Conference of the IEEE 2013 , Page(s): 5940 - 5944
• Ice C, “EDN Network,” Bringing LED Control Into the Digital Age, 11 September 2012, pp. 1-6.
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Current Topologies Solutions are
• Multichip
At times
• Multimodule
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“Choice of power and control coupling elements for dimmable led driver for smart lighting networks” Tetervenoks, O. IECON 2013 - 39th Annual Conference of the IEEE 2013
Soc lighting chip
Digital PWM control chip
Mid voltage DC DC chip
High Voltage AC to midvoltage DC
Can the right technology enable all electronics on one Chip?
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Shallow Trench Isolation
8
Introduced since 0.25 micrometer technology nodes to allow smaller separation between NMOS and CMOS
contact.
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Isolation Option
Base Shallow Deep SOI *
CMOS 1.8 V (TS18PM) Yes Yes Yes Yes 125Kgate/mm2
5 V (TS18PM/TS35PM) Yes Yes Yes Yes 35Kgate/mm2
HV Options NLDMOS Vds (5V Vgs) 12, 20-40 12, 20-60, 80 12, 20-40 Up to 200V Operating
PLDMOS Vds (5V Vgs) 12, 20-40 12, 20-60 12, 20-40 Up to 200V Operating
Epi and buried layer No Yes Yes No
Drain Isolated No No Yes Yes
Passives MIM Cap 1, 1.7, 3.4 1, 1.7, 3.4 1, 1.7, 3.4 1, 1.7, 3.4 fF/um2
Poly Resistor 1k or 2k 1k or 2k 1k or 2k 1k or 2k Ohm/sq
Other Zener Diode (5.5v) Option Option Option Option
Schottky Diode Yes Yes Yes Yes
VNPN, SVPNP Yes Yes Yes Yes
Embedded NVM 64,4k, 16k 64,4k, 16k 64,4k, 16k 64,4k, 16k Bits
Metal Layers 3 3 to 5 3 to 5 3 to 5
Top Metal Al options 0.9, 2, 3 0.9, 2, 3 0.9, 2, 3 0.9, 2, 3 um
Top Metal Cu option 3.3 3.3 3.3 3.3 um
MidVoltage + CMOS platform: TS18/35PM Features
* Coming soon
April 30, 2014 10
TS100PM LS TS100PM HS
CMOS 5 V, 1.8V Yes, No Yes, No
Logic density
HV Options LDMOS Vfloat (5V Vgs) No Up to 650V
LDMOS Vfloat (26V Vgs) No Up to 650V
JFET Vds 700V No
Ldmos BVsd 750V 650V (Level
Shifter)
Passives MIM Cap No No
Poly Resistor Yes Yes
Other Zener Diode (5.5v) Yes Yes
VNPN, SVPNP Yes VNPN only
Embedded NVM No No
Metal Layers 2 2
Metal Material Al Al
Top Metal Al 1.2 1.2
High Voltage 1 Micron Based Platform: TS100PM LS/HS
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Platform Integration Approach
TS 18 35 PM
TS 100 PM
Integration of Processes
Enhancement “Children are better than their parents”
Ts 18 35 UHV
Digital PWM control chip
Mid voltage DC DC chip
High Voltage AC to midvoltage DC
Soc lighting chip
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CMOS and Power Technologies: Features and Physical Dimensions
Item Dimensions (Micrometers)
Typical Technology Node
Logic Density Gates/mm^2
Non Volatile Memory
Comment
700 V Device Source Drain contact pitch
50-65 1 -0.5
Micron
Fuse ( 1 to several bits)
Silicon Breakdown Field Dictates L > ~50 Microns for all technologies
Gate length 1 mic Cmos
1 1 4 Fuse
Gate length 0.5 mic 5V Cmos
0.5 0.5 8 Fuse
Gate length 0.35 mic 3.3V Cmos 0.35 0.35 15
Fuse / High mask count nvm
Best Available gate density for 700V in market
Hybrid 0.18 Backend of line ; 5VGate length (TS35PM)
0.5 0.5 >>15
Yflash (64 to 64Kb), fuse
New Highest gate density with single gate integrated 700V switch available enabling 700V SOC
New 700V platform TS18/35 UHV
0.18,5, 55(1.8V ,5V, HV ldmos)
0.18 >>>15
Yflash (64 to 64Kb), fuse
New Highest gate density with integrated 700V switch available enabling 700V SOC
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Maximum Logic Gate Density Integrated with 700V
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Requirements : Fully Integrated offline Lighting Platform
• High performance High Voltage Device ( Low rdson Scalable Voltage)
• High Performance startup devices (JFETs)
• High Density NVM
• High Density Logic
• High quality LV Analog Device Modeling
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Continuous Voltage Scaling
Why: Different applications require slightly higher voltage margins. Moving to the next discrete voltage bears a high Rdson penalty .
Solution : Continuous Voltage Scaled Platform •Rdson penalty for small increase in voltage is minimized. •Scalable Voltage devices are accompanied by scalable voltage ESD protection devices. •Automated pcells allow simple control and predictability of Rdson in continuous manner. •Requires high end modeling solutions
BV [V] R
dSp
[m
Oh
m m
m^2
]
Two Device Offering 1 ,2 Continuous Voltage
Device Offering
1
2
Rdson reduction by continuous offering vs Two Device offering
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Scalable Voltage and RdsOn of HV Devices in 700V Devices
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Digital PM - Embedded Low Mask Count NVM
• “Y-Flash” – TowerJazz unique Non-Volatile Memory solution
• Two Terminal Device based on nmos transistor allows
Small cell size
• 64b -64Kb module size
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Y-cell I-V in different directions
1.E-14
1.E-12
1.E-10
1.E-08
1.E-06
1.E-04
0 0.5 1 1.5 2 2.5 3
Drain or Source voltage, V
Dra
in c
urr
en
t, A
Forward
Reverse
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700V NLDMOS
Double Resurf: Isolation layer Pinched off on both sides
Layout Examples: 700v Ldmos Device and Building Blocks
April 30, 2014 18
0
0.05
0.1
0.15
0.2
0 100 200 300 400 500 600 700 800
ID [
A]
VD [V]
VG=2V
VG=3V
VG=4V
700v LDMOS Pulsed Safe Operating Area
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30V LDMOS
0.0E+00
2.0E-03
4.0E-03
6.0E-03
8.0E-03
1.0E-02
1.2E-02
1.4E-02
0 5 10 15 20 25 30 35 40
Id [
A]
Vds [V]
Id Vs Vds @ Vgs=0 to 5V
Vgs=1V
Vgs=2V
Vgs=3V
Vgs=4V
Vgs=5V
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BV=800V
High voltage Jfet for Startup Circuit
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TS100PM LS TS100PM HS TS35UHV LS* TS35UHV HS** Comment
CMOS 5 V, 1.8V Yes, No Yes, No Yes, Yes Yes, Yes
Logic density 35, 125 35, 125 kgates/mm2
HV Options LDMOS Vfloat (5V Vgs) No Up to 650V No Up to 650V Operating
LDMOS Vfloat (26V Vgs) No Up to 650V No Up to 650V Operating
JFET Vds 700V No 700V 700V Operating
Ldmos BVsd 750V 650V (Level
Shifter) 750V
650V (Level Shifter)
Typical
Passives MIM Cap No No 1, 1.7, 3.4 1, 1.7, 3.4 fF/um2
Poly Resistor Yes Yes 1k, 2k 1k, 2k Ohm/sq
Other Zener Diode (5.5v) Yes Yes Yes Yes
VNPN, SVPNP Yes VNPN only Yes Yes
Embedded NVM No No 64 64 Bits
Metal Layers 2 2 3 3
Metal Material Al Al Al Al
Top Metal Al 1.2 1.2 2, 3 2, 3 um
TS18/35UHV: Lighting SOC Platform Features
* PDK available in Q2 2014 ** Coming soon
April 30, 2014 22
