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Lecture16

Datapath fortheMIPSArchitecture

(Asingle-cycle implementation)

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Registers

Register #

Data

Register #

Data

memory

Address

Data

Register #

PC Instruction ALU

Instruction

memory

Address

Figure5.1:AbstractviewoftheMIPSdatapath

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State

elementCombinational logic

ClockMethodology

Whatcanwedosothatwecanread

thestateandwritebacktoitinthe

sameclockcycle?

CLOCK

READ WRITE

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IncrementingtheProgramCounter

PC

Instructionmemory

Read

address

Instruction

4

Add

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InstructionRegisters

Writeregister

Readdata 1

Readdata 2

Readregister 1

Readregister 2

Writedata

ALUresult

ALU

Zero

RegWrite

ALU operation3

Figure5.7:Datapath forR-typeinstructions

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Instruction

16 32

RegistersWriteregister

Readdata 1

Readdata 2

Readregister 1

Readregister 2

Datamemory

Writedata

Readdata

Writedata

Sign

extend

ALUresult

Zero

ALU

Address

MemRead

MemWrite

RegWrite

ALU operation3

Figure5.9:Load/storedatapath

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16 32Sign

extend

ZeroALU

Sum

Shiftleft 2

To branch

control logic

Branch target

PC + 4 from instruction datapath

Instruction

Add

RegistersWriteregister

Readdata 1

Readdata 2

Readregister 1

Readregister 2

Writedata

RegWrite

ALU operation3

Figure5.10:Branchdatapath

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PC

Instructionmemory

Readaddress

Instruction

16 32

Registers

Writeregister

Writedata

Readdata 1

Readdata 2

Readregister 1

Readregister 2

Sign

extend

ALUresult

Zero

Datamemory

Address

Writedata

Readdata

Mux

4

Add

Mux

ALU

RegWrite

ALU operation3

MemRead

MemWrite

ALUSrcMemtoReg

Figure5.12:Datapath withinstructionfetch.

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PC

Instructionmemory

Readaddress

Instruction

16 32

Add ALUresult

Mux

Registers

Writeregister

Writedata

Readdata 1

Readdata 2

Readregister 1

Readregister 2

Shiftleft 2

4

Mux

ALU operation3

RegWrite

MemRead

MemWrite

PCSrc

ALUSrc

MemtoReg

ALUresult

ZeroALU

Datamemory

Address

Writedata

Readdata M

ux

Signextend

Add

Figure5.13:Singlecycledatapath forbasicMIPSinstructions

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111

001

000

110

010

110

010010

ALU

control

input

addXXXXXXloadword00lwaddXXXXXXstoreword00sw

or100101OR10R-type

subtract100010subtract10R-type

subtractXXXXXXbrancheq01beq

setonless

than

101010slt10R-type

and100100AND10R-type

add100000add10R-type

ALUactionfunctoperationALU

Op

opcode

Figure5.14:ALUcontrolbitsforR-typeinstructions

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OperationFunct fieldALU

op2

ALU

op1

1110101XXX1

0011010XXX1

0011010XXX1

1100100XXX1

110XXXXXX1X

0

0

X

0

0

X

1

0

X

0

0

X

X

X

X

000XX1

010XX1

010X00

Figure5.15:TruthtableforthethreeALUcontrolbits

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ReviewofInstructionFormats

OP rs rt rd shamt funct

6bits 5bits 5bits 5bits 5bits 6bits

R-format:

OP rs rt address/immediate

6bits 5bits 5bits 16bits

I-format:

OP targetaddress

6bits 26bits

J-format:

Lookingatthedatapath,youllseemanycontrollinesthathavebeenleftdanglinguptonow.Weneedtofigureouthowtoset

thesevalues;theinformationforthiswillcomefrominstructions.

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MemtoReg

MemRead

MemWrite

ALUOp

ALUSrc

RegDst

PC

Instructionmemory

Readaddress

Instruction[310]

Instruction [2016]

Instruction [2521]

Add

Instruction [50]

RegWrite

4

16 32Instruction [150]

0

Registers

Writeregister

Writedata

Writedata

Readdata 1

Readdata 2

Readregister 1

Readregister 2

Signextend

ALUresult

Zero

Datamemory

Address Readdata

Mux

1

0

Mux

1

0

Mux

1

0

Mux

1

Instruction [1511]

ALUcontrol

Shiftleft 2

PCSrc

ALU

AddALU

result

Figure5.17:Controllinesinthedatapath

DesigningtheControlUnit

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PC

Instructionmemory

Readaddress

Instruction

Instruction [20 16]

Instruction [25 21]

Add

Instruction [5 0 ]

MemtoReg

ALUOp

MemWrite

RegWrite

MemRead

Branch

RegDst

ALUSrc

Instruction [31 26]

4

16 32

Instruction [15 0]

0

0Mux

0

1

Control

AddALU

result

Mux

0

1

RegistersWriteregister

Writedata

Readdata 1

Readdata 2

Readregister 1

Readregister 2

Signextend

Mux

1

ALUresult

Zero

PCSrc

Datamemory

Writedata

Readdata

Mux

1

Instruction [15 11]

ALUcontrol

Shiftleft 2

ALU

Address

Figure5.19:Addingthecontrolunittothedatapath

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PC

Instructionmemory

Readaddress

Instruction

Add

MemtoReg

ALUOp

MemWrite

RegWrite

MemRead

Branch

RegDst

ALUSrc

4

16 32

0

0Mux

0

1

Control

AddALU

result

Mux

0

1

RegistersWriteregister

Writedata

Readdata 1

Readdata 2

Readregister 1

Readregister 2

Signextend

Shiftleft 2

Mux

1

ALUresult

Zero

Datamemory

Writedata

Readdata

Mux

1

ALUcontrol

ALUAddress

Figure5.21:ExecutinganR-typeinstruction fetchfrominstruction

memoryandincrementthePC.

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PC

Instructionmemory

Readaddress

Instruction

Add

MemtoReg

ALUOp

MemWrite

RegWrite

MemRead

Branch

RegDst

ALUSrc

4

16 32

0

0Mux

0

1

Control

Add ALUresult

Mux

0

1

RegistersWriteregister

Writedata

Readdata 1

Readdata 2

Readregister 1

Readregister 2

Signextend

Shiftleft 2

Mux

1

ALUresult

Zero

Datamemory

Writedata

Readdata

Mux

1

ALUcontrol

ALU

Address

Figure5.22:Readsourceregistersfromregisterfile.

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PC

Instructionmemory

Readaddress

Instruction

Instruction [20 16]

Instruction [25 21]

Add

Instruction [5 0]

MemtoReg

ALUOp

MemWrite

RegWrite

MemRead

Branch

RegDst

ALUSrc

Instruction [31 26]

4

16 32Instruction [15 0]

0

0Mux

0

1

ALUcontrol

Control

Add ALUresult

Mux

0

1

RegistersWriteregister

Writedata

Readdata 1

Readdata 2

Readregister 1

Readregister 2

Signextend

Mux

1

ALUresult

Zero

Datamemory

ReaddataAddress

Writedata

Mux

1

Instruction [15 11]

ALU

Shiftleft 2

Figure5.23:ALUperformsoperationonregistercontents.

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PC

Instructionmemory

Readaddress

Instruction

Instruction [20 16]

Instruction [25 21]

Add

Instruction [5 0]

MemtoReg

ALUOp

MemWrite

RegWrite

MemRead

Branch

RegDst

ALUSrc

Instruction [31 26]

4

16 32Instruction [15 0]

0

0Mux

0

1

ALUcontrol

Control

Shiftleft 2

AddALU

result

Mux

0

1

RegistersWriteregister

Writedata

Readdata 1

Readdata 2

Readregister 1

Readregister 2

Signextend

Mux

1

ALUresult

Zero

Datamemory

Writedata

Readdata

Mux

1

Instruction [15 11]

ALU

Address

Figure5.24:Finally,writeresulttodestinationregisterand

incrementthePC.

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DesigningtheControlUnit

Thesettingofcontrollinesiscompletelydeterminedby

theinstructionopcode. Question: Howareopcodes determined?

0

1

0

Op0Op1Op2Op3Op4

0

1

0

Op5

1000beq

0001sw

0000lw

Opcode inbinaryInstruction

Usinganopcode asinput,youcandefineafunctionthatproduces

controlsignalsasoutputs(RegDst,ALUSrc,MemtoReg,etc).

Thecontrolunitinthiscaseissimplyacombinationalcircuit.

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PerformanceofSingle-CycleMachines

Thegoal: haveeveryinstructionexecuted

inasingleclockcycle.

Thedrawback: theclockperiodischosen

toallowfortheexecutionofthelongest

instruction.

Variableclocks:isthisasolution?

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AMulticycle Machine

Goal: breakuptheexecutionofaninstructionintosteps,

whereeachsteptakesoneclockcycletocomplete.

PC

Memory

Address

Instructionor data

Data

Instructionregister

Registers

Register #

Data

Register #

Register #

ALU

Memorydata

register

A

B

ALUOut

Maindifferences: onememoryunitfordataandcode,asingleALU,extraregisterstoholddatathatspassedfromoneclock

cycletothenext.

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Figure5.33:Completedatapath foramulticycle

machine

Shiftleft 2

PC

Mux

0

1

RegistersWriteregister

Writedata

Readdata 1

Readdata 2

Readregister 1

Readregister 2

Instruction

Mux

0

1

Mux

0

1

4

Instruction

Signextend

3216

Instruction

Instruction

Instruction

Instructionregister

ALUcontrol

ALUresult

ALU

Zero

Memorydata

register

A

B

IorD

MemRead

MemWrite

MemtoReg

PCWriteCond

PCWrite

IRWrite

ALUOp

ALUSrcB

ALUSrcA

RegDst

PCSource

RegWrite

Control

Outputs

Op

Instruction[31-26]

! " #

Mux

0

2

Jumpaddress [31-0]

$ ! " #

$

26 28Shiftleft 2

PC [31-28]

1

1 Mux

0

3

2

Mux

0

1ALUOut

Memory

MemData

Writedata

Address