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4.1

Lecture4

MoreCombinationalCircuits,

MemoryElementsand

Clocks

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4.2

XNORfromNANDs andNORs

A B BA

BAABBA +=

(i) FromNANDs:startwithSOPform

andapplyinvolution.

(ii) FromNORs:getthe0-rows,writethe

maxterms andtaketheproduct,then

applyinvolution:

))(( BABABAF ++==

)()( BABAFF +++==

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4.3

MultiplexerThinkofitasamulti-wayswitchoraselector.

0I

1I

Out

SELECT

2-to-1MUX

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4.4

Multiplexer

4-to-1MUX

Question: Howmanybitsare

neededtoselectwhichinputwillbe

shownattheoutput?

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4.5

GenericDesignforaMultiplexer

Question: ForanN-to-1MUX,

whatkindofdecoderwillwe

need?

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4.6

Exercise:DesignaDemultiplexer

0O

In

SELECT

1O

2O

nO

1-to-NDEMUX

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4.7

ProgrammableLogicArray(PLA)

AND gates

OR gates

Product terms

Outputs

Inputs

Usedtoimplementgeneric

functions

directlyfromtheSOP

canonicalform.

Theyarecalled

programmablebecausethey

haveafixedstructureandthe

designeronlyhastodefine

connectionsinorderto

implementafunction.

nnF 22:

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4.8

InsideaPLA

A

B

C

Inputs

D

E

F

Outputs

AND plane

OR plane

EachcolumnintheAND

planecorrespondstoa

minterm.Eachrowinthe

ORplanecorrespondsto

asum ofminterms.

)()()( CABCBABCAE++=

Thereisanelectronicallyprogrammablesimilarcomponent

calledPAL(programmablearraylogic).

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4.9

MemoryElements

Nothingweveseensofarhastheabilityto

storedata,notevenasinglebit.

Whenyouremove(orchange)anyinput,

afterapropagationdelay,theoutput

correspondinglychanges.

Aswewellknow,acomputerneedsto

rememberpiecesofinformation

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4.10

TheS-RLatch

not

allowed

nochange

S R Q

QQS

QQR

=+=

=+=

00

00

10

011

==

==+=

QS

QQR

11

010

==

==+=

QS

QQR

Note: statechangeshappenwhentheyhappen.

Youcantcontrolwhen.

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4.11

Clocks

Clock period Rising edge

Falling edge

Aclocksignal isasquarewaveform(usuallysymmetrical)

definedbyaperiodorcycletime.Itisareferencesignalthat

allowsonetomeasurethepassageoftime.

Theclockrate orclockfrequency istheinverseofthecycle

timeandismeasuredinHertz:

secondperntimesHertz =n

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4.12

ClockEdges

Clock period Rising edge

Falling edge

Ourcircuitswillallbeedge-triggered,thatis,thingshappen

onlywhenclockvalueschangefor0-to-1or1-to-0.

Notethattheclockperiodmustbechosensothatitislong

enoughforallsignalsinacombinationalcircuittostabilize.

Definition: setuptime istheminimumtimethattheinputs

mustbevalidbeforetheclockedge.

Definition: holdtime istheminimumtimeduringwhichtheinputsmuststayvalidaftertheclockedge.

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4.13

TheDFlip-Flop

D

C

Q

Q

Whentheclocklinetransitionsfrom0to1,thevaluepresentedat

theD lineisreadintothecomponentandbecomesthestateofthe

flip-flop.

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4.14

Register:MorethanaSingleBit

D

C

Q D

C

Q D

C

Q D

C

Q

clock

nR 1nR 2nR 0R

nD 1nD 2nD 0D

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4.15

RegisterFile:MorethanaSingleRegister

Read registernumber 1 Read

data 1

Readdata 2

Read registernumber 2

Register fileWriteregister

Writedata Write

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4.16

InsideaRegisterFile:ReadPorts

M

ux

Register 0

Register 1

Register n 1

Register n

M

ux

Read data 1

Read data 2

Read register

number 1

Read register

number 2

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4.17

InsideaRegisterFile:WritePorts

n-to-1

decoder

Register 0

Register 1

Register n 1

C

C

D

D

Register n

C

C

D

D

Register number

Write

Register data

0

1

n 1

n