Copy of Vlsi Manual 1

7/28/2019 Copy of Vlsi Manual 1

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1. Logic Gates

AIM:

a) Write verilog code for two input logic gates

b) Verify the code using test bench

PROGRAMME:

module gate2(a,b,x);

input a,b;

output x;

// 2- input Logic gates

1. and(x,a,b);

2. or(x,a,b);

3. not(x,a); // only one input for NOT

4. nand(x,a,b);

5. nor(x,a,b);

6. xor(x,a,b);

7. and a1(x,m,n); // Instance name a1 is specified even though optional

// for logic gates

8. and(x,a,b,c); // 3-Input AND gate

9. xor(x,a,b,c,d); // 4- Input XOR gate

endmodule

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OUTPUT WAVEFORM:

1. and gate

Fig. 1

2. or gate

Fig. 2

3. not gate

Fig. 3

4. nand gate

Fig. 4

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5. nor gate

Fig. 5

6. xor gate

Fig. 6

7. andgate using instance

Fig.7

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8. 3_input andgate

Fig. 8

9. 4_input xorgate

Fig. 9

VIVA VOCE QUESTIONS:

1. What is a Simulator?

2. What are the different levels of abstractions in the Verilog?

3. What are the differences between C language and Verilog?

4. What is the basic component in Verilog programme?

5. What is the difference between wire and reg data types?

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2. Realization of Four Variable Functions

AIM:

a) Realize Four Variable functions


i) f(a,b,c,d) = 0, 1, 3, 5, 7, 11, 15

ii) f(a,b,c,d) = 0, 1, 2, 3, 4, 8, 10, 12, 15

iii) f(a,b,c,d) = 0, 2, 8, 9, 11, 12, 13, 14

iv) f(w,x,y,z) = 0, 1, 3, 5, 7, 11, 15

v) f(w,x,y,z) = 0, 1, 2, 3, 4, 8, 10, 12, 15

vi) f(w,x,y,z) = 0, 2, 8, 9, 11, 12, 13, 14

Minimize the above expressions using Boolean algebra and write the data flow model.

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1. What are the different logic minimization techniques and name them?

2. What is the difference between Minterm and Maxterm?

3. What is the difference between POS and SOP?

4. In logic minimization, which method is preferred if the number of

variables are more than 5?

5. How many Boolean equations are possible with n variables?

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3. Adders & Subtractors

AIM:

a) Write verilog code for halfadder, fulladder, 4-bit parallel adder andfull subtractor.


PROGRAMME:

Half Adder

module halfadder(sum,carryout,in0,in1);

input ino,in1;

output sum,carryout;

1. xor x1(s,a,b);

and a1(c,a,b);

2. assign sum = a b;

assign carryout = (a & b) | (b & c) | (c & a);

endmodule

OUTPUT WAVEFORM:

Fig. 10

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Full - Adder

module fulladder (Cin, x, y, s, Cout);

input Cin, x, y;

output s, Cout;

reg s, Cout;

1. assign s = x y Cin; //concurrent dataflow

assign Cout = (x & y) | (x & Cin) | (y & Cin);

2. always @(x or y or Cin) // Sequential

{Cout, s} = x + y + Cin;

3. xor (z4, x, y); // Using Primitives

xor (s, z4, Cin); // wire z1,z2,z3,z4 ; connecting

wires

and (z1, x, y);

and (z2, x, Cin);

and (z3, y, Cin);

or (Cout, z1, z2, z3);

4. xor (s, x, y, Cin); //3-input xor

and (z1, x, y), (z2, x, Cin),(z3, y, Cin); //multiple instantiations

or (Cout, z1, z2, z3);

endmodule

OUTPUT WAVEFORM:

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Fig. 11

4-bit Full Adder

module adder4bit (carryin, X, Y, S, carryout);

input carryin;

input [3:0] X, Y;

output [3:0] S;

output carryout;

wire [3:1] C;

// Structural Model for 4-bit Full Adder

fulladder stage0 (carryin, X[0], Y[0], S[0], C[1]);

fulladder stage1 (C[1], X[1], Y[1], S[1], C[2]);

fulladder stage2 (C[2], X[2], Y[2], S[2], C[3]);

fulladder stage3 (C[3], X[3], Y[3], S[3], carryout);

endmodule

OUTPUT WAVEFORM:

Fig. 12

N-Bit Adder

module addern (carryin, X, Y, S, carryout);

parameter n=32;input carryin;

input [n-1:0] X, Y;

output [n-1:0] S;

output carryout;

reg [n-1:0] S;

reg carryout;

reg [n:0] C;integer k;

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1. always @(X or Y or carryin)

begin

C[0] = carryin;

for (k = 0; k


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Full Substractor

module fullsub(x1,x2,x3,d,b);

input x1,x2,x3;

output d,b;

assign d= x1^x2^x3;

assign b=(~x1)&((x1^x3)|(x2&x3));

endmodule

OUTPUT WAVEFORM:

Fig. 14


1. What is module instantiation?

2. What are the different ways of association of ports in module

instantiation?

3. Which is the fastest Adder?

4. What are the applications of Adders and Subtractors?

5. Which level of abstraction is suitable for combinational circuits?

6. What is the data type supports for the assignment of data in data flow

modeling?

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4. N-Bit Parallel Adder

AIM:

a) Write the verilog code for N Bit Parallel Adder


PROGRAMME:

N-Bit Adder

module addern (carryin, X, Y, S, carryout);

parameter n=32;

input carryin;

input [n-1:0] X, Y;

output [n-1:0] S;

output carryout;

reg [n-1:0] S;

reg carryout;

reg [n:0] C;

integer k;


begin

C[0] = carryin;

for (k = 0; k


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end


S = X + Y + carryin;

3. always @(X or Y or carryin) // output carryout,

overflow;

begin // reg carryout, overflow;

Sum = {1'b0,X} + {1'b0,Y} + carryin; // reg [n:0] Sum;

S = Sum[n-1:0];

carryout = Sum[n];

overflow = carryout ^ X[n-1] ^ Y[n-1] ^ S[n-1];

end

endmodule

OUTPUT WAVEFORM:

Fig. 15


1. What are the differences between tasks and function declarations?

2. How many values can be returned using functions?

3. How many values can be returned using tasks?

4. Are the tasks and functions synthesizable?

5. Can you call a task in a function?

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5. Multiplexers & Demultiplexers

AIM:

a) Write the verilog code for multiplexers & Demultiplexers


PROGRAMME:

Mux 2x1

module mux2to1 (w0, w1, s, f);

input w0, w1, s;

output f;

reg f;

1. assign f = s ? w1 : w0;

2. always @(w0 or w1 or s)

f = s ? w1 : w0;

3. always @(w0 or w1 or s)

if (s==0)

f = w0;

else

f = w1;

endmodule

OUTPUT WAVEFORM:

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Fig. 16

Mux 4x1

module mux4to1 (w0, w1, w2, w3, S, f);

input w0, w1, w2, w3;

input [1:0] S;

output f;

1. assign f = S[1] ? (S[0] ? w3 : w2) : (S[0] ? w1 : w0);

2. always @(w0 or w1 or w2 or w3 or S)

if (S == 2'b00) // (S == 1)

f = w0;

else if (S == 2'b01) // (S == 2)f = w1;

else if (S == 2'b10) // (S == 3)

f = w2;

else if (S == 2'b11) // (S == 4)

f = w3;

3. always @(W or S)

case (S)

0: f = W[0];

1: f = W[1];

2: f = W[2];

3: f = W[3];

endcase

endmodule

OUTPUT WAVEFORM:

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Fig. 17

Mux 16x1

module mux16to1 (W, S16, f); // Structural Modeling

input [0:15] W;input [3:0] S16;

output f;

wire [0:3] M;

mux4to1 Mux1 (W[0:3], S16[1:0], M[0]);

mux4to1 Mux2 (W[4:7], S16[1:0], M[1]);

mux4to1 Mux3 (W[8:11], S16[1:0], M[2]);

mux4to1 Mux4 (W[12:15], S16[1:0], M[3]);

mux4to1 Mux5 (M[0:3], S16[3:2], f);

endmodule

OUTPUT WAVEFORM:

Fig. 18

DEMULTIPLEXERS

1x4 Demux

module demux1x4(y,s,i);

input i;

input [1:0]s;output [3:0]y;

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wire w0,w1;

not(w0,s0);

not(w1,s0);

and(y[0],i,w0,w1);

and(y[1],i,w1,s0);

and(y[2],i,s1,w0);

and(y[3],i,s1,s0);

endmodule

1x8 Demux

module demux18(i,s,f);

input i;

input[2:0] s;

output[7:0] f;

1. always @(s)

begin

case (s)

3'b000: f[0]=i;

3'b001: f[1]=i;

3'b010: f[2]=i;

3'b011: f[3]=i;

3'b100: f[4]=i;

3'b101: f[5]=i;

3'b110: f[6]=i;

3'b111: f[7]=i;

endcase

end

2. wire[2:0] sb;

assign sb[0]=~s[0];

assign sb[1]=~s[1];

assign sb[2]=~s[2];

assign f[0]=i&sb[2]&sb[1]&sb[0];

assign f[1]=i&sb[2]&sb[1]&s[0];

assign f[2]=i&sb[2]&s[1]&sb[0];

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assign f[3]=i&sb[2]&s[1]&s[0];

assign f[4]=i&s[2]&sb[1]&sb[0];

assign f[5]=i&s[2]&sb[1]&s[0];

assign f[6]=i&s[2]&s[1]&sb[0];

assign f[7]=i&s[2]&s[1]&s[0];

endmodule

OUTPUT WAVEFORM:

Fig. 19


1. How many 2 x 1 multiplexers are required in implementing a n x 1

multiplexer where n is multiple of 2?

2. What are the applications of multiplexers and demultiplexers?

3. How many select lines are required for n x 1 multiplexer?

4. What is other name of behavioral level of abstraction?

5. Why the multiplexer can be called as a Universal element?

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6. Encoders, Priority Encoders & Decoders

AIM:

a) Write the verilog code for encoders, priority encoders & decoders


PROGRAMME:

4to2 Encoder:

Module encoder4to2(W,Y,En);

input En;

input [3:0]W;

output [1:0]Y;

if (En == 0)

Y = 2'b00;

else

case (W)

0: Y = 2'b00;

1: Y = 2'b01;

2: Y = 2'b10;

3: Y = 2'b11;

endcase

endmodule

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OUTPUT WAVEFORM:

Fig. 20

DECODERS

2 to 4 Decoder

module dec2to4 (W, Y, En);

input [1:0]W; // Address lines

input En; // Enable

output [0:3]Y;

reg [0:3]Y;

1. always @(W or En)

case ({En, W})

3'b100: Y = 4'b1000;

3'b101: Y = 4'b0100;

3'b110: Y = 4'b0010;

3'b111: Y = 4'b0001;

default: Y = 4'b0000;

endcase

2. if (En == 0)

Y = 4'b0000;

else

case (W)

0: Y = 4'b1000;

1: Y = 4'b0100;

2: Y = 4'b0010;

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3: Y = 4'b0001;

endcase

3. always @(W or En)

for (k = 0; k


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if (W == k)

Y[k] = En;

2. dec2to4 Dec1 (W[3:2], M[0:3], En);

dec2to4 Dec2 (W[1:0], Y[0:3], M[0]);

dec2to4 Dec3 (W[1:0], Y[4:7], M[1]);

dec2to4 Dec4 (W[1:0], Y[8:11], M[2]);

dec2to4 Dec5 (W[1:0], Y[12:15], M[3]);

endmodule

OUTPUT WAVEFORM:

Fig. 21

PRIORITY ENCODER

3-bit Priority Encoder

module priority (W, Y, z);

input [3:0] W;

output [1:0] Y;

output z;

reg [1:0] Y;

reg z;

1. always @(W)

begin

z = 1;

casex(W)

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4'b1xxx: Y = 3;

4'b01xx: Y = 2;

4'b001x: Y = 1;

4'b0001: Y = 0;

default: begin

z = 0;

Y = 2'bx;

end

endcase

end

2. Y = 2'bx;

z = 0;

for (k = 0; k < 4; k = k+1)

if(W[k])

begin

Y = k;

z = 1;

end

end

endmodule

OUTPUT WAVEFORM:

Fig. 22

8-bit Priority Encoder

module priority_8(q,q3,d);

input [7:0]d;

output q3;

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output [2:0]q;

reg [2:0]q;

reg q3;

always@(d)

begin

q3=1;

if(d[7]) q=3'b111;

if(d[6]) q=3'b110;

if(d[5]) q=3'b101;

if(d[4]) q=3'b100;

if(d[3]) q=3'b011;

if(d[2]) q=3'b010;

if(d[1]) q=3'b001;

if(d[0]) q=3'b000;

else

begin

q3=0;

q=3'b000;

end

end

endmodule

OUTPUT WAVEFORM:

Fig. 23


1. What is an Encoder and Decoder?

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2. What are the applications of Encoder and Decoder?

3. How a priority encoder is different from normal encoder?

4. Why the decoder is widely used than demultiplexer?

5. Design a 3 x 8 line decoder using a 2 x 4 line decoder?

7. 4-Bit Comparator

AIM:

a) Write the verilog code for 4-bit comparator


PROGRAMME:

4-bit Comparator with Equal, Lesser & Greater than functions :

module compare (A, B, AeqB, AgtB, AltB);

input [4:0] A, B;

output AeqB, AgtB, AltB;

reg AeqB, AgtB, AltB;

always @(A or B)

begin

AeqB = 0;

AgtB = 0;

AltB = 0;

if(A == B)

AeqB = 1;

else if (A > B)

AgtB = 1;else

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AltB = 1;

end

endmodule

OUTPUT WAVEFORM:

Fig. 24

2-bit Magnitude Comparator

module magcomp(a0,a1,b0,b1,f0,f1,f2); //Gate level model

input a0,a1,b0,b1;

output f0,f1,f2;

wire x,y,u,v,p,q,r,j,k,c,f,g;

not(x,a0);

not(y,a1);

not(u,b0);

not(v,b1);

and(p,x,y,b0);

and(q,x,b0);

and(r,b0,b1,y);

or(f0,p,q,r);

and(j,a1,b1);

and(k,y,v);or(f1,j,k);

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and(c,a1,u,v);

and(f,a0,u);

and(g,v,x,y);

or(f2,c,f,g);

endmodule

4-bit magnitude comparator using functions

module mc(a,b,l,g,e);

input [3:0]a,b;

output [3:0]l,g,e;

reg [3:0]l,g,e;

always @(a or b)

begin

l=less(a,b);

g=great(a,b);

e=equal(a,b);

end

function [3:0]less;

input [3:0]a,b;

if(a


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if(a>b)

begin

great=a;

$display(a>b);

end

else

great=0;

endfunction

function [3:0]equal;

input [3:0]a,b;

if(a==b)

begin

equal=a;

$display(a==b);

end

else

equal=0;

endfunction

endmodule


1. Write verilog code for 4 bit comparator in gate level model?

2. What are the differences between gate level and data flow models?

3. Explain gate delays using comparator?

4. What are the differences between data flow model and behavioral model?

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8. ALU Modeling

AIM:

a) Write the verilog code for ALU with 16 Operations


PROGRAMME:

module alu_8(out,in1,in2,s);

input [8:0]in1,in2;

input [3:0]s;

output [8:0]out;

reg [8:0]out;

//,flag;

always@(s)

begin

case(s)

4'b0000: out=in1+in2; //8-bit addition

4'b0001: out=in1-in2; //8-bit subtraction

4'b0010: out=in1*in2; //8-bit multiplication

4'b0011: out=in1/in2; //8-bit division

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4'b0100: out=in1%in2; //8-bit modulo division

4'b0101: out=in1&&in2; //8-bit logical and

4'b0110: out=in1||in2; //8-bit logical or

4'b0111: out=!in1; //8-bit logical negation

4'b1000: out=~in1; //8-bit bitwise negation

4'b1001: out=in1&in2; //8-bit bitwise and

4'b1010: out=in1|in2; //8-bit bitwise or

4'b1011: out=in1^in2; //8-bit bitwise xor

4'b1100: out=in1


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Fig. 25

ALU with 8 Operations

module alu(s, A, B, F);

input [2:0] s;

input [3:0] A, B;

output [3:0] F;

reg [3:0] F;

always @(s or A or B)

case (s)

0: F = 4'b0000;

1: F = B - A;

2: F = A - B;

3: F = A + B;

4: F = A ^ B;

5: F = A | B;

6: F = A & B;

7: F = 4'b1111;

endcase

endmodule

ALU using Functions

module alu(a,b,out,s);

input [7:0]a,b;

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input [2:0]s;

output [15:0]out;

reg [15:0]out;

always @(s)

begin

case(s)

3b000:out=add(a,b);

3b001:out=sub(a,b);

3b010:out=mul(a,b);

3b011:out=and1(a,b);

3b100:out=or1(a,b);

3b101:out=xor1(a,b);

3b110:out=rshift(a,b);

3b111:out=lshift(a,b);

endcase

end

function [15:0]add;

input [7:0]a,b;

add=a+b;

endfunction

function [15:0]sub;

input [7:0]a,b;

sub=a-b;

endfunction

function [15:0]mul;

input [7:0]a,b;

mul=a*b;

endfunction

function [15:0]and1;

input [7:0]a,b;

and1=a&b;

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endfunction

function [15:0]or1;

input [7:0]a,b;

or1=a|b;

endfunction

function [15:0]xor1;

input [7:0]a,b;

xor1=a^b;

endfunction

function [15:0]lshift;

input [7:0]a,b;

lshift=ab;

endfunction

endmodule


1. What are the differences between tasks and functions?

2. Write a program for ALU using tasks and functions?

3. What are various delays in behavioral model?

4. What are various delays in data flow model?

5. What is the use of generate statement? Give its syntax?

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9. Memories

AIM:a) Write the verilog code forRAM with 12-bit Address lines:


PROGRAMME:

module ram(addr,w,addw);

input [12:0]addr,addw;

input [15:0]w;

reg [15:0]x[2047:0];

reg [15:0]y;

always @(addw or w)

begin

if(addw>0 &&addw0 && addr


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SRAM with Memory size is 4096 words of 8 bits each:

module sram (Enable,ReadWrite,Address,DataIn,DataOut);

input Enable,ReadWrite;

input [7:0] DataIn;

input [11:0] Address;

output [7:0] DataOut;

reg [7:0] DataOut;

reg [7:0] Mem [0:4095]; //4096 x 8 memory

always @ (Enable or ReadWrite)

if (Enable)

if (ReadWrite)

DataOut = Mem[Address]; //Read

else

Mem[Address] = DataIn; //Write

else DataOut = 8'bz; //High impedance state

endmodule


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10. Latches, Flip-Flops

AIM:

a) Write the verilog code for D, SRLatch, & D, SR Flip-Flop


PROGRAMME:

D Latch

module D_latch(D, Clk, Q);input D, Clk;

output Q;

reg Q;

always @(D or Clk)

if (Clk)

Q = D;

endmodule

OUTPUT WAVEFORM:

Fig. 26

SR latch

module SRlatch(q,q_bar,s,r);

input s,r;

output q,q_bar;

nor(q_bar,r,q);

nor(q,s,q_bar);

endmodule

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OUTPUT WAVEFORM:

Fig. 27

Flip-Flop

SRFF

module rsff(q,s,r,clr,clk);

input s,r,clk,clr;output q;

reg q;

initial q=1'b 0;

always@(r or s or clk or clr)

begin

if(clk==1 && clr==0)

begin

if(s==0 && r==0)

q=q;

else

if((s==0 && r==1) || (s==1 && r==0))

q=s;

else

if(s==1 && r==1)

$display("Undefined operation

performed");

else

q=q;

end

end

endmodule

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OUTPUT WAVEFORM:

Fig. 28

DFF

module flipflop(D, Clock, Resetn, Q);

input D, Clock, Resetn;

output Q;

reg Q;

1. always @(posedge Clock)

Q = D;

2. always @(negedge Resetn or posedge Clock)

if (!Resetn)

Q


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initial

q=1'b 0;

always @(j or j or posedge clk or posedge clr)

begin

if(clr==0)

q=1b0;

else

begin

if(j==0 && k==0)

q=q;

else

if((j==0 && k==1)

q=1b0;

else

if (j==1 && k==0))

q=1b1;

else

if(j==1 && k==1)

q=~q;

qb=~qb;

end

end

endmodule

OUTPUT WAVEFORM:

Fig. 30

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D Flip-flop using 2x1 mux

module muxdff(D0, D1, Sel, Clock, Q);

input D0, D1, Sel, Clock;

output Q;

reg Q;

always @(posedge Clock)

if (!Sel)

Q


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11. Shift Registers and Counters

AIM:a) Write the verilog code for 4-bit shift register & counters


PROGRAMME:

SHIFT REGISTER

4-bit Shift Register

module shift4(R, L, w, Clock, Q);

input [3:0] R;

input L, w, Clock;

output [3:0] Q;

reg [3:0] Q;


if (L)

Q


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8-bit Shift Register

module shift_reg(out,in,load,clk);

output [7:0]out;

input [7:0]in;

input clk;

input load;

reg [7:0]out;

wire [7:0]in;

always@(posedge clk)

begin

if(load)

begin

out


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OUTPUT WAVEFORM:

Fig. 33

Generic N-bit Shift Register

module shiftn(R, L, w, Clock, Q);

parameter n = 16;

input [n-1:0] R;

input L, w, Clock;

output [n-1:0] Q;

reg [n-1:0] Q;

integer k;


if (L)

Q


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COUNTER

Up counter

module upcount(R, Resetn, Clock, E, L, Q);

input [3:0] R;

input Resetn, Clock, E, L;

output [3:0] Q;

reg [3:0] Q;

always @(negedge Resetn or posedge Clock)

if (!Resetn)

Q


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if (L)

Q


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OUTPUT WAVEFORM:


1. Why constructs are not supported in synthesis?

2. What is gate level net list?

3. Write verilog program for counter using instantiation?

4. Explain delay with respect to counters?

5. What is universal shift register?

6. What are the differences between synchronous and asynchronous

counters?

7. What are the components that are needed to construct decade counter?

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12. Parity Generator &Finite State Machine

AIM:

a) Write the verilog code for Parity Generator & Finite state machine


PROGRAMME:

Parity Generatormodule parity_9bit(d,even,odd);

input[0:8]d;

output even,odd;

xor

xe0(e0,d[0],d[1]),

xe1(e1,d[2],d[3]),

xe2(e2,d[4],d[5]),

xe3(e3,d[6],d[7]),

xf0(f0,e0,e1),

xf1(f1,e2,e3),

xh0(h0,f0,f1),

xeven(even,d[8],h0);

not

xodd(odd,even);

endmodule

Gray to Binary Converter

module GTB(out,in);

input [3:0]in;

output [3:0]out;

assign out[3]=in[3];

xor(out[2],out[3],in[2]);

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endmodule

Moore Machine

module moore (Clock, w, Resetn, z);

input Clock, w, Resetn;

output z;

reg [1:0] y, Y;

parameter A = 2'b00, B = 2'b01, C = 2'b10;

always @(w or y)

begin

case (y)

A: if (w == 0) Y = A;

else Y = B;

B: if (w == 0) Y = A;

else Y = C;

C: if (w == 0) Y = A;

else Y = C;

default: Y = 2'bxx;

endcase

end

always @(posedge Clock or negedge Resetn)

begin

if (Resetn == 0)

y


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Finite State Machine Using Moore machine

module moore_fsm (a,clock,z);

input a,clock;

output z;

reg z;

parameter st0=0,st1=1,st2=2,st3=3;

reg[1:0] moore_state;

initial

moore_state=st0;

always @(negedge clock)

begin

case (moore_state)

st0: begin

z=0;

if(a)

moore_state =st1;

end

st1:

begin

z=0;

if(a)

moore_state=st1;

else

moore_state=st2;

end

st2 :

begin

z=0;

if (a)

moore_state =st3;

else

moore_state =st0;

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end

st3:

begin

if (a)

begin

moore_state =st0;

z=1;

end

else

begin

moore_state =st2;

z=0;

end

end

endcase

end

endmodule

OUTPUT WAVEFORM:

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Mealy Machine

module mealy (Clock, w, Resetn, z);

input Clock, w, Resetn ;

output z ;

reg z;

reg y, Y;

parameter A = 0, B = 1;

always @(w or y)

case (y)

A: if (w == 0)

begin

Y = A;

z = 0;

end

else

begin

Y = B;

z = 0;

end

B: if (w == 0)

begin

Y = A;

z = 0;

end

else

begin

Y = B;

z = 1;

end

endcase

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always @(posedge Clock or negedge Resetn)

if (Resetn == 0)

y


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13. WAVEFORM GENERATORS

AIM:

a) Write the verilog code for Wave form Generators


PROGRAMME:

OUTPUT WAVEFORM:


1. Write verilog program to generate square wave of duty cycle with 66.6 %?

2. Write a program to explain pin pin delay?

3. Write a verilog program to generate rectangular wave?

4. What are timing constraints?

5. What are the differences between always and initial statements?

Date post:	03-Apr-2018
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