Copy of Vlsi Manual Final11

8/8/2019 Copy of Vlsi Manual Final11

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VLSI LABORATORY

Department Of Electronics and

Communication Engineering

Paavai College of EngineeringPachal,Namakkal

VLSI LAB SYLLABUS


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SL. No. ExperimentsCycle-I Design and simulation of Combinational Logic Circuit using VHDL

1 Adder2 Multiplexer and Demultiplexer3 Encoder and Decoder4 Multiplier

Cycle-II Design and simulation of Sequential logic circuit using VHDL1 Flip Flops2 Counter3 Shift registers

Cycle-III CMOS Circuit design using Multisim (DC and Transient Analysis)1 CMOS Inverter2 CMOS NAND and NOR Gates3 CMOS D Latch

Cycle-IV FPGA Implementation1 4 bit Adder2 Real Time Clock

TOOLS USED: Modelsim, Xilinx ISE and Multisim.

EX.No:1ADDERDATE :

AIM:

To Simulate VHDL Program for Adder Using ModelSim SE 6.0a tool and verify theoutput.


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APPARATUS REQUIRED:

1. EDA Tool: ModelSim SE 6.0a2. PC : WINDOWS OS

PROCEDURE:

1. Double click on ModelSim SE 6.0a icon in the Desktop.

2. Click fileNew SourceVerilog.

3. Type the program in the work space window.

4. Save the program as .v extension in Work.

5. Go to Compile Type file name Compile Done.

6. Go to Simulate Start SimulationWorkSelect Filename Ok.

7. Go to ViewDebug WindowObjects.

8. Force the input by right clicking the input variables

9. Select all the variablesRight clickAdd To WaveSelected Signals.

10. Go to SimulateRunRun 100ps.

11. Then verify the output.

PROGRAM:

Half Adder(VHDL) using dataflow:

library ieee;

use ieee.std_logic_1164.all;

use ieee.std_logic_arith.all;use ieee.std_logic_unsigned.all;

entity halfadder isport ( a,b : in std_logic;

sum, carry : out std_logic);

end halfadder;

architecture behavioral of halfadder isbegin

sum


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Full Adder(VHDL) using dataflow:

library ieee;use ieee.std_logic_1164.all;

use ieee.std_logic_arith.all;

use ieee.std_logic_unsigned.all;entity fulladder is

port ( a,b,c : in std_logic;

sum, carry : out std_logic);end fulladder;

architecture behavioral of fulladder is

beginsum


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architecture behavioral of xor1 is

begin

y


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y


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component xor1

port(a,b,c: in std_logic; y: out std_logic);

end component;component and1

port(a,b: in std_logic; y: out std_logic);

end component;component or1

port(a,b,c: in std_logic; y: out std_logic);

end component;signal y1,y2,y3:std_logic;

begin

x1: xor1 port map(a,b,c,sum);

a1: and1 port map(a,b,y1);a2: and1 port map(b,c,y2);

a3: and1 port map(c,a,y3);

o1: or1 port map(y1,y2,y3,carry);

end behavioral;

RESULT:

Thus the half adder and full adder program using ModelSim SE 6.0a was stimulated and

output was verified.

EX.No:2Multiplexer and DemultiplexerDATE :

AIM:

To Simulate VHDL Program for Multiplexer and Demultiplexer Using ModelSim SE6.0a tool and verify the output.

ECE DEPARTMENT

PERFORMANCE 25

RECORD 15

VIVA-VOCE 10

TOTAL 50


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APPARATUS REQUIRED:

1. EDA Tool: ModelSim SE 6.0a tool2. PC:WINDOWS OS

PROCEDURE:












PROGRAM:

2 to 1 MUX (VHDL) using dataflow:

library ieee;



use ieee.std_logic_unsigned.all;

entity mux 2 to 1 is

port ( i1,i2,s : in std_logic;

y : out std_logic);end mux 2 to 1;

architecture behavioral of mux 2 to 1 is

begin

y


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end behavioral;

4 to 1 MUX (VHDL) using dataflow:library ieee;

use ieee.std_logic_1164.all;use ieee.std_logic_arith.all;


entity mux 4 to 1 isport ( i1,i2,i3,i4,s1,s2 : in std_logic;

y : out std_logic);

end mux 4 to 1;

architecture behavioral of mux 4 to 1 is

begin

y


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case sel is

when"000"=>

y

yy

y

y

y

y

y

end case;end process;

end behavioral;

1 to 2 DEMUX (VHDL) using dataflow:




entity demux 1 to 2 is

port ( i, s : in std_logic;y1,y2 : out std_logic);

end demux 1 to 2;

architecture behavioral of demux 1 to 2 is

begin

y1


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entity demux 1 to 4 isport ( i,s1,s0 : in std_logic;

y1,y2,y3,y4 : out std_logic);

end demux 1 to 4;

architecture behavioral of demux 1 to 4 is

begin

y1


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end behavioral;

RESULT:

Thus the Multiplexer and Demultiplexer program using ModelSim SE 6.0a was

stimulated and output was verified.

EX.No:3Encoder and DecoderDATE :

AIM:

ECE DEPARTMENT

PERFORMANCE 25

RECORD 15

VIVA-VOCE 10

TOTAL 50


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To Simulate VHDL Program for Encoder and Decoder Using ModelSim SE 6.0a tool and

verify the output.

APPARATUS REQUIRED:

3. EDA Tool: ModelSim SE 6.0a tool

4. PC:WINDOWS OS

PROCEDURE:












PROGRAM:

2 to 4 Decoder:

library ieee;


use ieee.std_logic_arith.all;use ieee.std_logic_unsigned.all;

entity decoder 2 to 4 isport ( e,i1,i2 : in std_logic;

o1,o2,o3,o4 : out std_logic);

end decoder 2 to 4;architecture behavioral of decoder 2 to 4 is

begin

o1


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o2


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o2


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AIM:To Simulate VHDL Program for Multiplier Using ModelSim SE 6.0a tool and verify the

output.

APPARATUS REQUIRED:5. EDA Tool: ModelSim SE 6.0a tool6. PC:WINDOWS OS

PROCEDURE:












PROGRAM:

Unsigned 8 x 4 bit Multiplier:

library ieee;

use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;

entity mult is

port(A : in std_logic_vector(7 downto 0);B : in std_logic_vector(3 downto 0);

RES : out std_logic_vector(11 downto 0));

end mult;architecture archi of mult is

begin


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RES


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AIM:

To Simulate VHDL Program for Flip Flops Using ModelSim SE 6.0a tool and verify the

output.

APPARATUS REQUIRED:1. ModelSim SE 6.0a tool

2. PC:XP/WINDOWS

PROCEDURE:












PROGRAM:

DFF(VHDL) using Behavioral:

library ieee;



entity dff is

port ( d,res,clk : in std_logic;

q : out std_logic);end dff;

architecture behavioral of dff is

begin

process(clk)begin

if(res='0') then q


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elsif clk'event and clk='1'

then q


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port (s,r,clk : in std_logic;

q,qb : buffer std_logic);

end srff;

architecture behavioral of srff is

begin

q


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COUNTERDATE :

AIM:

To Simulate VHDL Program for Counter Using ModelSim SE 6.0a tool and verify the

output.

APPARATUS REQUIRED:

1. ModelSim SE 6.0a tool2. PC:XP/WINDOWS

PROCEDURE:












PROGRAM:

UP COUNTER(VHDL) using Behavioral:




entity upcounter is

port ( clk,clr : in std_logic;q : inout std_logic_vector (2 downto 0));


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end upcounter;

architecture behavioral of upcounter is

begin

process(clk)

variable temp: std_logic_vector (2 downto 0):="000";

begin

if (rising_edge (clk)) thenif clr='0' then

case temp is

when "000"=>temp:="001";

when "001"=>temp:="010";when "010"=>temp:="011";

when "011"=>temp:="100";

when "100"=>temp:="101";


when "111"=>temp:="000";when others=>temp:="000";

end case;

else

temp:="000";end if;

end if;

q


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process(clk)

variable temp: std_logic_vector (2 downto 0):="000";

begin

if (rising_edge (clk)) then

if clr='0' thencase temp is

when "000"=>temp:="111";


when "101"=>temp:="100";

when "100"=>temp:="011";


when "001"=>temp:="000";

when others=>temp:="000";

end case;else

temp:="000";end if;

end if;

q


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begin

if (rising_edge (clk)) then

if clr='0' thencase temp is

when "0000"=>temp:="0001";


when "0011"=>temp:="0100";


when "0110"=>temp:="0111";

when "0111"=>temp:="1000";


end case;

else

temp:="0000";end if;

end if;q


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case temp is

when "000"=>temp:="001";


when others=>temp:="000";

end case;else

temp:="000";

end if;end if;

qtemp:="001";when "001"=>temp:="011";

when "011"=>temp:="101";



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end case;

else

temp:="000";end if;

end if;

q


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EX.No:7SHIFT REGISTERSDATE :

AIM:

To Simulate VHDL Program for Shift Registers Using ModelSim SE 6.0a tool and verifythe output.

APPARATUS REQUIRED:

1. ModelSim SE 6.0a tool2. PC:XP/WINDOWS

PROCEDURE:

12. Double click on ModelSim SE 6.0a icon in the Desktop.13. Click fileNew SourceVerilog.










PROGRAM:

REGISTER:


entity reg is

port(clk : in std_logic;input : in std_logic_vector(15 downto 0);

output : out std_logic_vector(15 downto 0);

ld : in std_logic) ;


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end reg;

architecture behavioral of reg is

begingeneric_register: process(clk, input, ld)

begin

if (rising_edge(clk)) thenif (ld = '1') then

output


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8-bit Shift Register with Positive-Edge Clock, Serial In,and Parallel Out:

library ieee;


entity sipo is

port(C, SI : in std_logic;PO : out std_logic_vector(7 downto 0));

end sipo;

architecture archi of sipo issignal tmp: std_logic_vector(7 downto 0);

beginprocess (C)

beginif (C'event and C='1') then

tmp


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EX.No:8CMOS INVERTERDATE :

AIM:

To Design CMOS Inverter Using Multisim Software and verify the output.

APPARATUS REQUIRED:

1. Multisim Software2. PC:XP/WINDOWS

Inverter Circuit:


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DC Operating Point:

RESULT:

Thus the CMOS Inverter is Designed using Multisim and output was verified.

ECE DEPARTMENT

PERFORMANCE 25

RECORD 15

VIVA-VOCE 10

TOTAL 50


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EX.No:9CMOS NAND and NOR GatesDATE :

AIM:

To Design CMOS NAND and NOR Gates Using Multisim Software and verify theoutput.

APPARATUS REQUIRED:

3. Multisim Software4. PC:XP/WINDOWS

NAND Gate Circuit:


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DC Operating Point:

NOR Gate Circuit:


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DC Operating Point:

RESULT:

Thus the CMOS NAND and NOR Gates is Designed using Multisim and output was

verified.

ECE DEPARTMENTPERFORMANCE 25

RECORD 15

VIVA-VOCE 10

TOTAL 50


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EX.No:10CMOS D LatchDATE :

AIM:

To Design CMOS D Latch using Multisim Software and verify the output.

APPARATUS REQUIRED:

5. Multisim Software

6. PC:XP/WINDOWS

D Latch with NAND Gate Circuit:


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Circuit:

DC Operating Point:


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RESULT:

Thus the CMOS D Latch is Designed using Multisim and output was verified.

ECE DEPARTMENT

PERFORMANCE 25

RECORD 15

VIVA-VOCE 10

TOTAL 50


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EX.No:114 BIT ADDERDATE :

AIM:

To Study the synthesis of a VHDL Program Using tools in XILINX ISE 8.2i Software.

APPARATUS REQUIRED:

1. XILINX ISE 8.2i tool2. PC:XP/WINDOWS

PROCEDURE:

1. Double click on XILINX ISE 8.2i icon in the Desktop.

2. Click fileNew project Enter the project name & Location, Select top level source

type as HDL. Click NEXT.

3. In the device property window select the details:

4. Click NextNEXTNEXTFINISH.

5. Click Project New source Select Verilog module, Enter the file Name

NEXTNEXT FINISH.

6. Type program in the work space window.

7. Save the program.

8. Double click the synthesis XST in the process window.

9. Click view RTL schematic in the synthesis XST.

10. Click view Technology schematic in the synthesis XST.

11. Verify the schematic diagram.

PROGRAM:



entity fadd4 is

port(a,b : in std_logic_vector(3 downto 0);

cin : in std_logic;s : out std_logic_vector(3 downto 0);

cout : out std_logic);

end fadd4;


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architecture structural of fadd4 iscomponent fulladd

port(a,b,cin : in std_logic;

sum,cout : out std_logic);

end component;signal c1,c2,c3: std_logic;

begin

a0: fulladd port map (a(0),b(0),cin,s(0),c1);

a1: fulladd port map (a(1),b(1),c1,s(1),c2);

a2: fulladd port map (a(2),b(2),c2,s(2),c3);a3: fulladd port map (a(3),b(3),c3,s(3),cout);

end structural;

RESULT:

Thus the 4 Bit Adder program using XILINX ISE 8.2i Software was stimulated andoutput was verified.

ECE DEPARTMENTPERFORMANCE 25

RECORD 15

VIVA-VOCE 10

TOTAL 50


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EX.No:12Real Time ClockDATE :

AIM:To Study the synthesis of a VHDL Program Using tools in XILINX ISE 8.2i Software.

APPARATUS REQUIRED:

3. XILINX ISE 8.2i tool

4. PC:XP/WINDOWS

PROCEDURE:

12. Double click on XILINX ISE 8.2i icon in the Desktop.

13. Click fileNew project Enter the project name & Location, Select top level

source type as HDL. Click NEXT.

14. In the device property window select the details:

15. Click NextNEXTNEXTFINISH.

16. Click Project New source Select Verilog module, Enter the file Name

NEXTNEXT FINISH.

17. Type program in the work space window.

18. Save the program.

19. Double click the synthesis XST in the process window.

20. Click view RTL schematic in the synthesis XST.

21. Click view Technology schematic in the synthesis XST.

22. Verify the schematic diagram.

PROGRAM:

library ieee;



entity rtc_im is

port(reset,clk_4m,load,control:in std_logic;

rtc_seg:out std_logic_vector(7 downto 0);rtc_dis:out std_logic_vector(5 downto 0));


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end rtc_im;

architecture behavioral of rtc_im issignal tc,tc1,tc2,tc3,tc4,tc5,tc6,enable:std_logic;

signal sec1,sec2,min1,min2,hr1,hr2: std_logic_vector(3 downto 0);

signal sec1_rg:std_logic_vector(3 downto 0);signal sec2_rg:std_logic_vector(3 downto 0);

signal min1_rg:std_logic_vector(3 downto 0);

signal min2_rg:std_logic_vector(3 downto 0);signal hr1_rg:std_logic_vector(3 downto 0);

signal hr2_rg:std_logic_vector(3 downto 0);

signal pulsegen:std_logic_vector(21 downto 0);

signal sel:std_logic_vector(2 downto 0);signal mout:std_logic_vector(3 downto 0);

signal sgout:std_logic_vector(7 downto 0);

signal dis_sig:std_logic_vector(5 downto 0);

signal cnk2:std_logic_vector(2 downto 0);begin

--*************************** pulse generator ******************p0:process(reset,clk_4m,pulsegen)

begin

if (reset = '1') then

pulsegen


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if (sec1_rg = "1001")then

sec1_rg


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min1_rg


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hr1_rg


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end if;

end if;

end if;else

if (tc6 = '1') then

hr2_rg


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"10000000" when mout = "1000" else

"10011000" when mout = "1001" else

"11111111" ;dis_sig

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